Virtual first in first out direct memory access device

Abstract

A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or saves data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected with the DMA unit and the processor respectively. A processor reads data from or writes data into the virtual FIFO via the virtual port and the DMA unit.

Description

This application claims the benefit of Taiwan applications, Serial No. 92134466, filed Dec. 5, 2003, and Serial No. 93137250, filed Dec. 2, 2004 the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a direct memory access (DMA) device, and more particularly to a virtual first in first out (FIFO) DMA device.

2. Description of the Related Art

Referring to FIG. 1, a block diagram of a conventional electronic device during UART transmitting. To transmit a first data through a UART unit 110, the higher layer software task 102 firstly calls a UART driver and makes the UART driver fill the first data into a buffer 104, which can be a ring buffer or a double buffer. When the first data has been completely filled into the buffer 104, the UART driver updates a buffer pointer set by the UART driver to a next address. Through the DMA unit 106, the first data stored in the buffer 104 is transferred to and stored in the UART first in first out (FIFO) unit, wherein the UART unit 110 serially outputs the first data. Here, the data transferring between the buffer 104 and the UART FIFO unit 108 can be performed by either the DMA unit 106 or a processor. Normally, the DMA unit 106 is more efficient in transferring data.

In a complicated electronic device, however, it is possible that multiple higher software layer tasks 102A and interrupt service routines (ISR) 112 might use the same UART unit 110 to transmit data, as shown in FIG. 2. Under such circumstance, the data stored in the buffer 104 might be overwritten, resulting in data error. If the ISR 112 has a second data that needs to be transmitted by the UART unit 110 when the first data of the higher layer software task 102A is being filled into the buffer 104, the ISR 112 calls the UART driver to store the second data into the buffer 104. Not until the first data of the higher layer software task 102A has been completely filled into the buffer 104 does the UART driver start to update the buffer pointer. Consequently, the second data is written into the buffer 104 according to original buffer pointer, and therefore the first data, which has been saved in the buffer 104, is overwritten. After the UART driver has written the second data of the ISR 112 into the buffer 104, the higher layer software task 102A continues to save the first data into the buffer 104 and therefore will overwrite part of the second data. Accordingly, data loss between the first data and the second data, saved in the buffer 104, will result in data error.

There are two conventional methods of solving the data error in the buffer 104. The first method is disabling the ISR 112 to prevent the occurrence of data error before the higher layer software task 102A starts to call the UART driver. However, since the ISR 112 might need to be executed in real-time, if the system fails to process the ISR 112 promptly, it will cause system error.

The second method involves the use of two buffers. Referring to FIG. 3, a block diagram of using two buffers for UART transmitting is shown. The second data of the ISR 112 is saved in the buffer 104A, while the first data of the higher layer software task 102A is saved in the buffer 104B. By controlling the multiplexer 114, the first data and the second data are alternately transferred to the UART FIFO unit 108 and are further transmitted out by the UART unit 110. However, this method requires more memory space for the buffer and the control of the UART driver is more complicated.

Apart from data loss and data error that might occur during UART transmitting, the conventional electronic device also has several problems during UART receiving. Referring to FIG. 4, a block diagram of a conventional electronic device during UART receiving. After a UART unit 410 receives a third data, the third data is temporarily stored in a UART FIFO unit 408, and then a DMA unit 406 will transfer the third data to a buffer 404. After the DMA unit 406 has transmitted the data of a pre-set length to the buffer 404, the DMA unit 406 notices a processor 416 to read the data stored in the buffer 404. For example, whenever the DMA unit 406 transmits data of 500 bytes to the buffer 404, the DMA unit 406 notices the processor 416 to read the data stored in the buffer 404.

However, since the length of the third data received by the UART unit 410 is unpredictable, the DMA unit 406 is unable to determine whether the third data has been completely received. For example, assume the length of the third data is 700 bytes. After the DMA unit 406 transmits the first 500 bytes of the third data, the DMA unit 406 notices the processor 416 to read the data stored in the buffer 404. However, after the DMA unit 406 transmits the other 200 bytes of the third data, the DMA unit 406 will not notice the processor 416 to read the data stored in the buffer 404 because the length of received data (200 bytes of the third data) does not reach the pre-set length and the DMA unit 406 can not determine that the third data has been completely received. Therefore, the processor 416 has to periodically detect the status of the UART FIFO unit 408 so as to determine whether the UART FIFO unit 408 is empty (because the data has been moved to buffer 404). Besides, the processor 416 further determines whether the UART FIFO unit 408 has been in the empty status for a predetermined period. If so, it represents that the data has been received completely. At this time, the processor 406 reads the data stored in the buffer 404 to process the data.

Before the processor 416 detects the status of the UART FIFO unit 408, the processor 416 has to disable the DAM unit 406 first to prevent incorrect detection due to the moving of data by the DAM unit 406. Before disabling the DAM unit 406, the UART unit 410 has to be disabled first and sends a signal to notice the transmitting end to cease the transmission of data.

However, if data happens to be transmitted to the UART unit 410 when the DMA unit 406 is being disabled, the DMA unit 406 is unable to transfer data from the UART FIFO unit 408 to the buffer 404. Under this circumstance, the data stored in the UART FIFO unit 408 might overflow, causing data loss. To prevent data loss, a buffer of at least 16 bytes must be reserved for the UART FIFO unit 418.

On the other hand, if the processor 416 is used to transfer data from the UART FIFO unit 408 to the buffer 404, the UART FIFO unit 408 must be enlarged lest the processor 416 might be frequently interrupted in order to process data transferring because the UART FIFO unit 408 is easily filled up. However, this will further increase the cost.

To summarize, during UART transmitting, the UART driver of a conventional electronic device might be unable to update the buffer pointer promptly, resulting in data error as parts of data are overwritten. During UART transmitting, (1) the processor 416 must periodically detect the status of the buffer 404 and the UART FIFO unit 408, hence reducing the efficiency of the processor 416; (2) when the DMA unit 406 is disabled, an extra buffer of 16 bytes must be reserved for the UART FIFO unit 408 to prevent the UART FIFO unit 408 from data overflow. It will consequently increase the cost and the chip size of the UART FIFO unit 408.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a virtual FIFO DMA device, which promptly updates pointer value so as to prevent data error caused by data overwriting during UART transmitting. According to the invention, the UART FIFO unit does not need to reserve a space of 16 bytes during UART receiving, which reduces the cost and the chip size of the UART FIFO unit.

According to the object of the invention, a virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO is provided. The virtual FIFO DMA device includes a DMA unit, a virtual FIFO controller and a virtual port. The DMA unit, which is electrically connected with the UART unit and the virtual FIFO respectively, transfers data between the UART unit and the virtual FIFO. The virtual FIFO controller, which is electrically connected with the DMA unit, has a read pointer and a write pointer. When DMA unit reads data from or writes data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of read pointer or write pointer. The virtual port is electrically connected with the DMA unit and the processor respectively. The processor reads data from or writes data into the virtual FIFO through the virtual port and the DMA unit.

According to another object of the invention, an electronic device is provided. The electronic device includes a virtual FIFO DMA device, a UART unit, a virtual FIFO and a processor. The virtual FIFO DMA device has a DMA unit, a virtual port and a virtual FIFO controller, wherein the virtual port is electrically connected with the DMA unit, while the virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. The UART unit is electrically connected with the DMA unit, while the virtual FIFO is electrically connected with DMA unit. The DMA unit transfers data between the UART unit and the virtual FIFO. When DMA unit reads data from or writes data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. The processor, which is electronically connected with the virtual port, reads data from or writes data into the virtual FIFO through the virtual port and the DMA unit.

Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional electronic device during UART transmitting;

FIG. 2 is a diagram showing the status when plural higher layer software tasks and interrupt service routines use the same UART unit to transmit data;

FIG. 3 is a block diagram of using two virtual FIFOs for UART transmitting;

FIG. 4 is a block diagram of a conventional electronic device during UART receiving;

FIG. 5 is a block diagram of a virtual FIFO DMA device according to a preferred embodiment of the invention;

FIG. 6 is a system block diagram of an electronic device using the virtual FIFO DMA device of the invention when the UART unit performs data receiving; and

FIG. 7 is a system block diagram of an electronic device using the virtual FIFO DMA device of the invention when the UART unit performing data transmitting.

DETAILED DESCRIPTION OF THE INVENTION

Different from the conventional technique, the invention applies a certain area of the memory as a virtual FIFO for replacing the UART FIFO unit in the conventional electronic device. Therefore, additional UART FIFO unit is not required in the UART unit of the invention. Consequently, the cost and chip size of the UART unit can be reduced. By the invention, the processor of the electronic device can access the virtual FIFO through the virtual FIFO DMA device with no data error caused by data overwriting.

Referring to FIG. 5 a block diagram of a virtual FIFO DMA device according to a preferred embodiment of the invention is shown. The virtual FIFO DMA device 502 according to the invention is applied in an electronic device 500. For example, the electronic device 500 is a mobile phone. The electronic device 500 includes a processor 510, a UART unit 512 and a virtual FIFO 514. The virtual FIFO DMA device 502 includes a DMA unit 504, a virtual FIFO controller 506 and a virtual port 508. The DMA unit 504, which is respectively electrically connected with the UART unit 512 and the virtual FIFO 514, is for transferring data between the UART unit 512 and the virtual FIFO 514. The virtual FIFO controller 506, which is electrically connected with the DMA unit 504, has a read pointer RP and a write pointer WP, for respectively pointing to a data reading location and a data writing location. When the DMA unit 504 reads data from or writes data into the virtual FIFO 514, the virtual FIFO controller 506 correspondingly changes the value of the read pointer RP or the write pointer WP. The virtual port 508 is respectively electrically connected with the DMA unit 504 and the processor 510, as an accessing interface thereof. The processor 510 reads data from or writes data into the virtual FIFO 514 through the virtual port 508 and the DMA unit 504.

Referring to FIG. 6, a system block diagram of an electronic device 500 using the virtual FIFO DMA device 502 of the invention when the UART unit 512 performs data receiving is shown. In the electronic device 500, the UART unit 512 is electrically connected with the DMA unit 504; the virtual FIFO 514 is electrically connected with the DMA unit 504; and the processor 510 is electrically connected with the virtual port 508. The UART unit 516 has a data register 516 whose memory is one byte for instance. After the electronic device 500 is started and before the UART unit 512 is enabled, the processor 510 sets a certain area of a memory as a virtual FIFO and enables the FIFO DMA device 502. The processor 510 further sends a DMA setting signal DMA_set to set the initial value of the write pointer WP and the read pointer RP to the initial location of the area.

After that, the processor 510 enable UART unit 512. When the UART unit 512 receives data up to one byte, the UART unit 512 sends a request signal DMA_req to request the DMA unit 504 to transfer (write) the data from the data register 516 to the location where the write pointer WP points in the virtual FIFO 514. Meanwhile, the DMA unit 504 sends a write notice signal Winc to the virtual FIFO controller 506 so that the virtual FIFO controller 506 correspondingly changes the value of the write pointer WP.

Besides, the processor 510 can read data stored in the virtual FIFO 514 through the virtual port 508 and the DMA unit 504 at any time. The virtual port 508 has a peripheral device address and the processor 510 takes the virtual FIFO DMA device 502 as a peripheral device. When the processor 510 is going to read the data in the virtual FIFO 514, the processor 510 sends a reading signal to the virtual port 508, so that the virtual port 508 sends a DMA read request REQ_R to the DMA unit 504. At this time, the DMA unit 504 reads the virtual FIFO 514 to read a first data DATA(1) according to the read pointer RP. The DMA unit 504 further sends a read notice signal Rinc to the virtual FIFO controller 506, so that the virtual FIFO controller 506 changes the value of the read pointer RP accordingly. After that, the DMA unit 504 transmits the first data DATA(1) to the virtual port 508, which in turn transmits the first data DATA(1) to the processor 510.

The virtual FIFO controller 506 further has a flow control function. The virtual FIFO controller 506 disables all write instructions and instructs the UART unit 512 to notice the transmitting end to cease the transmission of data when the virtual FIFO 514 is substantially full and disables all read instructions when the virtual FIFO 514 is substantially empty. The virtual FIFO 514 can additionally reserve a buffer of 16 bytes to accomplish the request where the DMA unit 504 still needs to transfer data from the UART unit 512 to the virtual FIFO 514 when the virtual FIFO 514 is almost full but the transmitting end has not yet ceased the transmission of data.

In the embodiment, the processor 510 accesses the virtual FIFO 514 through the UART unit 512. The UART unit 512 writes data to the virtual FIFO 514 whenever the UART unit 512 receives one byte data. Therefore, despite that the UART unit 512 is unable to predict the length of the data received and that the DMA unit 504 is unable to determine whether the data having a plurality of bytes has been completely received, the processor 510 can still access the virtual FIFO 514 through the UART unit 512 without disabling the DMA unit 504. Furthermore, by setting a certain area of the memory as the virtual FIFO in the embodiment, the UART unit 512 does not require the UART FIFO unit of 16 bytes and the chip size of the UART unit 512 is thus reduced.

Referring to FIG. 7, a system block diagram of an electronic device 500 when the UART unit 512 performs data transmitting is shown. In the electronic device 500, when data of the processor 510 need to be transmitted by the UART unit 512, the processor 510 transmits a transmission instruction and a data-to-be-transmitted data DATA(2) to the virtual port 508. The virtual port 508 sends a write request REQ_W to the DMA unit 504, so that the DMA unit 504 writes the DATA(2) to the virtual FIFO 514 according to the value of the write pointer WP. Meanwhile, the DMA unit 504 sends the write notice signal Winc to the virtual FIFO controller 506 for the virtual FIFO controller 506 to correspondingly change the value of the write pointer WP. After that, the DMA unit 504 sequentially transfers the data from the virtual FIFO 514 to the data register 516 of the UART unit 512.

Writing data into the virtual FIFO 514 by the processor 510, including the writing of data performed under the instruction of the higher layer software task and the ISR, is completed by the virtual FIFO DMA device 502. No matter the writing of data is instructed by the higher layer software task or by the ISR, the processor 510 writes data into the virtual FIFO 514 through the virtual port 508 and the DMA unit 504; meanwhile, the DMA unit 504 sends a writing notice signal Winc to instruct the virtual FIFO controller 506 to update the value of the write pointer WP. According to the conventional method, the UART driver cannot update the buffer pointer until the higher layer software task or the ISR has completed writing the data. Compared with the conventional method, the virtual FIFO controller 506 according to the invention can promptly update the value of the write pointer WP while writing data with no data error caused by data overwriting.

Through the virtual FIFO DMA device according to the invention, the UART driver controls the virtual FIFO as one FIFO unit. The complexity of the UART driver is therefore reduced. Moreover, compared with the conventional method, the invention sets a certain area of memory as the virtual FIFO and utilizes the virtual FIFO DMA device to access the virtual FIFO. Therefore, extra UART FIFO unit is not required, and the chip size of the UART unit can be further reduced.

While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims

1. A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO, the virtual FIFO DMA device comprising: a DMA unit, being respectively electrically connected with the UART unit and the virtual FIFO, for transferring data between the UART unit and the virtual FIFO; a virtual FIFO controller, being electrically connected with the DMA unit, having a read pointer and a write pointer, wherein when the DMA unit reads data from or writes data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of read pointer or write pointer; and a virtual port, being respectively electrically connected with the DMA unit and the processor, wherein the processor reads data from or writes date into the virtual FIFO through the virtual port and the DMA unit.

2. The virtual FIFO DMA device according to claim 1, wherein the virtual FIFO controller has a read pointer and a write pointer for respectively pointing to a data reading location and a data writing location of the virtual FIFO, the UART unit has a data register, when the UART unit receives data up to a particular amount, the UART unit sends a request signal to request the DMA unit to transfer the data from the data register to the location where the write pointer WP points in the virtual FIFO, the DMA unit further sends a write notice signal to the virtual FIFO controller so that the virtual FIFO controller correspondingly changes the value of the write pointer; wherein the virtual port has a peripheral device address and the processor takes the virtual FIFO DMA device as a peripheral device, when the processor reads the data in the virtual FIFO, the processor sends a reading signal to the virtual port and the virtual port sends a DMA read request to the DMA unit, the DMA unit reads the virtual FIFO to get a first data according to the read pointer, the DMA unit further sends a read notice signal to the virtual FIFO controller to change the value of the read pointer accordingly, the DMA unit transmits the first data to the virtual port, which in turn transmits the first data to the processor.

3. The virtual FIFO DMA device according to claim 1, wherein the electronic device is a mobile phone.

4. The virtual FIFO DMA device according to claim 1, wherein the virtual FIFO controller has a read pointer and a write pointer for respectively pointing to a data reading location and a data writing location of the virtual FIFO, the UART unit has a data register, when data of the processor need to be transmitted from the UART unit, the processor transmits a transmission instruction and a data-to-be-transmitted data to the virtual port, the virtual port sends a write request to the DMA unit, and the DMA unit writes the data-to-be-transmitted data to the virtual FIFO according to the value of the write pointer, the DMA unit sends a write notice signal to the virtual FIFO controller for the virtual FIFO controller to correspondingly change the value of the write pointer, the DMA unit sequentially transfers the data from the virtual FIFO to the data register of the UART unit.

5. The virtual FIFO DMA device according to claim 1, wherein the virtual port has a peripheral device address and the processor takes the virtual FIFO DMA device as a peripheral device, when the processor reads data from the virtual port, the virtual port sends a DMA read request to the DMA unit, which in turn gets a first data from the virtual FIFO according to the read pointer, the virtual FIFO controller changes the value of the read pointer accordingly, the DMA unit transmits the first data to the virtual port, which in turn transmits the first data to the processor; when the processor transmits a to-be-written second data to the virtual port, the virtual port sends a DMA write request to the DMA unit, which in turn writes the second data into the virtual FIFO according to the write pointer, the virtual FIFO controller changes the value of the write pointer.

6. The virtual FIFO DMA device according to claim 1, wherein the virtual FIFO controller further has a flow control function, and the virtual FIFO controller disables all write instructions when the virtual FIFO is substantially full, and disables all read instructions when the virtual FIFO is substantially empty.

7. An electronic device, comprising: a virtual FIFO DMA device, comprising: a DMA unit; a virtual port, being electrically connected with DMA unit; and a virtual FIFO controller, being electrically connected with the DMA unit, having a read pointer and a write pointer; a UART unit, being electrically connected with the DMA unit; a virtual FIFO, being electrically connected with the DMA unit, wherein the DMA unit transfers data between the UART unit and the virtual FIFO, and the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer when the DMA unit reads data from or writes data into the virtual FIFO; and a processor, being electrically connected with virtual port, wherein the processor reads data from or writes data into the virtual FIFO through the virtual port and the DMA unit.

8. An electronic device according to claim 7, wherein the UART unit has a data register, and data of the data register is transferred to the virtual FIFO by the DMA unit when the data register is full.

9. The virtual FIFO DMA device according to claim 8, wherein the electronic device is a mobile phone.

10. The virtual FIFO DMA device according to claim 7, wherein the virtual port has a peripheral device address, and the processor takes the virtual FIFO DMA device as a peripheral device, when the processor reads data from the virtual port, the virtual port sends a DMA read request to the DMA unit, which in turn reads a first data from the virtual FIFO according to the read pointer, the virtual FIFO controller changes the value of the read pointer accordingly, the DMA unit transmits the first data to the virtual port, which in turn transmits the first data to the processor; when the processor transmits a to-be-written second data to the virtual port, the virtual port sends a DMA write request to the DMA unit, which in turn writes the second data into the virtual FIFO according to the write pointer, the virtual FIFO controller changes the value of the write pointer.

11. The virtual FIFO DMA device according to claim 7, wherein the virtual FIFO controller further has a flow control function, and the virtual FIFO controller disables all write instructions when the virtual FIFO is substantially full and disables all read instructions when the virtual FIFO is substantially empty.

12. A virtual first in first out (FIFO) direct memory access (DMA) method applied in a virtual FIFO DMA device of an electronic device, the electronic device having a processor, a UART unit and a virtual FIFO, the FIFO DMA device having a DMA unit, a virtual FIFO controller, and a virtual port, the virtual FIFO controller having a read pointer and a write pointer, the UART unit having a data register, the virtual port having a peripheral device address, and the processor taking the virtual FIFO DMA device as a peripheral device, the virtual FIFO DMA method comprising: when the UART unit receives data up to a particular amount, the UART unit sending a request signal to request the DMA unit to transfer the data from the data register to the location where the write pointer WP points in the virtual FIFO, the DMA unit further sending a write notice signal to the virtual FIFO controller so that the virtual FIFO controller correspondingly changes the value of the write pointer; when the processor reads the data in the virtual FIFO, the processor sending a reading signal to the virtual port and the virtual port sending a DMA read request to the DMA unit, the DMA unit reading the virtual FIFO to get a first data according to the read pointer, the DMA unit further sending a read notice signal to the virtual FIFO controller so that the virtual FIFO controller changes the value of the read pointer accordingly, the DMA unit transmitting the first data to the virtual port, which in turn transmits the first data to the processor; when data of the processor need to be transmitted by the UART unit, the processor transmitting a transmission instruction and a data-to-be-transmitted data to the virtual port, the virtual port sending a write request to the DMA unit and the DMA unit writing the data-to-be-transmitted data to the virtual FIFO according to the value of the write pointer, the DMA unit sending a write notice signal to the virtual FIFO controller for the virtual FIFO controller to correspondingly change the value of the write pointer, the DMA unit sequentially transferring the data from the virtual FIFO to the data register of the UART unit.

13. The virtual FIFO DMA device according to claim 12, wherein the electronic device is a mobile phone.