Patent Application
20060112212
1. Field of the Invention
The invention relates to a virtual machine computer system being capable of running multiple guest operating systems concurrently by virtualization of a host machine. In this connection commonly operating systems of several guests are handled on the hardware of the host machine under the host operating system by means of a so-called virtual machine monitor and using the region ID virtual memory option.
2. Background Art
A computer system generally consists of input/output devices, memory devices and a central processing unit (CPU). In the CPU a memory management unit (MMU) is implemented which in the context of host/guest systems uses the principle of virtual addressing. Actually all current operating systems installed and running on standard CPUs use this principle of virtual addressing to protect the memory of different processes against accesses from outside of the currently running process.
To make use of the virtual addressing facility the MMU has to have a knowledge of both the virtual addresses and the corresponding physical addresses involved in a process, i.e. the MMU disposes of a reference list with a “translation” between each virtual address and each corresponding physical address. One of these translations is always valid for a whole memory area—a so called “memory page”.
The part of the MMU which contains said translations is called translation look-aside buffer (TLB).
To visualize the entries and use of the TLB reference is made to the accompanying drawing of
Now as can be seen from
In the above mentioned translation look-aside buffer (TLB) 14 of the MMU 9 one can find a number of entries 14.1, 14.2, each of which is filled with a translation for a particular memory page, e.g. for process #1 the entry 14.1 comprises the virtual address 111 and the according physical address 211. Accordingly entry 14.2 comprises the virtual address 112 of the virtual address space 12 of process #2 and the according physical address 212. The same applies for all entries 14n with the n-th entry comprising a virtual address 11n and a physical address 21n. The physical addresses 211, 212, . . . 21n point to the physical address space 15.
In the prior art when the host operating system running on the CPU 8 switches from e.g. process #1 of guest system 1 to process #2 of guest system 2, i.e. the operating system makes a so-called context switch, the TLB 13 is cleared of all translations (virtual address 111, physical address 211) of the first process #1 to ensure that the second process #2 is not able to access data from the first process #1. Processing this clearage and the refill of the TLB is expensive and time-consuming leading to a considerable deterioration of the whole system performance.
To avoid this problem current CPUs use a mechanism to accelerate context switches, which is called virtual region/virtual address space ID/number. To realize this mechanism the TLB entries 14 are added with a further value which is a region identification value (region ID) 16. The operating system running on the CPU 8 of the host computer 3 ensures that to each process #1, #2, . . . #n a region ID 16.1, 16.2 . . . 16.n is assigned which is unique within the computer system. Further on the CPU 8 is provided with a region register 17 which contains the region ID 16 of the process currently running on the CPU 8.
Now in case of a context switch it is only necessary to update the region register 17 with a region ID 16 of the process that has to be run. Doing so only the TLB entries 14 corresponding to the new process are valid and a safe protection against the memory of the other processes is achieved. By means of this virtual region/virtual address space mechanism so called flushes, i.e. clearing translations for virtual addresses, of the TLB 8 can be saved. If one process receives control again it is probable that translations, i.e. TLB entries 14 needed by this process are still available.
In
In a virtual machine monitor (VMM) 4 environment multiple operating systems (guests) are running concurrently. When running the guest operating systems 1, 2 in a completely virtualized computer environment by the VMM 4, however, the latter regularly has to flush all TLB entries 14 when switching from one guest operating system to another. Otherwise it is not ensured that the memory of one guest operating system does not accidentally be accessed by another guest operating system by using the same region ID in the virtual environment.
Starting from the aforementioned problems of the prior art the object of the invention is to provide a virtual machine computer system for running guest operating system processes on a central processing means fully virtualized by the VMM with improved performance by avoiding the necessity to flush all TLB entries when switching from one guest operating system to another.
This object is achieved by a novel structure of the region ID which is composed of on the one hand a guest allocated bit field of a field size less than the maximum field size of the region ID and in which a guest allocated region sub ID is entered by a guest system and on the other hand a guest system identifier bit field in which an identification value uniquely identifying an associated guest system is entered by the VMM. By this structure an overall region ID is created which is unique throughout the overall computer system. This means that no flushing of the TLB 13 is necessary as each region ID is now unambiguously assigned to each virtualized guest system 1, 2.
Further features, details and advantages of the invention are disclosed in the following description in which an embodiment of the subject matter of the invention is described in more detail with reference to the accompanying drawings.
The basic handling of the virtual region/virtual address space concept is fully explained with reference to
Now in
As can be seen by comparing
Since the host operating system uses region Ids beginning from around zero in ascending order the value “00” of the guest system identifier is reserved for the host operating system. By doing so the host operating system can use up to 218 different region Ids without interfering with the region Ids used for the guest operating systems.
By running processes in a virtualized environment on Intel® Itanium® processors, e. g. under the Intel® IA-64 process architecture, the number of implemented bits can be found in a returned field named “rid_size” in the return value “vm_info—2” of the function called “PAL_VM_SUMMARY”. Said function is part of the processor abstraction layer PAL which is implemented as firmware for the Intel® Itanium® IA-64 processor. Reference is made to the “Intel® IA-64 architecture software developer's manual volume 2: IA-64 system architecture” revision 1.1, July 2000, pages 11-107, 11-108. By virtualizing this function each guest system 1, 2 only uses the foreshortened maximum field size of the region sub ID which is returned by aforesaid function “PAL_VM_SUMMARY” as an unsigned 8-bit integer denoting the number of bits implemented in the RR.rid field.
With a fully implemented 24 bits wide region register of the host system and a restricted region register given to the guest systems with a region sub ID which is 18 bits wide at maximum 26−1=63 guest systems can be unambiguously served by a host system in a virtualized environment. The subtraction of 1 is based on the fact that one identification value is reserved for the host system (value “00” in the identifier bit field 19 of
The diagrammatic representation of
Under the concept of guest system identifier bit field 19 the identification value 191 of that WINDOWS® guest operating system 1 could be “01” whereas the host operating system 3 carries an identification value 191 of “00”.
The processor abstraction layer PAL of the CPU 8 is denoted as 100 in
Finally it is to be noted that the VMM 4 may include a host operating system functionality, i.e. the VMM 4 can operate as so-called hostless VMM.
