Virtual on-chip memory

Abstract

A “virtual on-chip memory” that provides advantages as compared to an on-chip memory that utilizes a cache. In accordance with the invention, when a CPU attempts to access a memory address that is not on-chip, the access is aborted and the abort is handled at a page level. A single page table is utilized in which each entry constitutes an address in the virtual address space that will be mapped to a page of on-chip memory. The CPU obtains the missing data, updates the page table, and continues execution from the aborted point. Because aborts are handled at the page level rather than the line level, the virtual on-chip memory is less expensive to implement than a cache. Furthermore, critical real-time applications can be stored within a non-virtual portion of the memory space to ensure that they are not stalled.

Description

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention.

FIG. 1 depicts basic elements of an example System-on-a-Chip using Virtual On-Chip Memory in accordance with an embodiment of the present invention.

FIG. 2 depicts the basic elements of an example System-on-a-Chip using Virtual On-Chip Memory and introduces further complexities in accordance with an embodiment of the present invention.

FIG. 3 illustrates a flowchart of a method for reading information from a Virtual On-Chip Memory and responding to a situation where the information is not presently located in the paged memory in accordance with an embodiment of the present invention.

FIG. 4 depicts a virtual memory addressing scheme where an address into the virtual address space is used to consult the page table and find the corresponding paged area of memory in which the requested information is kept in accordance with an embodiment of the present invention.

FIG. 5 depicts the basic elements of an example System-on-a-Chip using Virtual On-Chip Memory and further shows a data bus which is used by a processor in order to retrieve information from a data stream that corresponds to a particular location within a virtual address space in accordance with an embodiment of the present invention.

Claims

1. A method of processing requests by one or more processors for information from an on-chip memory, wherein the on-chip memory comprises data from a subset of a virtual address space, the method comprising: receiving a request for information within the virtual address space to be provided by the on-chip memory;determining if the information requested is located in the on-chip memory;if the information requested within the virtual address space is contained in the on-chip memory, replying to the request for information with the data from the on-chip memory; andif the information requested within the virtual address space is not contained in the on-chip memory, retrieving the information from the virtual address space onto the on-chip memory and replying to the request for information with the data from the on-chip memory.

2. The method, as set forth in claim 1, wherein the on-chip memory comprises a paged memory region for storing the data from the subset of the virtual address space and a page table for storing lookup information to the virtual address space, the method further comprising: consulting the page table to determine if the paged memory region contains the information requested in the virtual address space; andreplying to the request for information within the virtual address space with a page table miss message if the information requested within the virtual address space is not contained in the paged memory region.

3. The method, as set forth in claim 2, wherein the memory further comprises an unpaged memory region, the method further comprising: determining if the information requested is contained in the unpaged memory region prior to consulting the page table; andif the information requested is contained in the unpaged memory region, replying to the request for information with the information from the unpaged memory region rather than consulting the page table.

4. The method, as set forth in claim 2, further comprising: receiving the page table miss message in one of the one or more processors;determining the location of the information requested within the virtual address space;retrieving the information from the virtual address space;storing the information in the paged memory region; andupdating the page table to indicate the presence of the information in the paged memory region.

5. The method, as set forth in claim 4, wherein the step of determining the location of the information requested within the virtual address space further comprises: identifying one of one or more input streams as the input stream that contains the information requested.

6. The method, as set forth in claim 4, wherein the step of receiving the page table miss message in the one of the one or more processors further comprises: selecting the one of the one or more processors to receive the page table miss message.

7. The method, as set forth in claim 3, wherein at least one of the one or more processors is running a real-time process, further comprising: preloading information for the real-time process into the unpaged region of the on-chip memory.

8. The method, as set forth in claim 2, wherein at least one of the one or more processors is running a non-real-time process, further comprising: aborting the non-real-time process when the non-real-time process has requested information from the on-chip memory in response to a page table miss message; andreturning control to a real-time process running on the same one of the one or more processors.

9. The method, as set forth in claim 6, wherein the one of the one or more processors that receives the page table miss message has access to a semaphore, further comprising: consulting the semaphore prior to updating the page table;configuring the semaphore to protect the page table when updating the page table; andconfiguring the semaphore to no longer protect the page table once the page table has been updated.

10. The method, as set forth in claim 5, wherein the step of retrieving the information from the virtual address space further comprises: reading the information requested from the input stream which contains it.

11. A system for processing a request for information from memory, the system comprising: one or more processors; anda memory coupled to the one or more processors, the memory comprising: a memory controller,a paged area of memory, anda page table, wherein the page table consists of mappings from a virtual address space to a location in the paged area of memory;

12. The system, as set forth in claim 11, wherein the memory further comprises: an unpaged area of memory that stores information that will not be paged and is not referenced by the virtual address space or the page table.

13. The system, as set forth in claim 11, further comprising: one or more data memories, each of the one or more data memories coupled to a corresponding one of the one or more processors, wherein each data memory stores data needed only by the processor to which it is coupled.

14. The system, as set forth in claim 11, further comprising: one or more caches, each of the one or more caches coupled to a corresponding one of the one or more processors and to the memory, wherein each cache stores information received by the processor to which it is coupled from the memory.

15. The system, as set forth in claim 11, further comprising: a bus, coupled to the one or more processors and the memory, wherein each of the one or more processors sends requests for information from memory over the bus and the memory sends information or replies to the one or more processors over the bus.

16. The system, as set forth in claim 11, wherein the one or more processors are each further configured to: select one or more input streams, each of the one or more input streams being a section of the virtual address space;read information from one of the one or more input streams; andstore the information in the paged area of memory, responsive to receiving a page table miss message.

17. The system, as set forth in claim 16, wherein the one or more input streams consists of one or more TCP/IP input streams.

18. The system, as set forth in claim 16, wherein the one or more input streams consists of one or more off-chip memory input streams.

19. The system, as set forth in claim 16, wherein the one or more input streams consists of one or more on-chip compressed memory input streams.

20. The system, as set forth in claim 12, wherein each of the one or more processors is configured to run a real-time code base, wherein instructions for the real-time code base are stored in the unpaged area of memory.

21. The system, as set forth in claim 20, wherein each of the one or more processors is configured run one or more instances of a non-real-time process, wherein if one or more of the one or more instances of the non-real-time process requests information from the paged area of memory, and the information is not available in the paged area of memory, the one or more instances of the non-real-time process are terminated and the one or more instances of the real-time process running on the one or more of the one or more processors continues to execute.

22. The system, as set forth in claim 11, wherein the physical implementation of the memory comprises a static memory device.

23. A memory located on the same integrated circuit as a processor, the memory comprising: a paged area of memory;a page table, wherein the page table consists of mappings from a virtual address space to a location in the paged area of memory; anda memory controller, wherein the memory controller determines if information requested by the processor at a certain address within the virtual address space is located within the paged area of memory and, if so, replies with the information requested or, if not, replies with a page fault message.

24. The memory, as set forth in claim 23, further comprising: an unpaged area of memory;