Patent Application
20210241679
The invention relates to the field of electronics, and more specifically that of matrix display units. It relates to a LED, OLED or any other type of matrix display unit. This matrix display unit makes it possible to dynamically or statically display images, or overlay these two display types; in order to make this double display possible, it comprises a new architecture of each sub-pixel.
Matrix display unit systems are known that implement on each sub-pixel a different architecture according to the type of static or dynamic display desired on the interface.
The publication “Ultra High Resolution AMOLED” by Wacyk et al., published in Proc. SPIE 8042, Display Technologies and Applications for Defense, Security, and Avionics V; and Enhanced and Synthetic Vision 2011, 80420B (doi: 10.1117/12.886520), describes a circuit of the active matrix type with an architecture of the analog memory type. This type of circuit is perfectly suitable for displaying video image sources, because these circuits need periodic addressing, in the order of 25 Hz to 125 Hz, in order not to lose information. On the other hand, in this circuit, the static display generates excessive consumption because its architecture is dedicated to a dynamic display.
Then again, the publication “Ultra-low Power OLED Microdisplay for Extended Battery Life” by Uwe Vogel et al., published in SID 2017 Digest, p. 1125-1128, describes a memory cell matrix circuit, of the SRAM (Static Random Access Memory) type. In this circuit, the image is stored in memory in a memory matrix and the state of the latter only changes when the data to be displayed changes. This type of circuit does not need to be refreshed periodically, it is a static display that is perfectly suitable for displays of the graphic type. Its main advantages are low consumption for static images or low change rate as well as the possibility of addressing the matrix directly by a microcontroller without passing through a video controller.
WO 2014/108741 describes a method for overlaying the two static and dynamic modes for producing the display of a dynamic or static source on the same display unit. The unit comprises a data processing unit for adapting the signals for display on the display matrix. Said post-processing of data makes it possible to produce an overlay, but it is based on a dynamic display unit; consequently, the energy consumption of the unit remains significant. Another unit for the overlaying of images is described in US 2002/0093472.
Given the foregoing, one aim of the present invention is to remedy, at least partially, the drawbacks of the prior art mentioned above by proposing a display unit with very low consumption such as for the static mode but that also makes possible the dynamic display (video mode) of very good quality. This display unit should also make it possible to easily overlay graphic images (in overlay mode) on images in video mode.
One obvious solution for enabling the overlay of graphic images on images in video mode would be to use a screen with a SRAM matrix type circuit and optimize the levels and the speed of addressing the memory in order to be able to display video quality images with a suitable refresh rate. However, this solution encounters a plurality of difficulties. In particular, in order to display a video image of good quality, as a minimum an coding on eight bits, or even on ten bits per sub-pixel is necessary. However, with the CMOS technologies currently available (silicon wafer of 200 mm, with a resolution of 130 nm), this leads to pixel sizes that are much too large. By way of example, a sub-pixel such as described in the article by Vogel et al, cited above, with only four bits of levels measures 12 μm×12 μm, whereas the AMOLED screens such as described in the publication by Wacyk et al., cited above, currently have sub-pixels of a size in the order of 4 μm×4 μm.
According to the invention the problem is solved by using a matrix of elementary electroluminescent emitting zones that has two addressing modes: a first mode (known as “video mode”) using a video type interface, preferably standardized, which makes it possible to display video images of good quality (with typically eight to ten bits of gray levels and a good refresh rate (also known as refresh frequency), typically between 30 Hz and 120 Hz, preferably between 60 Hz and 120 Hz), but that does not need to keep the image in permanent memory, and a second mode (known as “graphic mode”) using a data type interface, preferably standardized (for example of SPI type) that keeps the image in memory, knowing that said graphic mode only requires a small number of gray levels (for example one or two bits per sub-pixel), and that the image stored in memory may either be displayed alone, or overlaid with a video image entered in the display unit by the video interface. It is noted that the expression “gray level” designates here an emission intensity level by an elementary electroluminescent emitting zone, regardless of the color of said emission. Each elementary electroluminescent emitting zone may be a sub-pixel or a pixel. Each elementary electroluminescent emitting zone has two independent memories: a static memory, advantageously of SRAM type, intended for graphic data, and a dynamic, analog memory, intended for data from the video stream; said dynamic memory may be a capacity.
For the video mode, the data is synchronous data, refreshed (updated) periodically, said refresh being typically controlled by a clock.
For the graphic mode, the image may be static and reprogrammed (that is to say updated) as required (that is to say each elementary emitting zone may be refreshed by sending new data only when the content of the static memory thereof will change following said saving of the new data in said static memory), or refreshed periodically. In the first case, this concerns asynchronous data, which does not depend on a clock; in the second case, this may concern synchronous data.
When the graphic image is refreshed periodically, the rate for refreshing the image may be low, in particular lower than 0.1 Hz (or even 0 Hz); it is advantageously in the order of 0.1 Hz to 1 Hz, but may reach a frequency higher than 10 Hz. During the refresh of graphic data, the updated data is saved in all static memories at the same time, even if for some elementary emitting zones this updated data is identical to the previous data that is replaced by the newly saved data. The refresh frequency may be fixed or variable. The frequency for refreshing graphic data is independent of that for video data; it is advantageously lower, but may also be higher.
The object of the invention is an electroluminescent display unit comprising:
Said first and second control blocks are configured to be able to display on the matrix of pixels only the video data stream, or only the graphic and/or alphanumeric data stream, or even to overlay said graphic and/or alphanumeric data stream on said video data stream.
Said first control block is configured to send images towards the matrix of static memories of the pixels, for example via a first system of “select” lines and of “data” columns.
The first control block may comprise a clock or be controlled by a clock.
Said second control block is configured to send:
The second control block must comprise a clock or be controlled by a clock, the video data stream being a synchronous data stream.
According to the invention, each elementary emitting zone comprises a dynamic memory, preferably a capacity, intended for video data. Each elementary emitting zone is connected to at least one, and preferably to a plurality of (for example two or three), static memories, preferably of SRAM type, intended for the static display or with a lower refresh rate and/or with a lower number of intensity levels; said data may be graphic and/or alphanumeric data, static images or video data with temporal and/or visual resolution lower than the video data passing through the dynamic memory.
In a preferred unit of the invention, said first and second control blocks are configured so that said first control block has a number of bits of emission intensity levels lower than same of said second control block. Advantageously, said first control block is configured on three to eight bits of emission intensity levels, and/or said second control block is configured on at least eight bits of emission intensity levels; for example the second control block may be configured on ten, twelve or even fourteen bits of emission levels. Advantageously, said second control block has a refresh rate higher than same of said first control block. Said refresh rate is preferably of at least 25 Hz, more preferably of at least 30 Hz, even more preferably of at least 60 Hz, and optimally of at least 90 Hz, and/or said second control unit includes a memory unit for storing said graphic and/or alphanumeric data for a static display.
The invention will be described hereafter, with reference to the appended drawings, given only by way of non-limiting examples, wherein:
The following numerical references are used in the present description
More specifically, the video block of the unit comprises a counter (for example eight bits) and a comparator at the end of each column that compares the values of the counter with the video data. At the same time, the counter supplies a system of weighted current sources (namely a reference voltage generator). When the values of the counter and of the video data are equal, the reference voltage of the generator is firstly transferred into the buffer memory of the column, and subsequently during the following cycle into the elementary emitting zone, via the column. Between the counter and the reference voltage generator, there may be a conversion table for applying a non-linear correction (gamma factor); in this case it may be useful to have a greater number of bits in the reference voltage generator.
The reference voltage generator generates a voltage that introduces into the elementary emitting zone a current proportional to the value applied to the input.
A reference voltage generation unit 4 generates the reference voltage. Same comprises a counter module with eight bits 41 that sends a signal 45 to a Look-Up Table 42 (known under the acronym “LUT”), optional but recommended, which makes non-linear encoding possible. The value coming from the look-up table 42 is transmitted towards a reference voltage generator 44 coded on ten bits. Said latter comprises another input for providing a current source 43 weighted on ten bits. The output reference voltage 47 of the voltage generator 44 supplies the sampling and maintenance circuit 36 of the second control block 3.
The operation related to
Here, we describe, for a particular embodiment, the display of said graphic and/or alphanumeric data 131 on the matrix of electroluminescent pixels 38. The first control block 2 sends the graphic and/or alphanumeric data signal 131 towards the addressing table 132 of the second control block 3. The addressing table 132 is a horizontal addressing table that controls the addressing of the columns of the matrix of electroluminescent pixels 38; same receives the horizontal addressing signal 133. The second control block 3 moreover comprises a line driving element 137 (vertical addressing table) that receives the vertical addressing signal 134 that controls the addressing of the lines of the electroluminescent display unit 38. The matrix of pixels 38 moreover receives a reference voltage coming from a unit 4 referred to as the reference voltage generation unit. Said last unit 4 comprises a reference voltage generator 44, a current source module 43 and, optionally, a Pulse Width Modulation referred to as PWM signal generator 145.
The operation related to
a and 2b correspond to implementation modes for a dynamic or static display that are distinguished by the management thereof of the data streams thus by the refresh frequency of the information displayed on the matrix of pixels. The architecture of the unit according to the invention brings together said two functions on the same matrix of pixels 38.
The architecture of the matrix of pixels 38 comprises a plurality of pixels aligned horizontally and vertically. In this embodiment, each pixel comprises four sub-pixels as elementary emitting zones; said sub-pixels may mainly be the red, the green and the blue, whereas the fourth sub-pixel may be a complement in white or any other color. Obviously, only three sub-pixels per pixel may be provided for, or even it may be provided for that each pixel is formed from only one elementary emitting zone.
As indicated above, each elementary electroluminescent emitting zone has two independent memories: a static memory, intended for graphic data, and a dynamic memory, intended for data from the video stream.
The dynamic portion 270 of the circuit comprises the arrival of the analog video stream 31 and of a selection voltage 47 from the sequencer 33 on the gate of a transistor SW1205. The cathode of the transistor 205 supplies a capacitor 210 as well as the gate of a transistor TANA1 215. The anode of the transistor TANA1 215 is connected to a voltage VANA. The cathode of the transistor TANA1 215 is connected to the display sub-pixel 290. Said sub-pixel consists of a transistor SW2220 connected to an OLED element 225. The transistor SW2220 is itself also optional and makes it possible for example to modulate the emission of the OLED element 225.
The static portion 280 of the circuit (circled in
The circuit according to
The second usage is the graphic mode that essentially involves the static portion 280. The memory function of the SRAM cells 245,250 makes it possible to maintain open or closed the transistors SW3245 and SW4250. The controlled openings of SW3245 and SW4250 enable the passage of the reference voltage Vref 147 up to the OLED element 225. The assembly of TANA2 235 and TANA3 240 in parallel has the function of analog to digital converter on two bits. The converter enables four possible modes as follows:
Mode 00: When the two transistors SW3245 and SW4250 are not conducting, the current transiting in the circuit is null, as mentioned previously in the pure dynamic mode.
Mode 01: the transistor SW4250 is conducting, the relative current is sent to the unit for displaying the sub-pixel 290.
Mode 10: the transistor SW3245 is conducting, the relative current is sent to the unit for displaying the sub-pixel 290.
Mode 11: the transistors SW3245 and SW4250 are conducting, the relative current is sent to the unit for displaying the sub-pixel 290.
The third usage is a mixed mode referred to as overlay: both a video signal by the dynamic channel 270 and a graphic signal by the static portion 280 are applied. The current in the OLED therefore corresponds to the overlay of both signals; the display of the sub-pixel 290 is controlled by the converter formed by TANA2 235 in series with SW3245 and TANA3 240 in series with SW4250 as well as TANA1 215.
The diagram shown in
The architecture shown above is designed to supply the OLED 225 with steady current, however, same may also be applied to a voltage supply by means of minor modifications.
The static portion 380 (circled in
The output of a SRAM cell 355,360 makes it possible to make the respective transistors 345 and 350 conducting, a predetermined voltage Vref is applied to the gate of the transistor TANA 315 that is the current source for the OLED; there is no need for specific current sources, but it is necessary to provide one SRAM cell per level (and not per bit as in the first embodiment). This is shown in the following table for the case of four current sources: the reference voltages Vref1 and Vref2, when the transistors SW3345 and SW4350 are conducting, are on the transistor TANA:
The circuit according to
According to the number of memory cells present in the circuit, the display portion 390 reacts to the various voltages applied on TANA 315, as indicated for example in the table above.
In this use mode, the voltage state of the gate of the transistor TANA is not necessarily known and it may be in a case of high impedance, in which case the transistor remains blocked. In order to overcome this problem, the applicant proposes to use a voltage Vselect in order to initialize the transistor TANA. For this in the case of a graphic mode only, the voltage Vselect is not controlled by the sequencer 33 but comes from the reference voltage generation unit 4.
The signal of the voltage Vselect makes it possible to reinitialize the transistor TANA before each write in the memory cells.
The third use mode is a mixed mode referred to as overlay, which involves both the static portion 280 and the dynamic portion 270 of the circuit. The display of the sub-pixel 290 is controlled by the converter formed by TANA 315. In this case, the display portion 390 allows both the video signal 31 and the stream coming from the various memory cells 355,360 to pass through.
As indicated above, here circuits are described wherein the display of the sub-pixels 290 is controlled by the current, but the circuits may be controlled in voltage by means of minor modifications.
In this embodiment and by way of example comprising four bits of gray levels, the four control signals 146, S1, S2, S3, S4 control the gates of the four transistors 440, 445, 450, 455 that make it possible to transmit data coming from the cell memories 441, 446, 451, 456 respectively arranged on the anode thereof towards the gate of SW1435. The fifth transistor 460 is connected by the cathode thereof to the anode of SW1435 and comprises an analog supply VANA on the anode thereof and a signal Vreset on the gate thereof. The memory cell may be of type with six transistors or more. The sub-pixel 425 of the display portion 480 operates with only one level of luminance, therefore it is by controlling the emission time of said latter that the gray levels are produced.
The circuit according to
According to a second use mode only the static portion 480 of the circuit is used. The writing in the memory cells 441, 446, 451, 456 is carried out completely randomly. In order to prevent any effect of visible flicker at the display portion 490, the refresh frequency of the signal must be higher than 85 Hz or lower than 12 ms. It is preferable to use an even higher frequency, around 120 Hz, in order to limit the interferences concerning the writing time and emission of the memory cells. In this use mode, the voltage state of the gate of the transistor TANA is not necessarily known and it may be a case of high impedance, in which case the transistor remains blocked. In order to overcome this problem, the applicant proposes to use a voltage Vselect in order to initialize the transistor TANA. For this in the case of a graphic mode only, the voltage Vselect is not controlled by the sequencer 33 but comes from the reference voltage 147 generator 44.
The signal of the voltage Vselect makes it possible to reinitialize the transistor TANA before each write in the memory cells.
The third use mode is a mixed mode referred to as overlay, which involves both the static portion 480 and the dynamic portion 470 of the circuit. The dynamic portion 270 sends the video signal 31 on the sampling capacity CS 410. The voltage level on the capacity may be forced by the data coming from the memory cells 441, 446, 451, 456 that will force the display of the static portion 480 on the video stream 31 of the dynamic portion 470. The voltage Vselect takes the features of the signal of the sequencer 33 through the vertical shift register 37.
The diagram shown proposes an advantageous embodiment, however, it may consist of additional memory cells in order to increase the number of gray levels.
All of the embodiments use OLED current driving. For voltage driving, all of the transistors shown of the PMOS type must be replaced by NMOS transistors.
The voltage VANA is typically in the order of 1.0 V to 3.3 V (for example 1.8 Volt), the voltage Vcath is typically in the order of −2 V to −9 V (for example −8 Volt).
When the screen is configured to display graphic data at the same time as video data, the graphic data may have either the priority (in the embodiment shown in
More specifically, in the embodiment described in relation with
| Number | Date | Country | Kind |
|---|---|---|---|
| 1854079 | May 2018 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/FR2019/051100 | 5/15/2019 | WO | 00 |
