The present invention relates to a row-based Viterbi bit detection method for detecting the bit values of bits of a channel data stream stored on a record carrier. Further, the present invention relates to a corresponding row-based Viterbi bit detector, a method of reproduction of a user data stream, a corresponding reproduction device and a computer program for implementing said methods. In particular, the present invention relates to a row-based Viterbi bit detection method for information written in a two-dimensional way on a record carrier, such as an optical disc or a memory card. The present invention could also be regarded as relating to Partial Response Maximum-Likelihood (PRML) bit detection, i.e. the invention also relates to a PRLM bit detection method and device.
European patent application 01203878.2 discloses a method and system for multi-dimensionally coding and/or decoding an information to/from a lattice structure representing channel bit positions of said coded information in at least two dimensions. Encoding and/or decoding is performed by using a quasi close-packed lattice structure. For the case of three-dimensional encoding and/or decoding, preferably a (quasi) hexagonally close packed (hcp) lattice structure is to be used. Another possibility in three dimensions is the use of a (quasi) face-centered cubic (fcc) lattice structure. For the case of two-dimensional encoding and/or decoding, preferably a quasi-hexagonal lattice structure is to be used. Another possibility in two dimensions could be the use of a quasi square lattice structure. For the sake of a more simple and clear description of the object of the present invention, special attention is given to the two-dimensional case. The higher-dimensional cases can be derived as more or less straightforward extensions of the two-dimensional case. The special situation of the one-dimensional case which comprises only a single row of bits, boils down to the very classical case of PRML bit detection as is well known in the state of the art for one-dimensional modulation and coding, as for instance described in Chapter 7 “Viterbi Detection” by Jan Bergmans, “Digital Baseband Transmission and Recording”, Kluwer Academic Publishers, 1996.
In one-dimensional recording on optical discs the channel bits of the channel data stream are recorded along a spiral track, the spiral being one bit wide. For two-dimensional recording the channel bits of a channel data stream can also be recorded along a spiral, albeit a broad spiral, that consists of a number of bit rows which are aligned with respect to each other in the radial direction, that is, in the direction orthogonal to the spiral direction. The additional alignment of bit rows can also be obtained in another direction not strictly orthogonal to the spiral direction, but in a direction making a certain non-zero angle with the spiral direction.
A PRML bit detection apparatus for deriving a bit sequence from an input information signal is disclosed in WO 00/18016. The apparatus comprises input means for receiving the input information signal, sampling means for sampling the input information signal at sampling instants so as to obtain samples of the input information signal at said sampling instants, conversion means for converting an array of said samples into an array of bits of a first or a second binary value, detection means for repeatedly detecting a state for subsequent sequences of n subsequent bits of said array of bits, said subsequent sequences being obtained by shifting a time window of n subsequent bits each time over one bit in time, means for establishing the best path through the states, and deriving means for deriving a sequence of bits in accordance with the best path through said states. In that apparatus, n is larger than 3, and sequences of n subsequent bits having n-1 directly successive bits of the same binary value are allocated to the same state. In a specific embodiment n is an odd number larger than 4. In that specific embodiment, sequences of n subsequent bits having n-2 directly successive bits of the same binary value as the central n-2 bits in such n-bit sequence, are allocated to the same state. This results in a PRML detection apparatus with reduced complexity.
A full-fledged PRML bit detector for 2D bit-arrays would require a trellis which is designed for the complete width of the broad spiral, with the drawback of an enormous state-complexity that leads to a completely impractical algorithm since it cannot by far be implemented even in the fastest hardware of the coming decennia.
A 2D PRML bit detector is disclosed in “Study of Recording Methods for Advanced Optical Disks”, S. Taira, T. Hoshizawa, T. Kato, Y. Katayama, T. Nishiya, T. Maeda, Technical Report of IEICE, 2002-03, pp. 57-64. Therein, an optical storage system with 2D modulation on a square lattice, with d=1 RLL constraints both in horizontal and vertical directions is described. For this system, a receiver consisting of a 2D-equalizer and a 2D-Viterbi detector or a 2D-PRML detector is disclosed in “Two-Dimensional Partial-Response Equalization and Detection Method with Multi-Track”, T. Kato, S. Taira, Y. Katayama, T. Nishiya, T. Maeda, Technical Report of IEICE, 2002-03, pp. 65-70. The 2D PRML detector is based on three successive bit rows, but the typical add-compare-select operation (ACS) of the Viterbi-algorithm uses the HF-samples of the central bit row only; the other two bit rows are used in order to determine in a joint way the reference level from which the received HF-signal should be subtracted in order to derive the branch metrics for the branches (or transitions) in the trellis diagram of the Viterbi detector. In this way, at its output, the Viterbi-detector yields bit-decisions for the central bit row only. In this sense, for successive rows, the PRML detectors operate already independently, and the state-complexity for the complete set of bit rows has been reduced down to the complexity that is to be associated with 3 rows only. Within a strip of 3 rows, the known bit detector performs a kind of 2D-PRML, but with a 1D-output (for the single row being the mid-row of the 3-row strip). It should be noted that the channel strips are processed independently, but that the state-complexity of the Viterbi-detector is still quite high.
Assuming the practical case of a 3-taps response in the tangential direction, as disclosed in the above mentioned documents. For the square lattice, but also when applying this algorithm for a hexagonal lattice, assuming no modulation coding for both lattices, states characterized by 6 bits each would be obtained, yielding a number of 26=64 states; each state would then have 23=8 possible predecessors. On the square lattice, assuming the runlength modulation coding of the above references with 2D d=1 constraint, the number of states is only a bit smaller than 64, since some of the states are forbidden just because of the use of the runlength constraints along vertical and horizontal directions.
It is an object of the present invention to provide a Viterbi bit detection method that provides a high recording density, in particular such that the traditional “eye” of the eye pattern may even be closed. The “eye height” in the traditional eye-pattern corresponds with the systematic minimum difference in signal levels for the case that a bit has a value “0” and the case that a bit has a value “1”. An “open eye” means that (on average, or without any noise) the signal levels for bit “0” and bit “1” can be clearly discriminated: in such case a threshold detection procedure with an appropriately set slicer level could be used.
The case of a “closed eye” corresponds to the situation where some of the signal levels cannot unambiguously be allocated to bit “0” or bit “1”, even in the absence of noise. There is in the latter case a range of signal levels, called the erasure zone, where the signal levels for bit “0” and bit “1” overlap.
It is a further object of the present invention to achieve a low bit error rate, which is particularly less than 10−2 to 10−1 as would be achieved for the case of a “closed eye” by application of a straightforward threshold detection prior to ECC decoding. Preferably, the symbol or byte error rate (BER) for “random” errors (as opposite to so-called “burst errors”) in the case of a byte-oriented ECC, like the picket-ECC as used in BD (formerly known as DVR), shall not be larger than 2×10−3; for an uncoded channel bit stream this corresponds to an upper bound on the allowable channel-bit error rate (bER) of 2,5×10−4.
Still further, a further reduction of the state-complexity of the independent Viterbi-detectors shall be achieved.
These objects are achieved according to the present invention by a Viterbi bit detection method as claimed in claim 1, according to which the channel data stream is stored on a record carrier along an N-dimensional channel tube, N being at least two, of at least two bit rows one-dimensionally evolving along a first direction and being aligned with each other along at least a second of N-1 other directions, said first direction together with said N-1 other directions constituting an N-dimensional lattice of bit positions, comprising application of a row-based one-dimensional Viterbi bit detection method independent for each of the bit rows of said channel tube, wherein:
calculation of the branch metrics for all possible state transitions in a Viterbi trellis of a one-dimensional row-based Viterbi detector, said transitions representing a number of subsequent bits in said bit row, said bits being the central-row bits of a cluster of the N-dimensional lattice of bits, is based on the difference of the received HF signal value with respect to a reference level, wherein said reference level depends on all bits of said cluster, said cluster comprising in addition to the central-row bits a number of primary neighbouring bits in each of a number of neighbouring bit rows on each side along said N-1 other directions of said central bit row along which the one-dimensional Viterbi bit detection method is applied, and wherein preliminary bit decisions for the primary neighbouring bits in the neighbouring bit rows are used for determining the reference level to be used for calculating said branch metrics, and
selection of the bit value for the central bit of said cluster of the N-dimensional lattice of bits, corresponding with said received HF signal value, is based on the calculated branch metrics.
These objects are further achieved by a row-based Viterbi bit detector as claimed in claim 22 comprising Viterbi bit detection units including means for calculation of the branch metrics and means for selection of a bit value. The invention relates further to a method of reproduction of a user data stream, which is error correction code encoded and modulation code encoded into a channel data stream and stored on a record carrier, comprising a Viterbi bit detection method as described above for detecting the bit values of bits of the channel data stream and a modulation code decoding method and an error correction code decoding method. Still further, the present invention relates to a reproduction device as claimed in claim 25 and a computer program as claimed in claim 26. Preferred embodiments of the invention are defined in the dependent claims.
The present invention is based on the idea to achieve reliable bit detection by using a number of independent 1D Viterbi sequence-detectors, one for each bit row in the channel tube: the interference between successive neighbouring bit rows is taken into account via the computation of the branch metrics for the considered bit row, in which preliminary bit decisions on the primary neighbouring bits are used that may require local bit decisions on the secondary neighbouring bits in the neighbouring bit rows, said secondary neighbouring bits being the neighbouring bits of said primary neighbouring bits not being part of the central bit row being considered for the 1D Viterbi detection.
Regarding the general layout and function of a PRML bit detection apparatus reference is made to the above mentioned WO 00/18016 where also several terms are explained. This description and explanation is herein incorporated by reference.
Preferred embodiments for determining the preliminary bit decisions on the primary neighbouring bits are defined in claims 2 to 7. Thus, a slicer level can be used in a threshold detection. Further, specific bit values of the bits in the central row can be used in accordance with each of the specific branches to be considered in the Viterbi trellis. Said threshold detection is based on the detected HF signal value for a particular bit without consideration of the HF-signal samples at the neighbouring bit-locations.
According to a preferred embodiment a predetermined criterion is evaluated for determining the preliminary bit decisions, which criterion is determined by the sum over all the primary neighbouring bits, said sum comprising terms related to a subcriterion that is based on the differences of the HF signal value and a reference HF signal value corresponding to the bit cluster of each single primary neighbouring bit, which evaluation is done for all possible bit units obtained for all possible values of said primary neighbouring bits, and wherein the bit unit with the lowest value of said predetermined evaluation criterion is selected. Preferred subcriteria which relate to the squared value or the absolute value of the difference of the HF signal value and a reference HF signal value corresponding to the bit cluster of each single primary neighbouring bit to are defined in claims 5 and 6.
In addition to the primary neighbouring bits, preliminary bit decisions on secondary neighbouring bits can be used for determining the preliminary bit decisions on the primary neighbouring bits as defined in claim 8. Those preliminary bit decisions on said secondary neighbouring bits can be obtained, for instance, by threshold detection.
There are different ways to calculate the branch metrics. Two preferred ways are defined in claims 9 and 10. The Viterbi algorithm in a PRML bit detector searches for the “best” path, that is the path with the minimum path cost. The path cost is sometimes called “path metric”. A path can be seen as a succession of transitions. A transition from one state to another state is called a branch. Each transition (or branch) has associated with it a certain branch metric (or branch cost). The path metric for a given path is the sum of the costs of the individual branches of the path, that is, the path metric is a sum of a selection of branch metrics.
Generally, the present invention is applicable to a multi-dimensional code, where the channel words of the channel data stream may evolve in more than one direction as is the case for a card-based system, i.e. where the channel data stream is stored on a record carrier along a multi-dimensional channel tube with dimension at least two. Therein, the first direction along which the bit rows evolve is preferably common to all bit rows of the channel tube. The first direction constitutes together with the N-1 other directions, along which the bit rows are aligned with each other, an N-dimensional space and an N-dimensional lattice of bit positions. The channel tube comprises at least two bit rows of channel bits evolving along said first direction, and the collection of all said channel tubes fill the whole N-dimensional space.
However, it is preferred to apply the invention to a channel data stream which comprises a one-dimensionally evolving bit sequence or which comprises a channel strip of at least two bit rows one-dimensionally evolving along a first direction and aligned with each other along a second direction, preferably oblique or even orthogonal to said first direction, said two directions constituting a two-dimensional lattice of bit positions. Preferred embodiments of such a lattice are a 2D lattice of a square or a hexagonal type as defined in claims 12 and 13.
In a hexagonal lattice, hexagonal clusters may be formed of a set of 7 bits in total, comprising three bits in a central bit row and two primary neighbouring bits in each of the two neighbouring bit rows. Further secondary neighbouring bits can be located in the neighbouring bit rows of the central bit row considered. Preferred embodiments of the invention using hexagonal clusters are defined in claims 14 to 18.
An advantageous embodiment for calculation of the branch metrics using an expectation value is defined in claim 19. The method can also be applied in the three-dimensional case where the bits are location on bit positions of a three-dimensional lattice as claimed in claim 20.
The bit detection method according to the invention can also include an iterative use of the row-based one-dimensional Viterbi bit detection method: the output of the 1D-Viterbi detectors for a given 1D part of the set of bit rows can be used for the required primary bit decisions in the neighbouring rows during a second run of the method for the same 1D part (same bits along the 1D row) of the set of rows. The purpose is to use the output of the first set of 1D-Viterbi detectors for all bit rows as a better bit decision for the primary bit decisions required in a possible second set of Viterbi detectors for all bit rows.
The invention shall now be explained with reference to the drawings in which
In the above mentioned European patent application EP 01203878.2 the 2D constrained coding on hexagonal lattices in terms of nearest-neighbour clusters of channel bits is described. Therein, it has been focussed mainly on the constraints with their advantages in terms of more robust transmission over the channel, but not on the actual construction of such 2D codes. The latter topic is addressed in the European patent application 02076665.5 (PHNL 020368), i.e. the implementation and construction of such a 2D code is described therein. By way of example, a certain 2D hexagonal code shall be illustrated in the following. However, it should be noted that the general idea of the invention and all measures can be applied generally to any 2D code, in particular any 2D hexagonal or square lattice code. Finally, the general idea can also be applied to multi-dimensional codes, possibly with isotropic constraints, characterized by a one-dimensional evolution of the code.
As mentioned, in the following a 2D hexagonal code shall be considered. The bits on the 2D hexagonal lattice can be identified in terms of bit clusters. A hexagonal cluster consists of a bit at a central lattice site, surrounded by six nearest neighbours at the neighbouring lattice sites. The code evolves along a one-dimensional direction. A 2D strip consists of a number of ID rows, stacked upon each other in a second direction orthogonal to the first direction. The principle of strip-based 2D coding is shown in
The signal-levels for 2D recording on hexagonal lattices are identified by a plot of amplitude values for the complete set of all hexagonal clusters possible. Use is further made of the isotropic assumption, that is, the channel impulse response is assumed to be circularly symmetric. This implies that, in order to characterize a 7-bit cluster, it only matters to identify the central bit, and the number of “1”-bits (or “0”-bits) among the nearest-neighbour bits (0, 1, . . . , 6 out of the 6 neighbours can be a “1”-bit). A “0”-bit is a land-bit in our notation. A typical “Signal-Pattern” is shown in
According to the present invention the broad spiral (or meta-spiral) consists of a number of bit rows. It is proposed to apply a row-based 1D-PRML, in which the Viterbi-trellis relates only to the bits in the individual bit row itself. For a 3-tap target response in the direction along the bit row, states are obtained that are each defined by two bits.
Next, the computation of branch metrics shall be explained.
βij=(HF0−R.L.[x0=b1i;x1=b1j;x2;x3;x4=b0i;x5;x6])2
where HF0 denotes the sample value of the (possibly equalized) received signal at the (central) bit x0. R.L. denotes the reference amplitude level, which depends on all the bit-values of the 7-bit cluster. For a given transition (“i” to “j”), the values of the bits x0, x1 and x4 in the central bit row are already fixed. The other bits that still need to be determined, occur in two pairs of bits, denoted by x2, x3 and x5, x6. These pairs correspond with nearest neighbour bits of the central bit x0, where each of these pairs is located either in the upper neighbouring bit row, or in the lower neighbouring bit row. The bit values in these two bit-pairs are required in order to be able to uniquely identify the reference level R.L. to be used in the branch metric for the transitions in the 1D-PRML detector for the considered bit row. These bits will be further referred to as the primary neighbouring bits. Therefore, these bit decisions on the primary neighbouring bits can be seen as preliminary bit decisions, needed to assist the evaluation of the branch metrics required for the bit decisions of the bit in the considered (central) bit row. One aspect of the present invention relates to the decisions that are to be made on those two bit-pairs of primary neighbouring bits. The quality of these (temporarily needed) preliminary bit decisions that are (only) required for the computation of branch metrics, have an impact on the quality of the ultimate bit decisions of the bits in the central row on which the 1D-PRML is applied. The preliminary bit decisions on the primary neighbouring bits are thus never used as real output bits for the neighbouring bit rows.
A rather straightforward approach is to use threshold detection for the primary neighbouring bits denoted by x2 and x3 and x5 and x6. However, threshold detection is highly unreliable due to the large overlap in signal levels in the signal pattern shown in
More reliable bit decisions at the primary neighbouring bits can be obtained through the use of the hard-decision bit detectors on nearest-neighbour bits in neighbouring bit rows.
The trellis for 1D-PRML bit detection with 3-taps impulse-response in the tangential direction is illustrated in
For the above case (with 2-bits states “00”, “01”, “10” and “11”), a branch metric for a transition between states s0 and s1, from moment (or time) k-1 to moment k, is the squared value for the L2-norm (or absolute value for the L1-norm) of the difference between the measured HF-sample at time k (denoted by HFk) and the reference level R.L. that is associated with the transition from state s0 to state s1. The reference level is a kind of ideal (noise-free) signal level for the transition that is considered. The reference level here also depends on the bit values of the neighbouring bit rows, because of the strong 2D inter-symbol-interference (ISI). In standard 1D-storage, the neighbouring bit rows are always far away so that this problem is not present there. The applied Viterbi algorithm shall now be explained with reference to
(a) for each state the path metric for the best path, i.e. the path with minimum cost, that arrives in that state, is known;
(b) for each state the predecessor state at the previous time is known: the predecessor state is the state that lies on the best path at the previous time moment.
Then, the best path at moment k that arrives in “01” can be found by looking at the two possible predecessor states of state “01”: one path starts in state “00” with a path metric p00,k-1 and needs a branch “00”->“01” to arrive in state “01”, with a branch metric given by b00->01,k. The second path starts in state “10” with a path metric p10,k-1 and needs a branch “10”->“01” to arrive in state “01”, with a branch metric given by b10->01,kk. The best path is the path that realizes the minimum cost:
minimum of p00,k-1+b00->01,k and p10,k-1+b10->01,k.
If the latter is the best path, then the predecessor state of state “01” is “10”, in the other case the predecessor state of state “01” is “00”. This procedure is known as Add-Compare-Select (ACS): the branch metric is added to the previous path metric to obtain a candidate for the current path metric; the two candidate path metrics are compared, and the path with the lowest metric is selected.
This procedure is repeated for all states (at each time moment). As a result, a collection of path metric and predecessor state for each state and each time moment is obtained. The actual bit detection is then performed by a so-called back-tracking operation: one starts from a best state at moment k, and goes back to its predecessor state at time k-1, and to the predecessor state of that state at moment k-2 and so on. The back-tracking is done for a certain depth K (known as back-tracking depth); the bit value at moment k-K is (for instance) the bit-value of the first bit in the resulting state obtained at the end of the back-tracking operation. States “00” and “01” lead to bit “0”; states “10” and “11” lead to bit “1”.
There are four states, denoted by “00”, “01”, “10” and “11”. For each of these states, the best predecessor of that state and the path costs up to the given state for the path with the lowest cost going to that state are evaluated, as illustrated in
According to the embodiment shown in
The so-called “branch-bits” apply for the three bits of a given transition in the trellis for the bit row under consideration. A similar diagram (not shown) applies for the block HD-2 Low, yielding bit decisions in the lower row for the bits denoted by b2 and b3.
The bits determined by the HD-2 Upp block are further used, together with the similarly derived—by means of block HD-2 Low—lower bits b2 and b3 to derive reference levels from a reference level memory as shown in
For each hexagonal cluster with one central bit and 6 neighbouring bits, a reference signal level is available from a memory, i.e. the HF Reference-Level Memory. The reference level to be taken from the memory is determined by the two bits of the bit pair, and by 5 out of the 8 neighbouring bits of the bit pair. The 8 neighbouring bits of the bit pair comprise 3 bits of the central bit row (determined by the actual branch considered), and 5 secondary neighbouring bits.
The received HF-signal for each bit of the two bits of the bit pair are subtracted from the corresponding reference level; the absolute values (shown here; it may also be any other “norm” like the quadratic norm using the squared values instead) of these respective signal differences are added together for each of the four possible two-bit configurations for the two bits of the bit pair. The bits that result from the HD-2 bit detector are those that lead to the smallest value of the above set of 4 parameters or samples of the selection criterion, one sample for each possible bit pair. This is denoted in
According to an alternative embodiment soft-decision information about the primary neighbouring bits in the bit pairs (denoted by x2 and x3, and x5 and x6) is used. The branch metric for a given transition from state “i” to state “j” is then computed as an expectation value, which is the average taken over all possible bit-configurations in the two bit pairs of primary neighbouring bits. Formally, this can be written as (with the index k to the HFk signal referring to the sample at the k-th bit in the hexagonal cluster):
It should be noted that the bit values denoted by (b0i, b1i) refer to the two bits in state “i” of the 4-state Viterbi-trellis (shown in
Just as in the HD-2 bit detector, reference can be made to
The performance for various detectors for the density of 1 .4× the density of BD has been computed. A lattice parameter a=165 nm with a pit-hole diameter equal to 120 nm (in order to avoid signal folding) has been assumed. The channel is subjected to AWGN disturbance (additive white Gaussian noise). The detectors are:
threshold detection (TD);
HD-3 Hard-Decision Iterative Bit detector (HD-3);
TD-assisted 1D-PRML;
HD-2 assisted 1D-PRML;
HD-3-assisted 1D-PRML;
SD-1 Soft-Decision Iterative Bit detector (SD-1);
Soft-Decision-assisted 1D-PRML.
The results are shown in
The present invention provides a solution to achieve reliable bit detection by using a number of independent 1D-Viterbi bit detectors (also known as sequence detectors) is used, one for each bit row in the channel tube: the interference between successive neighbouring bit rows is taken into account via the computation of the branch metrics (for the considered bit row), in which local bit decisions on the primary neighbouring bits in the neighbouring rows are used. As local bit detectors going beyond the performance of a threshold detector, the use of a HD-2 or HD-3-like hard-decision bit detector is proposed. Other local bit detectors might also be used, insofar that they take account of the specific bit values for the respective branches in the Viterbi trellis of the central row that is being processed with one-dimensional row-based Viterbi bit detector to condition the preliminary bit detection for the primary neighbouring bits in the neighbouring rows of the considered bit row.
Further, it is proposed to use the output of a soft-decision bit detector at the bits in the neighbouring rows of the central row, in order to compute the branch metrics. Practically, it is proposed to use soft-decision information that can be directly generated from the signal pattern (with 2×7 signal levels, grouped as 7 pairs of levels). Of course, other soft-decision bit detectors can be used for the same purpose, like e.g. iterative soft-decision-detectors. Preferably, the two- and three-dimensional cases are advantageous where the bits are arranged on a two- or three-dimensional lattice.
Number | Date | Country | Kind |
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02078985.5 | Sep 2002 | EP | regional |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB03/03733 | 8/13/2003 | WO | 3/23/2005 |