The present invention relates generally to packet based communication systems, and more particularly to scaling of inputs to a decoder in a packet based wireless communication system.
Communication systems generally transmit information from a transmitter to a receiver over a medium. The transmitted information is subject to corruption or degradation due to a variety of causes. The transmitter circuitry may introduce noise, the transmission medium may alter the information and reflections or energy from interfering sources may also be present at the receiver, and the receiver may introduce noise or otherwise fail to properly recapture the data.
Many systems therefore attempt to adjust operation so as to account for these and other possible sources of error. Redundant information is often added to data transmissions, for example using error correction coding, allowing for correction of some errors by a decoder of the receiver. Receiver circuitry for decoding encoded data, however, may be power and space intensive, increasing receiver cost, increasing receiver power usage, and also possibly increasing receiver failure rates.
Soft bits are often used in decoding schemes to improve decoder correction capabilities. Reducing the number of soft bits used may decrease decoder complexity and power requirements, with the soft bits possibly scaled before reducing the number of bits used. Inappropriate scaling of soft bits, however, may increase degradation of received data. Further, some communication systems additionally transmit data over different frequencies possibly using different spreading methods. The use of different frequencies and different spreading methods may further complicate decoder input scaling considerations.
The present invention provides for scaling of information prior to reducing bits used by a decoder, for example a soft decision decoder. In one aspect the invention provides a method of scaling decoder inputs performed by a receiver in an ultrawideband (UWB) communication system, comprising determining a plurality of values using received information; determining a data rate for further received information; selecting a one of the plurality of values based on the data rate; scaling a representation of the further received information using the one of the plurality of values; reducing in number bits used to represent the scaled representation of the further received information; and decoding received information using the reduced number of bits.
In another aspect the invention provides a method of scaling soft bit decision decoder inputs, comprising: receiving complex symbols; determining a mean value for the complex symbols; time combining the complex symbols; determining a mean value for the time combined complex symbols; frequency combining the time combined complex symbols; determining a mean value for the frequency and time combined complex symbols; receiving an indication of a data rate for further received information; scaling a representation of the further received information using one of the mean value for the complex symbols, the mean value for the time combined complex symbols, or the mean value of the frequency and time combined complex symbols based on the indication of the data rate for the further received information; reducing the number of bits used for the scaled representation of the further received information; and providing the reduced number of bits to a decoder.
In yet another aspect the invention provides a receiver for an wireless communication system, comprising: an RF portion including amplification and downconversion circuitry; an analog-to-digital converter for converting signals provided by the RF portion to digital signals; a Fast Fourier Transform block configured to transform samples of the digital signals to symbols in the frequency domain; a demapper configured to generate multiple bit symbols based on the symbols in the frequency domain; mean value computation circuitry configured to generate mean values of the symbols in a plurality of ways; and a scaler configured to scale the multiple bit symbols using a rate selectable one of the mean values.
These and other aspects are more fully comprehended upon consideration of this disclosure.
The digital baseband portion digitally processes received signals. In a digital processing block 815 operations on the received digital signal are performed. Operations generally include packet detection, frame synchronization, automatic gain control, and other operations. The processed signal is transformed to the frequency domain by an FFT block 817. The frequency domain signal is demapped by demapper 819. The demapper output is scaled by a scaler 821. The scaler includes circuitry for scaling the output of the demapper for use in soft decoding. In some embodiments the scaler includes circuitry for determining mean values of received information, with the demapper output scaled using the mean values. In most embodiments, however, the demapper block includes circuitry to determine the mean values, or alternatively the mean value computation circuitry may be located elsewhere in the digital baseband portion of the receiver.
The mean values may be mean absolute values of received symbols, for example of the complex symbols provided by the FFT block. In some embodiments mean values may be determined using different methods, for example by summing over different numbers of subcarriers and/or different number of symbols, with the mean value selected for use based on a predefined criteria, for example payload data rate. In addition, in some embodiments mean value determinations are made using channel compensated symbols of a preamble, with scaling performed for payload data only.
A soft decoder 823 decodes the scaled demapper output. The soft decoder generally includes circuitry for performing decoding, such as Viterbi decoding. The decoded information is then provided to further components, for example, a media access controller (MAC). In some embodiments the soft decoder reduces the number of bits used to represent the scaled demapper output prior to decoding. In general, however, received information is also interleaved and possibly punctured, and deinterleaving may be performed by deinterleaving circuitry and depuncturing may be performed by a depuncture block, which may be part of the soft decoder block, or separate blocks prior to the soft decoder block. In such cases bit reduction is generally performed prior to deinterleaving and depuncturing.
In one embodiment one of the mean values, for example VMEAN1, is determined using information from a first number of subcarriers and a first number of symbols. A second mean value, for example VMEAN2, is determined using information from the same number of subcarriers as used for VMEAN1, but over fewer symbols, with for example the symbols being combined over time. A third mean value, for example VMEAN3, may be determined over a fewer number of subcarriers and a fewer number of symbols, with for example the subcarriers having been subject to combination in frequency.
The selected mean value is provided to a square root block 213, which determines a square root value of the selected mean value. The square root of the selected mean value is then inverted by a 1/X divider 215. In some embodiments the inverse of the square root is used to scale the demapped soft values in a multiplier block 217, with the scaled soft values then subject to further processing. As illustrated in
As shown in
In some embodiments mean value scaling of decoder inputs is only performed for a payload portion of a packet, and in some embodiments the mean values are determined only once channel compensation information is available to be performed on received symbols.
As shown in
The demapper block receives complex soft symbols generated by a fast Fourier transform (FFT) block. A bit demapper 411 performs bit demapping of the complex soft symbols. The bit demapper demodulates or demaps a symbol, in a QPSK format for example, to bit values. In some embodiments symbols are modulated or mapped by a transmitter using one, some, or all of a QPSK scheme, a DCM scheme or a 16-QAM scheme, with the demapper including appropriate circuitry for demodulating or demapping of the symbols.
In some embodiments, usually depending on desired data rate, symbols on different subcarriers may be coherently combined at the receiver, and repetitive symbols in time may be similarly combined, for example to compensate for fading effects at different frequencies. Table 1 shows the use of time repetition and frequency repetition for different data rates in an example UWB system.
Table 1 shows that time repetition is used for data rates from 53.3 megabits per second (Mbps) to 200 Mbps. Table 1 shows that frequency repetition is additionally used for data rates of 53.3 Mbps and 80 Mbps.
Time repetition is provided by copying the OFDM symbol to a second time period, for example immediately following the first time period, or some other time period dependent on a frequency hopping pattern, for example such that the repeated UFDM symbol is transmitted on a different frequency subband. In many embodiments repetitive transmission of symbols provides further frequency diversity as many systems use time frequency hopping.
Table 2 shows an example of time frequency hopping used in some embodiments of the invention.
Table 2 shows 10 frequency hopping patterns over time, with each pattern indicated by a TFC number. For example, for TFC 1 transmission occurs over a first subband of frequencies at time n=0. At time n=1 transmissions occur over a second subband of frequencies. At time n=2 transmissions occur over a third subband of frequencies, with the pattern thereafter repeating. Accordingly, for many TFCs, symbols repeated in time are transmitted at different frequencies, providing frequency diversity.
Thus, it may be seen that in some embodiments transmitted symbols are either subjected to time repetition and frequency repetition, only time repetition, or neither time repetition or frequency repetition. Accordingly, returning to
The mean values may differ dependent on whether time and frequency combination have been performed, only time combination has been performed, or neither time or frequency combinations have been performed. Accordingly, the block diagram of
A mean value calculation block 421a receives the absolute values determined by the absolute value block 419a, and determines a mean value of the complex soft symbols. In one embodiment an OFDM symbol is transmitted over 100 data subcarriers, and the mean value is calculated over the 100 data subcarriers. Similarly, in one embodiment the header portion of a packet includes 12 symbols after channel compensation is available, accordingly 10 symbols are used for the determination of the mean value so as to allow for a timing buffer before beginning processing of a payload portion of a packet.
A mean value calculation block 421b similarly receives absolute values from the absolute value block 419b. As an absolute value block 419b is determining absolute values for symbols which have been combined in time, the mean value calculation block 421b determines mean values over 100 data subcarriers, but only 5 symbols in view of the 12 available symbols in the packet header after channel compensation begins and in view of the combination of symbols over time.
Also similarly, a mean value calculation block 421c receives absolute values from the absolute value block 419c. The absolute value block 419c determines absolute values of symbols which have been combined in time and combined in frequency. Accordingly, the mean value computation block 421c determines mean values over 50 data subcarriers over 5 symbols.
For completeness,
Also, as shown in
The analog baseband signal is converted from analog to digital by the analog-to-digital converter.
A digital processing block 721 of the digital baseband includes circuitry for performing packet detection, frame synchronization, fine automatic gain control processing, and frequency offset estimation. As illustrated in
The demapper demaps the received symbols. In many embodiments the demapper also performs coherent time combining and coherent frequency combining, which may be dependent on selected data rates. A scaler 729 scales the demapped symbols. The scaled demapped symbols are deinterleaved by a deinterleaver block 731, and then decoded by a decoder 733. As illustrated the decoder is a Viterbi decoder. The information is then provided to the MAC.
Accordingly, methods and apparatus for scaling information for a decoder have been discussed. Although the invention has been described in certain specific embodiments, it should be recognized that it may be practiced otherwise than as specifically described. Accordingly, the invention should be considered the claims and their insubstantial variations supported by this disclosure.
This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 60/871,102, filed Dec. 20, 2006, the disclosure of which is incorporated by reference herein.
Number | Date | Country | |
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60871102 | Dec 2006 | US |