Patent Application
20140169114
This application claims priority under 35 USC §119 to Korean Patent Application No. 10-2012-0145080, filed on Dec. 13, 2012, in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein in its entirety by reference.
1. Technical Field
Exemplary embodiments relate to memory devices, and more particularly to a volatile memory device and a memory controller controlling the same.
2. Discussion of the Related Art
A volatile memory device, such as a dynamic random access memory (DRAM), may perform a refresh operation to retain data stored in memory cells. If a memory cell has a retention time shorter than a set or selected refresh period (e.g., a refresh period defined in a standard), a row of memory cells including the memory cell is often replaced with a row of redundancy cells. As the size of a memory cell shrinks, the number of memory cells having retention times shorter than the set refresh period has increased. Accordingly, the number of rows of redundancy cells has increased in conventional volatile memory devices.
Some example embodiments provide a volatile memory device capable of adaptively adjusting refresh intervals.
Some example embodiments provide a memory system and memory controllers capable of adaptively adjusting refresh intervals. Related methods are also provided.
According to some embodiments, a volatile memory device may comprise a memory cell array including a plurality of pages; and a refresh control circuit configured to refresh the plurality of pages every refresh period by performing, during each refresh period, refresh operations at regular refresh intervals to corresponding selected ones of the plurality of pages, and configured to adjust the refresh interval according to a number of the plurality of pages identified as weak pages including at least a weak cell whose data retention time being shorter than a data retention time of normal cells, and configured to refresh the pages identified as weak pages at least twice during each refresh period.
A first page of the pages identified as weak pages may have a first address, the refresh control circuit may be configured to refresh the first page in response to the refresh control circuit generating a refresh address of one of the plurality of pages, and the first address may be the same as the refresh address except that the first address differs from the refresh address by at least one most significant bit (MSB).
The refresh control circuit may be configured to selectively invert the at least one MSB of a refresh address to provide a changed refresh address based on a first comparison of the first address and the refresh address and a second comparison of an abbreviated first address and an abbreviated refresh address, the abbreviated first address and the abbreviated refresh address respectively being the first address and refresh address without the corresponding at least one MSB.
The refresh control circuit may comprise a refresh pulse generator configured to generate a refresh pulse signal having a period corresponding to the refresh interval; a refresh counter configured to generate a refresh address by performing a counting operation in response to the refresh pulse signal; a plurality of comparing units each configured to compare a corresponding one of weak page addresses of the pages identified as weak pages and the refresh address to provide a corresponding first intermediate match signal and configured to compare a corresponding one of abbreviated weak page addresses and an abbreviated refresh address to provide a corresponding second intermediate match signal, each of the abbreviated weak page addresses being the corresponding weak page address without its at least one MSB, the abbreviated refresh address being the refresh address without its at least one MSB; an operation unit configured to provide a first match signal based on the first intermediate match signals and a second match signal based on the second intermediate match signals; a control signal generator configured to generate a halt signal that halts an operation of the refresh counter during the refresh period, based on the first match signal and the second match signal; and an address changing unit configured to selectively invert the at least one MSB of the refresh address to provide a changed refresh address.
The operation unit may comprise a first OR circuit to perform a logical OR operation on the first intermediate match signals to provide the first match signal and a second OR circuit to perform a logical OR operation on the second intermediate match signals to provide the second match signal.
The operation unit may provide the first match signal as a first match detected logic level when the at least one of the weak page addresses match with the refresh address and may provide the second match signal with second match detected logic level when at least one of the abbreviated weak page addresses matches with the abbreviated refresh address.
The control signal generator may be configured to enable the halt signal and to invert the at least one MSB of the refresh address to provide the changed refresh address when the first match signal is not the first match detected logic level and the second match signal is the second match detected logic.
The refresh counter may be configured to halt the counting operation when the halt signal is enabled and when the halt signal is disabled, the refresh counter is configured to restart the counting operation at a refresh address of the refresh counter when the halt signal was enabled.
The volatile memory device may also comprise a weak page register configured to store weak page addresses of the pages identified as weak pages; and a refresh information generator configured to generate a refresh information signal based on the number of the weak pages stored in the weak page register, wherein the refresh control circuit may be configured to adjust the refresh interval according to the refresh information signal.
The volatile memory device may comprise a bank address register configured to store information on a plurality of bank addresses of banks constituting the memory cell array, wherein the refresh control circuit may be configured to refresh the pages identified as weak pages at least twice during the refresh period in a bank corresponding to one of the bank addresses stored in the bank address register.
A memory system may comprise a first volatile memory device; and a memory controller configured to control the first volatile memory device, wherein the first volatile memory device may be configured to provide the memory controller with refresh information signal corresponding to a number of identified weak pages that include at least a weak cell whose data retention time is shorter than a data retention time of normal cells, wherein the memory controller may be configured to provide an auto refresh command to the first volatile memory device at regular refresh intervals over a refresh period and is configured to adjust the refresh interval according to the refresh information signal, and wherein the first volatile memory device may be configured to refresh the plurality of pages in response to auto refresh commands received during the refresh period while refreshing the identified weak pages of the plurality of pages at least twice during the refresh period.
The memory system of may further comprise a memory module including a plurality of volatile memory devices including the first volatile memory device, wherein each of the volatile memory devices may be configured to provide the memory controller with respective refresh information according to a number of identified weak pages of the corresponding volatile memory device.
The memory controller may be configured to provide each of the volatile memory devices with auto refresh commands at respective refresh intervals based on the corresponding refresh information provided to the memory controller by the corresponding volatile memory device.
The memory controller may be configured to provide the plurality of volatile memory devices with auto refresh commands at the same refresh interval.
The volatile memory devices may be configured to perform refresh operations at a timing responsive to the received auto refresh commands and are configured to skip an individual refresh operation based on the refresh information corresponding to the volatile memory device.
A memory controller may comprise a register configured to store refresh information from a first memory device, the refresh information reflecting a number of weak pages of the first memory device; a command generation circuit configured to generate auto refresh commands and periodically transmit an auto refresh command to the first memory device at a first refresh interval, the command generation circuit may be configured to determine a length of the first refresh interval in response to the refresh information.
The memory controller may be configured to communicate with a plurality of memory devices. The register may be configured to store refresh information of the plurality of memory devices, including the first memory device, reflecting a number of pages of the plurality of memory devices identified as weak pages, and, for each of the plurality of memory devices, the command generation circuit may be configured to generate and transmit auto refresh commands periodically at a refresh interval corresponding to the respective memory device and determined by the refresh information of the register corresponding to the respective memory device.
The register may be configured to store refresh information of a second memory device, the refresh information of the second memory device reflecting a number of weak pages of the second memory device, and the command generation circuit may be configured to periodically transmit an auto refresh command to the second memory device at a second refresh interval, the command generation circuit being configured to determine a length of the second refresh interval in response to the refresh information of the second memory device.
The first interval may be different from the second interval.
The memory controller may be configured to communicate with a plurality of memory devices, and the register may be configured to store refresh information of each of the plurality of memory devices, including the first memory device, the refresh information of each memory device reflecting a number of pages of the plurality of memory devices identified as weak pages of that memory device, and the command generation circuit ma be configured to generate and transmit auto refresh commands shared by the plurality of memory devices, the auto refresh commands being transmitted periodically at a refresh interval determined by the command generation circuit, and the refresh interval may be determined by the command generation circuit in response to the refresh information of each of the plurality of memory devices stored.
Accordingly, the interval of the auto refresh command or the self refresh interval may be adaptively adjusted based on the refresh information signal according to the number of the weak pages and the weak pages are refreshed at least twice during the refresh period. Therefore, refresh performance of the volatile memory devices and the memory systems may be enhanced.
Illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. These example embodiments are just that—examples—and many implementations and variations are possible that do not require the details provided herein. It should also be emphasized that the disclosure provides details of alternative examples, but such listing of alternatives is not exhaustive. Furthermore, any consistency of detail between various examples should not be interpreted as requiring such detail—it is impracticable to list every possible variation for every feature described herein. The language of the claims should be referenced in determining the requirements of the invention. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present inventive concept. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting of the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to
In an embodiment, a refresh period tREF may be predetermined, such as that defined by a specification. A refresh interval during the refresh period tREF (e.g., defined in the specification) may be a first refresh interval tREFI1, as illustrated in
For example, assume the refresh row address RA3 is a weak page address having an address of ‘0000000000010’ and the page having the refresh row address ‘0000000000010’ is to be refreshed an additional time during the refresh period. When refresh row addresses gradually increase from ‘0000000000000’ to ‘1111111111111’ the weak page having the refresh row address ‘0000000000010’ is refreshed an additional time when the page having a refresh row address RAP of ‘1000000000010’ is to be refreshed, and then the page having the refresh row address RAP of ‘1000000000010’ is refreshed. It will be noted that the refresh row address RAP is the same as the row address of RA3 with the exception of their most significant bit (MSB). Accordingly, the weak page may be refreshed at least twice during the refresh period tREF.
Referring to
The memory cell array may include first through fourth bank arrays 280a, 280b, 280c and 280d. The row decoder may include first through fourth bank row decoders 260a, 260b, 260c and 260d respectively coupled to the first through fourth bank arrays 280a, 280b, 280c and 280d, the column decoder may include first through fourth bank column decoders 270a, 270b, 270c and 270d respectively coupled to the first through fourth bank arrays 280a, 280b, 280c and 280d, and the sense amplifier unit may include first through fourth bank sense amplifiers 285a, 285b, 385c and 385d respectively coupled to the first through fourth bank arrays 280a, 280b, 280c and 280d. The first through fourth bank arrays 280a, 280b, 280c and 280d, the first through fourth bank row decoders 260a, 260b, 260c and 260d, the first through fourth bank column decoders 270a, 270b, 270c and 270d and the first through fourth bank sense amplifiers 285a, 285b, 285c and 285d may form first through fourth banks Although the volatile memory device 200 is illustrated in
The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from a memory controller (not shown). The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.
The bank control logic circuit 230 may generate bank control signals in response to the bank address BANK_ADDR. One of the first through fourth bank row decoders 260a, 260b, 260c and 260d corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the first through fourth bank column decoders 270a, 270b, 270c and 270d corresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.
The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220, and may receive a changed refresh row address CREF_ADDR from the refresh control circuit 300. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the changed refresh row address CREF_ADDR. A row address output from the row address multiplexer 240 may be applied to the first through fourth bank row decoders 260a, 260b, 260c and 260d.
The activated one of the first through fourth bank row decoders 260a, 260b, 260c and 260d may decode the row address output from the row address multiplexer 240, and may activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address.
The column address latch 250 may receive the column address COL_ADDR from the address register 220, and may temporarily store the received column address COL_ADDR. In some embodiments, in a burst mode, the column address latch 250 may generate column addresses that increment from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address to the first through fourth bank column decoders 270a, 270b, 270c and 270d.
The activated one of the first through fourth bank column decoders 270a, 270b, 270c and 270d may decode the column address COL_ADDR output from the column address latch 250, and may control the input/output gating circuit 290 to output data corresponding to the column address COL_ADDR.
The input/output gating circuit 290 may include circuitry for gating input/output data. The input/output gating circuit 290 may further include an input data mask logic, read data latches for storing data output from the first through fourth bank arrays 280a, 280b, 280c and 280d, and write drivers for writing data to the first through fourth bank arrays 280a, 280b, 280c and 280d.
Data DQ to be read from one bank array of the first through fourth bank arrays 280a, 280b, 280c and 280d may be sensed by a sense amplifier coupled to the one bank array, and may be stored in the read data latches. The data DQ stored in the read data latches may be provided to the memory controller via the data input/output buffer 295. Data DQ to be written to one bank array of the first through fourth bank arrays 280a, 280b, 280c and 280d may be provide from the memory controller to the data input/output buffer 295. The data DQ provided to the data input/output buffer 295 may be written to the one array bank via the write drivers.
The control logic 210 may control operations of the memory device 200a. For example, the control logic circuit 210 may generate control signals for the memory device 200a to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller and a mode register 212 that sets an operation mode of the volatile memory device 200. For example, the command decoder 211 may generate the control signals corresponding to the command CMD by decoding a write enable signal (/WE), a row address strobe signal (/RAS), a column address strobe signal (/CAS), a chip select signal (/CS), etc. The command decoder 211 may further receive a clock signal (CLK) and a clock enable signal (/CKE) for operating the volatile memory device 200 in a synchronous manner. The control logic circuit 210 may control the refresh control circuit 300 to generate the changed refresh row address CREF_ADDR. That is, the control logic circuit 210 may control the refresh control circuit 300 to perform a self refresh operation on the memory cell array in a power down mode of the volatile memory device 200. In addition, the control logic circuit 210 may control the refresh control circuit 300 to perform an auto refresh operation on the memory cell array in response to an auto refresh command from a memory controller in a normal operation mode of the volatile memory device 200.
The address storing unit 225 stores the weak page addresses of the weak pages and provides the refresh control circuit 300 with the refresh information signal RI based on the number of the weak pages. Each weak page includes at least a weak cell whose data whose data retention time being shorter than data retention time of normal cells. In some embodiments, the address storing unit 225 may provide the refresh information signal RI to the memory controller. The memory controller may adjust an interval of auto refresh command provided to the volatile memory device 200 based on the refresh information signal RI.
The refresh control circuit 300 adjusts (or decreases) the refresh interval tREFI based on the weak page addresses WEAK_ADDR and the refresh information signal SI and refreshes the plurality of pages according to increased refresh cycles at the adjusted refresh interval, while the weak pages are refreshed at least twice during the refresh period.
In some embodiments, the address storing unit 225 may be included in the refresh control circuit 300. In this case, the refresh control circuit 300 may provide the refresh information signal RI to the memory controller.
Referring to
For example, when the memory cell array includes 8K pages and the refresh period defined in the specification is 64 ms, the unadjusted refresh interval corresponds to 7.8 us. In this case, when the number of the weak pages is 1K, an adjusted refresh interval may be 64 ms/(8K+1K)=6.9 us. That is, the refresh control circuit 300 may decrease the refresh interval from 7.8 us to 6.9 us to increase a number of refresh cycles up to 1K when the refresh information signal RI is ‘10’ and the refresh control circuit 300 refreshes the weak pages an additional time during each refresh period using the increased number of refresh cycles.
In
Referring to
The refresh pulse generator 310 receives the refresh information signal RI and generates a refresh pulse RCK having a period corresponding to the adjusted refresh interval. The refresh counter 320 generates a refresh row address REF_ADDR by performing counting operation at an increased refresh cycle rate in response to the refresh pulse signal RCK. The comparing units 331˜33k compare each of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk and the refresh row address REF_ADDR to provide a plurality of first intermediate match signals MATCH11˜MATCH1k and compare each of abbreviated weak page addresses and an abbreviated row address to provide a plurality of second intermediate match signals MATCH21˜MATCH2k. Each of the abbreviated weak addresses may be obtained by omitting at least one MSB of each of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk and the abbreviated refresh row address may be obtained by omitting at least one MSB of the refresh row address REF_ADDR.
The operation unit 342a provides a first match signal MATCH1 and a second match signal MATCH2 based on the first intermediate match signals MATCH11˜MATCH1k and the second intermediate match signals MATCH21˜MATCH2k respectively. The operation unit 340a includes OR gates 341a and 342a. The OR gates 341a performs logical OR operation on the first intermediate match signals MATCH11˜MATCH1k to provide the first match signal MATCH1 and the OR gate 342a performs logical OR operation on the second intermediate match signals MATCH21˜MATCH2k to provide the second match signal MATCH2.
Therefore, when at least one of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk matches with the refresh row address REF_ADDR, the first match signal MATCH1 is a logic high level. In addition, when at least one of the abbreviated weak page addresses matches with the abbreviated refresh row address, the second match signal MATCH2 is a logic high level. That is, when at least one of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk matches with the refresh row address REF_ADDR in every bit, the first and second match signals MATCH1 and MATCH2 are logic high level. When at least one of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk matches with the refresh row address REF_ADDR except at least one MSB, the first match signal MATCH1 is logic low level and the second match signal MATCH2 is logic high level.
In
Referring to
Referring back to
Referring to
The refresh row address output unit 361 includes an inverter 362 that inverts the MSB of the refresh row address REF_ADDR, a multiplexer 363 and a plurality of inverters 364˜367. The multiplexer 363 selects one of the MSB RN of the refresh row address REF_ADDR and an output of the inverter 362 to provide MSB CRAN of a changed refresh row address CREF_ADDR. The inverters 364˜367 outputs first through N−1-th bits CRA1 and CRAN−1 of the changed refresh row address CREF_ADDR by delaying the first through N−1-th bits RA1 and RAN−1 of the refresh row address REF_ADDR.
Therefore, when the refresh row address REF_ADDR matches with at least one of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk except at least one MSB, the first match signal MATCH1 is low level and the second match signal MATCH2 is high level, and thus, the halt signal HALT is made a high level and the first selection signal SEL1 is made a high level. Accordingly, the second selection signal SEL2 is a low level causing multiplexer 363 to select the inverted MSB of the refresh row address REF_ADDR (here, the inverted logic value of RAN). The refresh row address output unit 361 thus outputs the changed refresh row address CREF_ADDR with the inverted MSB RAN. When it is not the case that the refresh row address REF_ADDR matches with at least one of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk except at least one MSB, the second selection signal will not be generated to cause selection of the inverted MSB, but will cause selection of MSB to be output as CRAN. As will be apparent, in this instance changed refresh row address CREF_ADDR will be the same as the previously input refresh row address REF_ADDR (i.e., unchanged).
When the halt signal HALT is maintained at high level during the refresh interval, the refresh counter 320 halts its counting operating during this refresh interval. When the halt signal HALT transitions to a low level, the refresh counter 320 starts the counting operation again. The refresh counter 320 resumes the counting operation starting at the refresh row address of the refresh counter when the refresh counter 320 was halted in its the counting operation. The refresh counter outputs the refresh row address REF_ADDR whose MSB is different from the weak page address. In this case, the first match signal MATCH1 is low level and the second match signal MATCH2 is high level. However, the halt signal HALT transitions from high level to low level, the selection signal generator 368 inverts the first selection signal SEL1 to provide the second selection signal SEL2. Since the second selection signal SEL2 is low level even when the first selection signal SEL1 is high level, the refresh row address output unit 361 maintains the MSB RAN of the refresh row address REF_ADDR to output the MSB CRAN of the changed refresh row address CREF_ADDR. Therefore, the refresh operation in
Referring to
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A refresh control circuit 300b of
Referring to
The control signal generator 350b decodes the first and second match signals MATCH1 and MATCH2 to generate the halt signal HALT for halting operation of the refresh counter 320 during the refresh interval and to generate the first selection signal SEL1 for determining at least one MSB of the changed refresh row address CREF_ADDR. The control signal generator 350b enables the halt signal HALT to logic high level and enables the first selection signal SEL1 to logic high level when the first match signal MATCH1 is logic low level and the second match signal MATCH2 is logic high level. The control signal generator 350b maintains the halt signal HALT and the first selection signal SEL1 at a logic low level in other cases. The address changing unit 360 inverts the MSB of the refresh row address REF_ADDR to provide the changed refresh row address CREF_ADDR with an inverted MSB in response to the halt signal HALT and the first selection signal SEL1 in a bank where the refresh row address REF_ADDR is to be changed. The address changing unit 360 may thus invert the MSB of the refresh row address REF_ADDR and may perform additional refresh operation in a bank corresponding to the bank address BANK_ADDR.
Referring to
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In
Referring to
A refresh control circuit 300c of
The multiplexer 310 selects one of the refresh pulse signal RCK from the refresh pulse generator 310 and an auto refresh signal AREF decoded in the command decoder 211 to provide the selected one to the refresh counter 320. That is, the multiplexer 370 selects the auto refresh signal AREF to be provided to the refresh counter 320 in a normal access mode and selects the refresh pulse signal RCK to be provided to the refresh counter 320 in a power down mode.
The refresh control circuit 300c ma sequentially generate the refresh row address REF_ADDR in response to the auto refresh signal AREF that has an interval corresponding to the interval of the auto refresh command from the memory controller 405 in the normal access mode and inverts the MSB of the refresh row address REF_ADDR to provide the changed refresh row address CREF_ADDR when the refresh row address REF_ADDR matches with at least one of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk except the MSB (or except a certain number of MSBs). In addition, the refresh control circuit 300c may sequentially generate the refresh row address REF_ADDR in response to the adjusted refresh pulse signal RCK according to the refresh information signal RI in the power down mode and inverts the MSB of the refresh row address REF_ADDR to provide the changed refresh row address CREF_ADDR when the refresh row address REF_ADDR matches with at least one of the weak page addresses WEAK_ADDR1˜WEAK_ADDRk except the MSB (or except a certain number of MSBs). Therefore, the refresh control circuit 300c generates the refresh row address REF_ADDR according to the adjusted refresh intervals based on the number of the weak pages and performs additional refresh operation on the weak pages in the normal access mode or the power down mode.
Referring to
Each of the volatile memory devices 621˜628 transmits each of refresh information signals RI1˜RI8 to the memory controller 610 through a dedicated transmission line 635. Each of refresh information signals RI1˜RI8 may include identification information for identifying each of the volatile memory devices 621˜628. The memory controller 610 may include an auto refresh timer 611. The auto refresh timer 611 decodes each of the refresh information signals RI1˜RI8 to apply the auto refresh command to each of the volatile memory devices 621˜628 at an individual interval according to decoded refresh information signals RI1˜RI8 of the corresponding volatile memory device.
In some embodiments, the auto refresh timer 611 decodes each of the refresh information signals RI1˜RI8 to apply the auto refresh command to each of the volatile memory devices 621˜628 at same interval according to one of the refresh information signals RI1˜RI8 of a volatile memory device having maximum weak pages.
In some embodiments, when the volatile memory devices 621˜628 perform self refresh operation in the power down mode, each of the memory devices 621˜628 performs self refresh operation at individual refresh cycles according to respective numbers of the weak pages of the respective volatile memory devices. In this case, each weak pages in each of the volatile memory devices 621˜628 are refreshed at least twice during the refresh period independently.
Referring to
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The application processor 710 may execute applications, such as a web browser, a game application, a video player, etc. In some embodiments, the application processor 710 may include a single core or multiple cores. For example, the application processor 710 may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. The application processor 710 may include an internal or external cache memory.
The connectivity unit 720 may perform wired or wireless communication with an external device. For example, the connectivity unit 720 may perform Ethernet communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile telecommunication, memory card communication, universal serial bus (USB) communication, etc. In some embodiments, connectivity unit 720 may include a baseband chipset that supports communications, such as global system for mobile communications (GSM), general packet radio service (GPRS), wideband code division multiple access (WCDMA), high speed downlink/uplink packet access (HSxPA), etc.
The volatile memory device 750 may store data processed by the application processor 710, or may operate as a working memory. For example, the volatile memory device 750 may be a dynamic random access memory, such as DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, etc., or may be any volatile memory device that requires a refresh operation. The volatile memory device 750 may provide the refresh information signal RI according to the number of the weak pages to the application processor 710, and the application processor 710 generates the auto refresh command according to decreased refresh interval such that the weak pages are refreshed at least twice during the refresh period. In addition, the volatile memory device 750 generates the refresh row address according to the adjusted refresh intervals based on the number of the weak pages and performs additional refresh operation on the weak pages in the normal access mode or the power down mode.
The nonvolatile memory device 740 may store a boot image for booting the mobile system 700. For example, the nonvolatile memory device 740 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc.
The user interface 730 may include at least one input device, such as a keypad, a touch screen, etc., and at least one output device, such as a speaker, a display device, etc. The power supply 760 may supply a power supply voltage to the mobile system 1100. In some embodiments, the mobile system 700 may further include a camera image processor (CIS), and/or a storage device, such as a memory card, a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.
In some embodiments, the mobile system 700 and/or components of the mobile system 1100 may be packaged in various forms, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed stack package (WSP).
Referring to
The processor 810 may perform various computing functions, such as executing specific software for performing specific calculations or tasks. For example, the processor 810 may be a microprocessor, a central process unit (CPU), a digital signal processor, or the like. In some embodiments, the processor 810 may include a single core or multiple cores. For example, the processor 810 may be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. Although
The processor 810 may include a memory controller 811 for controlling operations of the memory module 840. The memory controller 811 included in the processor 810 may be referred to as an integrated memory controller (IMC). The memory controller 811 may comprise a memory controller according to other embodiments described herein. A memory interface between the memory controller 811 and the memory module 840 may be implemented with a single channel including a plurality of signal lines, or may be implemented with multiple channels, to each of which at least one memory module 840 may be coupled. In some embodiments, the memory controller 811 may be located inside the input/output hub 820, which may be referred to as memory controller hub (MCH).
The memory module 840 may include a plurality of volatile memory devices that store data provided from the memory controller 811. The volatile memory devices may be a volatile memory device as described according to other embodiments described herein. The volatile memory devices provide the refresh information signal RI according to the number of the weak pages to the memory controller 811, and the memory controller 811 generates the auto refresh command according to decreased refresh interval such that the weak pages are refreshed at least twice during the refresh period. In addition, each of the volatile memory devices may generate the refresh row address according to the adjusted refresh intervals based on the number of the weak pages and performs additional refresh operation on the weak pages in the normal access mode or the power down mode.
The input/output hub 820 may manage data transfer between processor 810 and devices, such as the graphics card 850. The input/output hub 820 may be coupled to the processor 810 via various interfaces. For example, the interface between the processor 810 and the input/output hub 820 may be a front side bus (FSB), a system bus, a HyperTransport, a lightning data transport (LDT), a QuickPath interconnect (QPI), a common system interface (CSI), etc. Although
The graphics card 850 may be coupled to the input/output hub 820 via AGP or PCIe. The graphics card 850 may control a display device (not shown) for displaying an image. The graphics card 850 may include an internal processor for processing image data and an internal memory device. In some embodiments, the input/output hub 820 may include an internal graphics device along with or instead of the graphics card 850 outside the graphics card 850. The graphics device included in the input/output hub 820 may be referred to as integrated graphics. Further, the input/output hub 820 including the internal memory controller and the internal graphics device may be referred to as a graphics and memory controller hub (GMCH).
The input/output controller hub 830 may perform data buffering and interface arbitration to efficiently operate various system interfaces. The input/output controller hub 830 may be coupled to the input/output hub 820 via an internal bus, such as a direct media interface (DMI), a hub interface, an enterprise Southbridge interface (ESI), PCIe, etc. The input/output controller hub 830 may provide various interfaces with peripheral devices. For example, the input/output controller hub 830 may provide a universal serial bus (USB) port, a serial advanced technology attachment (SATA) port, a general purpose input/output (GPIO), a low pin count (LPC) bus, a serial peripheral interface (SPI), PCI, PCIe, etc.
In some embodiments, the processor 810, the input/output hub 820 and the input/output controller hub 830 may be implemented as separate chipsets or separate integrated circuits. In other embodiments, at least two of the processor 810, the input/output hub 820 and the input/output controller hub 830 may be implemented as a single chipset.
As mentioned above, the interval of the auto refresh command or the self refresh interval may be adaptively adjusted based on the refresh information signal according to the number of the weak pages and the weak pages are refreshed at least twice during the refresh period. Therefore, refresh performance of the volatile memory devices and the memory systems may be enhanced.
The present inventive concept may be applied to any volatile memory device that requires a refresh operation and to a system including the volatile memory device. The present inventive concept may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc. The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2012-0145080 | Dec 2012 | KR | national |
