Patent Application
20180152176
Disclosed aspects are directed to integrated circuit designs dual voltage domains. Specifically, exemplary aspects are directed to voltage aware circuits for widening pulse width and delaying leading edge of dual voltage domain signals.
Computer processing systems use several kinds of memory structures. Dual voltage memory array designs, for example, may include memory cells which are placed in a higher voltage domain to improve data retention, while peripheral logic such as write drivers may be placed in a lower voltage domain to reduce their power consumption. Voltage level shifters may be employed to shift signals from the write drivers from one voltage level to another.
In such dual voltage designs, as the low voltage of the low voltage domain goes lower (e.g., with advances in logic technologies), the voltage difference between two voltage domains may increase because advances in memory technologies may not be at the same pace to permit decreases in the high voltage domains that memory arrays are placed in. Device variations at the low voltage domain may start to play more significant roles as the voltage difference increases. This is because signals in the low voltage domain may be slower (i.e., lower frequency) than their counterparts in the high voltage domains. Correspondingly, it becomes difficult for the low voltage domain signals to meet critical timing margins (e.g., setup times, hold times, etc., relative to signals in the high voltage domains).
A conventional approach to handling the dual voltage signals involves adding dedicated voltage sensitive or voltage aware delay elements as well as pulse width extension circuits for signals in the high voltage domain to accommodate their slower counterparts in the low voltage domains. However, the delay elements and pulse width extension circuits are placed in series in conventional designs, which increases the overall delay for timing critical paths; moreover, the delay elements and pulse width extension circuits also add corresponding costs.
Accordingly, there is a need in the art for better solutions for handling dual voltage domain signals, while avoiding the aforementioned drawbacks of conventional designs.
Exemplary aspects include systems and methods related to pulse generation in a dual voltage domain. A first and a second voltage aware branch sensitive to a low voltage domain are disclosed. The first voltage aware branch includes an inverter in the low voltage domain for delaying a leading edge of an output pulse in a high voltage domain from a leading edge of an input pulse in the high voltage domain. The second voltage aware branch includes a delay element in the low voltage domain for extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse.
For example, an exemplary aspect is directed to a method of managing a pulse signal in a dual voltage domain. The method comprises receiving an input pulse in a high voltage domain, delaying a leading edge of an output pulse in the high voltage domain from a leading edge of an input pulse in a first voltage aware branch sensitive to a low voltage domain, and extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse in a second voltage aware branch sensitive to the low voltage domain.
Another exemplary aspect is directed to apparatus comprising a first voltage aware branch sensitive to a low voltage domain, configured to delay a leading edge of an output pulse in a high voltage domain from a leading edge of an input pulse in the high voltage domain, and a second voltage aware branch sensitive to the low voltage domain, configured to extend a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse.
Yet another exemplary aspect is directed to an apparatus comprising a first means sensitive to a low voltage domain, for delaying a leading edge of an output pulse in a high voltage domain from a leading edge of an input pulse in the high voltage domain, and a second means sensitive to the low voltage domain, for extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse.
The accompanying drawings are presented to aid in the description of embodiments of the invention and are provided solely for illustration of the embodiments and not limitation thereof.
Aspects of the invention are disclosed in the following description and related drawings directed to specific embodiments of the invention. Alternative embodiments may be devised without departing from the scope of the invention. Additionally, well-known elements of the invention will not be described in detail or will be omitted so as not to obscure the relevant details of the invention.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term “embodiments of the invention” does not require that all embodiments of the invention include the discussed feature, advantage or mode of operation.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Further, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequences of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the invention may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example, “logic configured to” perform the described action.
Exemplary aspects are generally directed to dual voltage circuits for generating pulses in high voltage domains taking into account a voltage differential between the high voltage domain and a low voltage domain. For example, if the voltage of the low voltage domain goes lower, increasing the difference between the high voltage domain and the low voltage domain, then the exemplary circuits correspondingly modify pulse shapes in the high voltage domains. In one aspect the same circuit is used to delay a leading edge of a pulse in the high voltage domain as well as widen a width of the pulse, taking into account the differential between the high voltage domain and the low voltage domain, while avoiding additional delay elements.
With reference to
In this disclosure, circuit 100 is said to comprise two paths or branches. A first branch comprises a low voltage delay element such as a first inverter, shown as inverter 122 in a low voltage domain (e.g., is supplied operating voltage in the low voltage domain, representatively shown in the depiction of
Circuit 100 also includes a second branch which may be used to generate a width of output pulse 134 by applying a voltage aware pulse width widening of input pulse 102. The second branch comprises a second inverter, shown as inverter 104 in the high voltage domain and a delay element shown as low voltage domain delay element 106. In
The operation of circuit 100 will now be described with combined reference to the structure of circuit 100 in
At time t1, input pulse 102 falls, and after the time delay associated with the low voltage domain inverter 122, the output of inverter 122 will start to rise, which is a slow path (due to inverter 122 operating in the low voltage domain) that will eventually cause NFET 126 to turn on. With falling input pulse 102, the output of high voltage domain inverter 104 in the second branch will rise faster and NFET 124 will turn on before NFET 126 turns on from the slower path through the first branch. The combination of NFETs 124 and 126 will pull down output pulse 134, which will cause the leading edge of output pulse 134 to fall to logic “0” at time t2. Since the slower path through NFET 124 is controlled by low voltage domain inverter 122, the corresponding fall of output pulse 134 at time t2 is also controlled by low voltage domain inverter 122. Thus, the first branch comprising low voltage domain inverter 122 provides a voltage aware leading edge delay for the leading edge of output pulse 134.
With continued combined reference to
In an aspect of circuit 100, it is possible for the late arriving signals through the above-mentioned low voltage domain delay elements to cause fluctuations in output pulse 134 while it is in the low logic level (and more specifically, during the duration of time between t3 and t4 from when input pulse 102 rises to when output pulse 134 rises).
To prevent such fluctuations, latches 118 and 132 are provided. Latch 118 includes a feedback path comprising PFETs 112 and 113 which keeps PFET 120 turned off, and latch 132 involves NFETS 128 and 130 to keep output pulse 134 pulled low for the duration of the low logic level of output pulse 134. During this period NFET 130 is turned on, providing a path to ground for output pulse 134. PFET 110 is turned on until time input signal 102 starts to rise at time t3. PFET 112 is on while input signal 102 is low. Once input signal 102 starts to rise at time t3, after a time delay through low voltage domain delay element 106, PFET 112 will turn off, thus disassociating the influence of latch 118, following which, output pulse 134 will be allowed to rise at time t4. Thus, during the time between t3 and t4, any fluctuations on input pulse 102 will not affect output pulse 134.
It will be appreciated that exemplary aspects include various methods for performing the processes, functions and/or algorithms disclosed herein. For example, as illustrated in
Block 302 comprises receiving an input pulse in a high voltage domain. For example, input pulse 102 is received in the high voltage domain.
Block 304 comprises delaying a leading edge of an output pulse in the high voltage domain from a leading edge of an input pulse, in a first voltage aware branch sensitive to a low voltage domain. For example, the leading edge of output pulse 134 is delayed from the leading edge of input pulse 102 using the first branch comprising inverter 122 in the low voltage domain.
Block 306 comprises extending a pulse width of the output pulse in the high voltage domain from a pulse width of the input pulse in a second voltage aware branch sensitive to the low voltage domain. For example, the pulse width of output pulse 134 is widened using the second branch comprising the low voltage domain delay element 106.
In some aspects, method 300 may further comprise avoiding fluctuations on output pulse 134 for a duration of the pulse width of output pulse 134, with a first latch coupled to the first voltage aware branch (e.g., latch 118 including a feedback path comprising PFETs 112 and 113 which keeps PFET 120 turned off) and a second latch coupled to the second voltage aware branch (e.g., latch 132 including NFETS 128 and 130 to keep output pulse 134 pulled low for the duration of the low logic level of output pulse 134). As discussed above, in method 300, a delay on the leading edge of the output pulse and the pulse width of the output pulse may be increased if a voltage of the low voltage domain decreases in comparison to a voltage of the high voltage domain.
Referring now to
In a particular embodiment, input device 430 and power supply 444 are coupled to the system-on-chip device 422. Moreover, in a particular embodiment, as illustrated in
It should be noted that although
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an embodiment of the invention can include a computer readable media embodying a method for managing a pulse signal in a dual voltage domain. Accordingly, the invention is not limited to illustrated examples and any means for performing the functionality described herein are included in embodiments of the invention.
While the foregoing disclosure shows illustrative embodiments of the invention, it should be noted that various changes and modifications could be made herein without departing from the scope of the invention as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the embodiments of the invention described herein need not be performed in any particular order. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
