Voltage clamping circuits using MOS transistors and semiconductor chips having the same and methods of clamping voltages

Abstract

A clamping circuit is provided, which may clamp a voltage at a node of a circuit to a stable level by using a transistor already included in the circuit. The clamping circuit may clamp a voltage at a first node of a circuit inside a semiconductor chip to a more stable level when electro-static discharge (ESD) occurs. The clamping circuit may include a transistor and a capacitive element to store a control voltage to turn on the transistor in response to ESD.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will become more apparent by describing in detail example embodiments with reference to the attached drawings in which:

FIG. 1 is a circuit diagram illustrating a conventional level shifter included in a semiconductor chip;

FIG. 2 is a circuit diagram illustrating a clamping circuit, according to an example embodiment;

FIG. 3 is a circuit diagram illustrating a level shifter/clamping circuit, where the circuit 10 of FIG. 2 may be a level shifter, according to an example embodiment;

FIG. 4 is a block diagram illustrating a semiconductor chip, according to an example embodiment; and

FIGS. 5A and 5B are graphs illustrating an operation result of a clamping circuit, according to an example embodiment in comparison with conventional art.

Claims

1. A clamping circuit to clamp a voltage at a first node of a first circuit, the first circuit to send and/or receive signals through a first pad, the clamping circuit comprising: a MOS transistor of the first circuit, a first electrode of the MOS transistor connected to the first node and a second electrode of the MOS transistor connected to a ground voltage; anda capacitive element connected between the first pad and the MOS transistor, the capacitive element storing a control voltage to turn on the MOS transistor in response to electro-static discharge (ESD).

2. The clamping circuit of claim 1, wherein: the MOS transistor is a gate coupled NMOS (GCNMOS) transistor; andthe capacitive element is connected between the first pad and a gate electrode of the GCNMOS transistor.

3. The clamping circuit of claim 1, wherein the capacitive element is a capacitor.

4. The clamping circuit of claim 1, wherein: the first circuit is a level shifter including a pair of PMOS transistors forming a latch structure and a pair of NMOS transistors that are connected to the PMOS transistors;the MOS transistor is one of the pair of NMOS transistors; andthe first node is an output node of the level shifter.

5. The clamping circuit of claim 4, wherein the output node of the level shifter outputs a voltage at the first node.

6. The clamping circuit of claim 1, wherein: a voltage drop circuit is connected between a second node and a ground voltage; andthe second node is where the MOS transistor and the capacitive element are connected.

7. A semiconductor chip comprising; the clamping circuit of claim 1; anda second pad, wherein, the first circuit outputs a voltage at the first node to a second circuit as a voltage signal.

8. The semiconductor chip of claim 7, wherein: the MOS transistor is a gate coupled NMOS (GCNMOS)transistor; andthe capacitive element is connected between the first pad and a gate electrode of the GCNMOS transistor.

9. The semiconductor chip of claim 7, wherein: the first circuit is a level shifter including a pair of PMOS transistors forming a latch structure and a pair of NMOS transistors that are connected to the PMOS transistors;the MOS transistor is one of the pair of NMOS transistors; andthe first node is an output node of the level shifter.

10. The semiconductor chip of claim 9, wherein the level shifter outputs a voltage at the first node.

11. The semiconductor chip of claim 7, wherein: a voltage drop circuit is connected between a second node and a ground voltage; andthe second node is where the MOS transistor and the capacitive element are connected.

12. The semiconductor chip of claim 7, further comprising: a first switch connected between a second pad and the second circuit;a second switch connected between the first pad and the clamping circuit; anda logic gate connected to an input of the clamping circuit.

13. The semiconductor chip of claim 12, wherein the first switch transmits control signals to an input of the second circuit.

14. The semiconductor chip of claim 12, wherein the second switch transmits control signals to the clamping circuit.

15. The semiconductor chip of claim 12, wherein the second circuit is an electrically erasable programmable read-only memory (EEPROM).

16. The semiconductor chip of claim 15, wherein the logic gate receives a data signal and a write enable signal for the EEPOM.

17. The semiconductor chip of claim 12, wherein the logic gate is a NOR gate.

18. A method of clamping a voltage of a first node of a first circuit in response to electro-static discharge (ESD), the method comprising: storing a voltage in a capacitance connected to a MOS transistor of a circuit in response to the ESD; andclamping the voltage of the first node by turning on the MOS transistor with the stored voltage in response to the ESD.

19. The method of claim 18, further comprising: transferring excess charge from the ESD to ground through at least one of the capacitance and a voltage drop circuit.

20. The method of claim 19, further comprising: turning off the MOS transistor.