Number | Date | Country | Kind |
---|---|---|---|
11-044891 | Feb 1999 | JP |
Number | Name | Date | Kind |
---|---|---|---|
5191301 | Mullgrav, Jr. | Mar 1993 | |
5239274 | Chi | Aug 1993 |
Number | Date | Country |
---|---|---|
9-214299 | Aug 1997 | JP |
Entry |
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“A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors”, I. A. Young et al., IEEE Journal of Solid-State Circuits, vol. SC-27, Nov. 1992, pp. 1599-1607. |
“A 0.35 μm CMOS 3-880 MHz PLL N/2 Clock Multiplier and Distribution Network with Low Jitter for Microprocessors”, I. A. Young et al., 1997 IEEE International Solid-State Circuits Conference, pp. 330-331. |
“Monolithic Phase-Locked Loops and Clock Recovery Circuits”, B. Razavi, IEEE Press Marketing, 1996, pp. 20-21. |