VOLTAGE CONTROLLED OSCILLATOR USING CAPACITIVE DEGENERATION

Abstract

A VCO is based on a capacitively emitter degenerated topology which uses a cross-coupled MOS pair as the degeneration cell. The cross-coupled MOS pair contributes additional conductance and results in a higher maximum attainable oscillation frequency and better negative resistance characteristics as compared to the other topologies at high frequencies. These properties of the disclosed VCO combined with small effective capacitance enable low-power low-noise high-frequency VCO implementations.

Description

LIMITED COPYRIGHT WAIVER

A portion of the disclosure of this patent document contains material to which the claim of copyright protection is made. The copyright owner has no objection to the facsimile reproduction by any person of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office file or records, but reserves all other rights whatsoever. Copyright © 2005, Regents of the University of Minnesota.

FIELD

The embodiments relate generally to voltage controlled oscillators and more particularly to a voltage controlled oscillator using capacitive degeneration.

BACKGROUND

Today there are a wide variety of computer and telecommunications devices, such as personal computers (PCs), mobile telephones, and personal digital assistants (PDAs), that need to share information with each other. Generally, this information is communicated from a sending device to a receiving device.

The sending device generally has the data in the initial form of a set of digital words (sets of ones and zeros). In the sending device, a transmitter circuit converts each word into a sequence of electrical pulses, and transmits the sequence of pulses through a cable, circuit board, or other medium to the receiving device. The receiving device includes a receiver circuit that identifies each of the pulses in the signal as a one or zero, enabling it to reconstruct the original digital words.

A key component in both the transmitter and the receiver is a voltage-controlled oscillator, a circuit that produces a signal that varies back and forth between two voltage levels at a frequency based on an input control voltage. The transmitter uses a VCO to place digital information into a high-frequency carrier signal, and the receiver uses a VCO to separate the digital information from the high-frequency carrier signal. Thus, voltage-controlled oscillators (VCOs) are critical building blocks in high-performance communication systems. The ever-increasing demand for bandwidth places very stringent frequency, power, and noise requirements on such systems.

SUMMARY

In general, the embodiments of the invention are directed to a voltage controlled oscillator (VCO) design using capacitive degeneration. The VCO employs a negative resistance cell topology that supports high-frequency performance in a low-power, low-noise implementation.

The VCO may include a negative resistance cell that is based on a capacitively emitter-degenerated topology, but employs a cross-coupled MOS pair as a degeneration cell. The cross-coupled MOS pair contributes additional conductance and allows the negative resistance cell to have a higher maximum attainable oscillation frequency and enhanced negative resistance characteristics in comparison with other topologies at high frequencies. These properties, combined with relatively small effective capacitance, enable low-power, low-noise high-frequency VCO implementations.

In one embodiment, a negative resistance cell is formed by two bipolar transistors that are interconnected via two field-effect transistors, such as NMOS field-effect transistors. An emitter of a first bipolar transistor is coupled to a gate of a first field-effect transistor and a drain of a second field-effect transistor. An emitter of a second bipolar transistor is coupled to a gate of the second field-effect transistor and a drain of the first field-effect transistors. In this manner, the two bipolar transistors are interconnected using the cross-coupled field-effect transistor pair.

The capacitance between the gate and the source of each of the field-effect transistors provides a capacitance that is equivalent to a degeneration capacitor of a capacitive emitter degenerated transistor. In addition, the positive feedback path of the cross-coupled field-effect transistors provides additional transconductance to improve the negative resistance value. The combined effect of the emitter degeneration and the additional transconductance allow the negative resistance cell to generate an effective negative resistance using small bias currents, thus reducing power consumption and noise contribution of the VCO core.

The VCO also may include a current source that: is connected to the source of each of the field-effect transistors. Additionally, the VCO may include one or more buffers to buffer the output of the VCO. In one embodiment, the VCO includes a pair of buffers, one coupled to the emitter of the first bipolar transistor and the other coupled to the emitter of the second bipolar transistor, An exemplary buffer for effectively buffering the output of the VCO is an emitter-follower.

Some embodiments may provide various advantages over simple cross-coupled negative resistance cells and capacitor emitter-degenerated negative resistance cells. For example, the combined effect of the emitter degeneration and the additional transconductance allows the negative resistance cell to generate an effective negative resistance using small bias currents, thus reducing power consumption and noise contribution of the VCO core. In addition, the cross-coupled field-effect transistors increase the maximum attainable oscillation frequency of the VCO. Also, in some embodiments the common-mode admittance of the field-effect transistor pair is near zero reducing the susceptibility of the VCO to common-mode oscillations.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 is an illustration of a parallel LC oscillator circuit model.

FIGS. 2A-2D illustrate cross-coupled negative resistance cells.

FIGS. 3A and 3B are graphs illustrating the negative resistance for a cross-coupled cell.

FIG. 4 is circuit schematic for a VCO core coupled to a buffer.

FIG. 5 illustrates a parallel LC oscillator model including buffer stage impedance.

FIGS. 6A and 6B are oscillator output admittance examples for BJT and MOS VCOs.

FIG. 7 illustrates pole frequency versus load capacitance of the buffer stage.

FIG. 8 illustrates a single-ended negative resistance cell using capacitive emitter degeneration.

FIG. 9 illustrates a differential negative resistance cell using capacitive degeneration and cross-coupled MOS transistors according to embodiments of the invention.

FIG. 10 illustrates an equivalent small-signal circuit model for the negative resistance cell illustrated in FIG. 9 according to embodiments of the invention.

FIG. 11 is a plot of R versus δ for different values of g_m1.

FIG. 12 is a plot of simulated R_Eq for the cross-coupled, capacitively degenerated, and cells according to embodiments of the invention.

FIG. 13 is a plot of simulated R_Eq for the cross-coupled, capacitively degenerated, and cells according to embodiments of the invention.

FIG. 14 illustrates a common-mode circuit equivalent for a capacitively emitter-degenerated cell according to embodiments of the invention.

FIG. 15 is a plot showing common-mode negative resistance simulation results.

FIG. 16 illustrates a common-mode tank schematic with bias network impedance according to embodiments of the invention.

FIG. 17 is a graph illustrating common-mode and differential-mode oscillation simulations.

FIGS. 18A and 18B illustrate tank-loading characteristics of a cross-coupled cell and a cell according to embodiments of the invention.

FIG. 19 is a graph illustrating a simulated tuning range versus effective capacitance of a negative resistance cell according to embodiments of the invention.

FIG. 20 is a chip microphotograph and layout according to embodiments of the invention.

FIG. 21 shows the measured output power spectrum of a 20-GHz oscillation signal according to an embodiment of the invention.

FIGS. 22A and 22B are graphs illustrating measured tuning range and simulated frequency variation according to the temperature and process variation and according to an embodiment of the invention.

FIG. 23 is a graph illustrating measured power variation in an embodiment of the invention.

FIGS. 24A and 24B illustrate phase-noise measurement of an embodiment of the invention.

FIG. 25 is a graph illustrating locking range and phase-noise measurement results of an embodiment of the invention.

DETAILED DESCRIPTION

In the following detailed description of example embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the example method, apparatus and system may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of this description.

In the following detailed description, reference is made to specific examples by way of drawings and illustrations. These examples are described in sufficient detail to enable those skilled in the art to practice the inventive subject matter, and serve to illustrate how the inventive subject matter may be applied to various purposes or embodiments. Other embodiments are included within the inventive subject matter, as logical, mechanical, electrical, and other changes may be made to the example embodiments described herein. Features or limitations of various embodiments described herein, however essential to the example embodiments in which they are incorporated, do not limit the inventive subject matter as a whole, and any reference to the invention, its elements, operation, and application are not limiting as a whole, but serve only to define these example embodiments. The following detailed description does not, therefore, limit embodiments of the invention, which are defined only by the appended claims.

I. LC-Tank-Based VCO Design Factors

This section analyzes the maximum attainable frequency of oscillation of a typical LC VCO which uses the traditional cross-coupled negative resistance cell. In addition, differences in behavior of a BJT-based and a CMOS-based negative resistance cell are discussed. A novel negative resistance cell that overcomes the frequency limits of the traditional cross-coupled negative resistance cell is presented along with design issues related to the novel architecture.

FIG. 1 shows a simplified circuit model for a parallel LC oscillator in steady state, where the resistance R_p represents the tank loss, R_Eq is the effective negative resistance generated by the active devices, and C_Eq is the effective shunt capacitance contributed by the active devices in the negative resistance cell. For stable oscillation, the magnitude of the effective negative resistance R_Eq has to be smaller than R_p. Additionally, for high-frequency operation where C_Var is small, the effective capacitance C_Eq becomes comparable to C_Var and may significantly limit the maximum attainable oscillation frequency and tuning range.

The traditional cross-coupled cell which is known also as the negative g_m cell is used widely due to its simplicity and its ability for differential signaling. First, limitations of the traditional cross-coupled cell in both BiCMOS and CMOS form are discussed. Though some embodiments are implemented in the IBM SiGe BiCMOS process, for comparison purposes, all simulations discussed in this specification use either the 0.25-m IBM SiGe BiCMOS process or the 0.18-mTSMC CMOS process.

In some parts of this section, small-signal models are used for the behavioral analysis of the different negative resistance cells.

A. Maximum Attainable Oscillation Frequency for the Cross-Coupled Negative Resistance Cell

This section evaluates the maximum frequency of oscillation for a given power budget for BJT and MOS implementations of the cross-coupled structure. Several factors (e.g., negative resistance cell design, buffer stage bandwidth, frequency tuning range, and the parasitic capacitances of the constituent components) affect the maximum oscillation frequency. Due to its higher transconductance per unit current, the BJT implementation provides a better R_Eq. However, as will be shown later, the finite base resistance severely limits the maximum attainable oscillation frequency.

1) Negative Resistance Cell

Mechanisms that degrade high-frequency performance in a cross-coupled negative resistance cell will now be considered. FIGS. 2A-2D show simplified circuit schematics for the BJT-based (FIG. 2A) and CMOS-based (FIG. 2B) cross-coupled cells, the shunt equivalent model (FIG. 2C), and the differential small-signal R_{Eq ∥}C_Eq model for the BJT version (FIG. 2D). At low frequencies, R_Eq is approximately −2/g_m where g_m is the device transconductance. Typically, BJTs have a higher g_m than CMOS transistors for a given bias current and may be a better choice for low-power design. Additionally, the lower flicker noise corner may make BJT devices a better candidate for low-power low-noise oscillator design. However, with increasing frequency, the magnitude of |R_Eq| becomes large and eventually R_Eq flips over and becomes positive. This is primarily due to the non-negligible base resistance, r_b, at high frequencies.

At high frequencies, the impedance offered by the base-emitter capacitance C_π becomes comparable to r_b with a result that a larger portion of the base voltage will appear across r_b rather than C_π. Additionally, there is a phase difference between the voltage across C_π and the base voltage due to the resistor-capacitor voltage division. The voltage across C_π can be calculated using the small-signal model shown in FIG. 2D. Using the voltage division ratio v_π/v_in, an effective transconductance may be defined as: $\begin{array}{cc}{G}_{m,\mathrm{eff}}\equiv \frac{v_{\pi }}{v_{in}}\equiv {\mathrm{Ag}}_m& \left(1\right)\end{array}$ In FIG. 2D, the difference between the transconductor current and i_π is returned to the signal source, thereby generating a negative resistance. A relationship between the current i_π and the conductance associated with this current (g_π) is given by g_π≡i_π/v_in. Only the real parts of G_{m, eff} and g_π contribute to the equivalent negative resistance. Therefore, R_Eq can be approximated as $\begin{array}{cc}{R}_{\mathrm{Eq}}\approx \frac{-2}{\mathrm{Re}\left[G_{m,\mathrm{eff}}\right]-\mathrm{Re}\left[g_{\pi }\right]}& \left(2\right)\end{array}$ Equation (2) suggests that R_Eq degrades rapidly as Re[g_π] approaches Re[G_{m, eff}] and has a distinct corner frequency which will be revisited next using simulations. An expression for the negative-to-positive transition frequency of R_Eq(ω_tran) can be calculated by considering the condition Re[G_{m, eff}]−Re[g_π]≦0, which results in $\begin{array}{cc}{\omega }_{\mathrm{tran}}=\sqrt{\frac{\left(1+\frac{r_b}{r_{\pi }}\right)\left(g_m-\frac{1}{r_{\pi }}\right)}{r_b{C}_{\pi }^2}}.& \left(3\right)\end{array}$ Assuming r_b/r_π<<1, r_π=β/g_m, and B>>1 where β is the base-to-collector current gain, then equation (3) can be simplified to $\begin{array}{cc}{\omega }_{\mathrm{tran}}\approx \sqrt{\frac{{\omega }_T}{r_b{C}_{\pi }}}& \left(4\right)\end{array}$ where ω_T=g_m/C_π. For the MOS version of the cross-coupled structure, r_b and C_π are replaced with r_g and C_gS. Equation (4) shows that the transition frequency is a strong function of the bias current, device size, and base resistance. In the case of the MOS transistor, a multiple-finger layout may be used to drastically minimize gate resistance. On the other hand, in the case of the BJT transistor, the relatively high base resistance of the BJT in comparison to the gate resistance of the CMOS device can result in a lower transition frequency, despite its higher ω_t. FIG. 3A shows the simulated R_Eq and C_Eq for the BJT and MOS cross-coupled cells using the 0.25-μm BiCMOS and 0.18-μm CMOS technologies, respectively, at a bias current of 2 mA. It can be seen that the BJT-based design shows a smaller |R_Eq| than its CMOS counterpart at low frequencies due to its higher transconductance value. However, it has a much lower transition frequency (˜28 GHz) as compared to the CMOS case (˜53 GHz). FIG. 3B shows plots for |R_Eq| for the BJT and MOS cross-coupled structures using equation (2). It can be seen that equation (2) predicts the rapid degradation of |R_Eq| after a certain corner frequency. Increasing the bias current increases ω_t and hence increases the transition frequency. This implies that a low base (gate) resistance design is desirable not only from a noise performance perspective but also from a low-power implementation perspective. This analysis suggests that a careful layout is desirable to increase the transition frequency especially for the CMOS case where the gate resistance can be reduced substantially by appropriate layout techniques without any serious impact on ω_t and/or C_gs.

2) Buffer Stage Design

Another factor that impacts the maximum attainable frequency of oscillation is the buffer stage. Buffer stages are usually implemented as emitter followers because of their high input impedance and wide bandwidth. FIG. 4 shows the simplified circuit schematic for the VCO core coupled to a buffer. The input admittance Y_BI of the buffer stage can be written as $\begin{array}{cc}{Y}_{\mathrm{BI}}=\frac{1}{Z_L\left[1+\frac{r_{\pi }}{1+\mathrm{j\omega }{C}_{\pi }{r}_{\pi }}\left(g_m+\frac{1}{Z_L}\right)\right]}.& \left(5\right)\end{array}$ When the load impedance is resistive, Z_L=R_S, the effective input shunt resistance and capacitance looking into the buffer are given by $\begin{array}{cc}\begin{array}{c}{R}_{\mathrm{Eq},\mathrm{BI}}=R_S\frac{{\left[1+\beta \left(1+\frac{1}{g_m{R}_S}\right)\right]}^2+{\left(\beta \frac{\omega }{{\omega }_T}\right)}^2}{1+\beta \left(1+\frac{1}{g_m{R}_S}\right)+{\left(\beta \frac{\omega }{{\omega }_T}\right)}^2}\\ \approx R_S\left[1+{\left(\frac{{\omega }_T}{\omega }\right)}^2{\left(1+\frac{1}{g_m{R}_S}\right)}^2\right]\end{array}& \left(6\right)\\ \begin{array}{c}{C}_{\mathrm{Eq},\mathrm{BI}}=C_{\pi }\frac{r_{\pi }^2\left(\frac{g_m}{R_S}+\frac{1}{R_S^2}\right)}{{\left[1+r_{\pi }\left(g_m+\frac{1}{R_S}\right)\right]}^2+{\left(\omega C_{\pi }{r}_{\pi }\right)}^2}\\ \approx \frac{1}{{\omega }_T{R}_S}\frac{\left(1+\frac{1}{g_m{R}_S}\right)}{{\left(1+\frac{1}{g_m{R}_S}\right)}^2+{\left(\frac{\omega }{{\omega }_T}\right)}^2}.\end{array}& \left(7\right)\end{array}$ If it is assumed that β>>1 and ω−ω_T, then the approximations shown in equations (6) and (7) may be made. It is desirable that R_{Eq, BI} is large enough so as not to reduce the loaded Q of the tank, while C_{Eq, BI} is small enough not to limit the frequency tuning range. In many integrated transceiver designs, the buffer drives an internal capacitive load C_L, in which case the effective shunt resistance and capacitance looking into the buffer input are now as follows: $\begin{array}{cc}{R}_{\mathrm{Eq},\mathrm{BI}}=-\frac{{\left(1+g_m{r}_{\pi }\right)}^2+{\omega }^2{r_{\pi }^2\left(C_{\pi }+C_L\right)}^2}{{\omega }^2{r}_{\pi }{C}_L\left(g_m{r}_{\pi }{C}_{\pi }-C_L\right)}& \left(8\right)\\ C_{\mathrm{Eq},\mathrm{BI}}=\frac{\left(1+g_m{r}_{\pi }\right)C_L+{\omega }^2{r}_{\pi }^2{C}_{\pi }{C}_L\left(C_{\pi }+C_L\right)}{{\left(1+g_m{r}_{\pi }\right)}^2+{\omega }^2{r_{\pi }^2\left(C_{\pi }+C_L\right)}^2}.& \left(9\right)\end{array}$ Equation (8) predicts a negative input resistance at the buffer input when g_m r_π>C_L/C_π. This condition is easily met as g_m r_π(=β) can easily be greater than ten. This additional negative resistance provided by the buffer can be utilized by the VCO core when driving a capacitive load. FIG. 5 shows the small-signal model for the VCO core and buffer load. The combined negative resistance is equal to (R_Eqμ2 R_{Eq, BI}). The negative resistance provided by the buffer reduces the g_m requirement of the cross-coupled cell and hence can be used to reduce power consumption and noise. Equation (9) predicts that the effective shunt capacitance is smaller than C_π or C_L, which allows for high-frequency design and wider tuning range. This basic negative resistance seen in the buffer due to capacitive emitter degeneration may be used to build a novel negative resistance cell for the VCO as described in the following sections.

The impedance looking at the output of the buffer Z_BO determines the bandwidth of the buffer. In a normal common base amplifier configuration, the output impedance is equal to ˜1/g_m, buffer at low frequencies. However, when driven by a high-impedance oscillator, Y_OSC affects Z_BO as shown in FIG. 4. The output impedance for this configuration is given by $\begin{array}{cc}{Z}_{\mathrm{BO}}=\frac{Z_{\pi }+Z_{\mathrm{OSC}}}{g_{m,\mathrm{buffer}}{Z}_{\pi }+1}& \left(10\right)\end{array}$ where Z_π=(1/s C_π∥r_{π) and ZOSC}=1/Y_OSC. FIGS. 6A and 6B show circuit and bias details for MOS (FIG. 6A) and bipolar (FIG. 6B) oscillator cores. The oscillator admittance Y_OSC is a strong function of Z_biasL and Z_biasC as well as Y_BI. Nevertheless, because the real part of Z_BO tends to increase with an increasing base impedance, an optimistic pole frequency produced at the emitter of the buffer stage can be derived and given by $\begin{array}{cc}{\omega }_{\mathrm{Pole}}=\frac{g_{m,\mathrm{buffer}}}{C_L}& \left(11\right)\end{array}$ This pole frequency has to be higher than the oscillation frequency to prevent output signal attenuation. More importantly, the signal suffers fairly large phase shift around the pole frequency, and relatively small process variations can introduce large relative phase shift between two output signals when the pole frequency is close to the oscillation frequency. FIG. 7 is a plot of the pole frequency ω_Pole as a function of the load capacitance C_L at the output of the buffer stage for bipolar and MOS implementations at a 1-mA bias current. The MOS design has a lower pole frequency even with a relatively small load capacitance due to its lower g_m. This implies that, even though the MOS cross-coupled cell can provide a negative resistance up to very high frequencies, the smaller bandwidth of the buffer stage can limit the practical maximum attainable oscillation frequency.

3) Parasitic Capacitance and Tuning Range

Another factor that determines the maximum attainable oscillation frequency for a given technology and power budget are the parasitic capacitances of the various components. The maximum oscillation frequency of the circuit in FIG. 1 is 1/√{square root over (L(C_Fix+C_Eq))}. When a desired tuning range Δω is required, the maximum attainable center frequency can be described as $\begin{array}{cc}{\omega }_{\mathrm{Max}}=\frac{1}{\left(1+\frac{\mathrm{Tune}}{200}\right)\sqrt{L_{\mathrm{Min}}\left(C_{\mathrm{Fix}}+C_{\mathrm{Eq}}\right)}}& \left(12\right)\end{array}$ where Tune is the tuning range as a percentage of the center frequency, L_Min, is the smallest feasible inductance without suffering severe process variations, C_Ex is the fixed sum of parasitic capacitances contributed by the varactor, the inductor, and the buffer, and C_Eq is the effective shunt capacitance of the negative resistance cell. The effective capacitance of the cross-coupled cell is ˜C_π/2. At high frequencies, this along with the effective capacitance from the buffer stage may become a significant portion of the overall capacitance and limit the maximum attainable oscillation frequency and tuning range.

This subsection showed the mechanisms that degrade the R_Eq generated by the cross-coupled cell and showed how the effective capacitance from the buffer and negative resistance cell limits the maximum attainable frequency and tuning range. These limitations have motivated a new negative resistance cell, described in the next subsection, that has a higher negative to positive transition frequency and lower effective capacitance, thereby enabling low-power low-noise high-frequency design. While the embodiments are technology-independent, certain benefits are realized in BiCMOS embodiments, and hence the following sections will focus on a BiCMOS design.

B. Novel Negative Resistance Cell Design

As seen in the previous section, a capacitive emitter degenerated transistor can generate a negative resistance. FIG. 8 shows a single-ended negative resistance cell using capacitive emitter degeneration. The R_Eq and C_Eq can be described using the formulas in (8) and (9). When a voltage is applied to the base, part of it appears across C_π, which in turn generates the transconductor current. Part of this transconductor current is returned to the signal source itself via the capacitor-capacitor divider. A portion of this returning current has a 180 phase shift from the applied voltage and this results in a negative resistance. This negative resistance cell has a very small effective capacitance. First, C_π and C_e are in series. Second, the g_m cell affects the charge buildup across each capacitor and increases the effective C_π while decreasing the effective C_e, thus further reducing the effective series capacitance. This cell also has a high R_Eq transition frequency. The small effective capacitance has a higher impedance than C_π, resulting in a smaller effective r_g. This causes the voltage drop across r_g and the phase shift from the base voltage to the voltage across C_π to be smaller than in the cross-coupled cell. So, it retards the degradation mechanism and increases the transition frequency. However, emitter degeneration decreases the effective transconductance. Because the R_Eq transition frequency is also a function of g_m, the reduced effective transconductance limits the improvement in the R_Eq transition frequency and increases the |R_Eq| value. The increased |R_Eq| typically requires a higher Q tank design and hence higher Q inductor design which is nontrivial at high frequencies.

A novel capacitive emitter-degenerated negative resistance cell that mitigates the reduction in issue mentioned above will now be discussed. FIG. 9 illustrates a novel negative resistance cell 900. In some embodiments, two capacitive emitter-degenerated negative resistance cells Q1 and Q2 are interconnected by using a cross-coupled NMOS pair M1 and M2. The gate and drain of each NMOS device is connected to the emitters of each negative resistance cell, respectively. The cross-coupled NMOS pair M1 and M2 works both as emitter-degenerating capacitors and provides additional transconductance to improve the negative resistance value. FIG. 10 shows the equivalent small-signal circuit model for the novel negative resistance cell. The input admittance can be calculated as $\begin{array}{cc}{Y}_{\mathrm{IN}}=\frac{\frac{1}{2}\left[{ℊ}_{m2}\left(\frac{r_{ℊ}}{Z_{ℊ}}-1\right)+\frac{1}{Z_{ℊ}}\right]}{\left[1+{ℊ}_{m1}{Z}_{\pi }^{\prime }\right]+Z_{\pi }\left[{ℊ}_{m2}\left(\frac{r_{ℊ}}{Z_{ℊ}}-1\right)+\frac{1}{Z_{ℊ}}\right]}& \left(13\right)\end{array}$ where Z_π′=(r_π∥1/sC_π), Z_π=r_b+Z_π′, Z_g=r_g+1/sC_gs, and g_m1 and g_m2 are transconductances of the BJT and the nMOS transistor, respectively. If r_b and r_g are ignored, the equivalent shunt resistance is given by $\begin{array}{cc}{R}_{\mathrm{Eq}}=\frac{-2\left[{\left(\frac{1}{r_{\pi }}+\Delta ℊ\right)}^2+{\left(\omega C_T\right)}^2\right]}{\left(\frac{1}{r_{\pi }}+\Delta ℊ\right)\left(\frac{{ℊ}_{m2}}{r_{\pi }}+{\omega }^2{C}_{\mathrm{gs}}{C}_{\pi }\right)-{\omega }^2{C}_T\left(\frac{C_{\mathrm{gs}}}{r_{\pi }}-C_{\pi }{ℊ}_{m2}\right)}& \left(14\right)\end{array}$ where Δg_m=g_m1−g_m2 and C_T=C_π−C_gs. For a fixed bias current, the g_m of the BJT is to first-order insensitive to device geometry, but the g_m of MOS device increases as the square root of the device size. To find an optimum g_m1/g_m2 ratio, let g_m1=δg_m2, and g_m2=K√{square root over (C_gs)}, where K is a constant. Using this relationship and assuming that g_m1r_π>>1, then equation (14) can be simplified to: $\begin{array}{cc}{R}_{\mathrm{Eq}}=\frac{-\frac{2}{\delta }\left[{\left(1-\delta \right)}^2+{\left(\frac{\omega }{{\omega }_T}\right)}^2\left(1+\frac{{\Gamma }^2}{C_{\pi }}\right)\right]}{\left(1-\delta \right){ℊ}_{m1}\left(\frac{1}{\beta }+\frac{{\omega }^2\Gamma }{{\omega }_{T}K}\right)-{\omega }^2\left(\frac{\Gamma }{\beta K}-\frac{1}{{\omega }_T}\right)\left(C_{\pi }+{\Gamma }^2\right)}& \left(15\right)\end{array}$ where ω_T=g_m1/C_π and Γ=Δg_m1/K

FIG. 11 is a plot of the expression in equation (15) as a function of δ for different values of g_m1. This shows that the R_Eq is optimized when δ is near unity, i.e., g_m1≈g_m2. Additionally, it shows that this ratio is more critical than the magnitude of g_m1 itself. For example, a 15-mA/V-15-mA/V combination results in a better R_Eq than a 30-mA/V-15-mA/V combination.

FIGS. 12 and 13 show the simulated R_Eq and C_Eq results for the cross-coupled cell, the simple capacitively degenerated cell, and the novel cell 900, respectively. All designs use a 2-mA bias current and use the same BJT size. As shown in FIGS. 12 and 13, the simple capacitive degeneration cell shows a higher R_Eq transition frequency but a larger |R_Eq| in comparison to the cross-coupled cell. The novel cell 900 also has a higher transition frequency in comparison to the cross-coupled cell, but it shows a better R_Eq in comparison to the simple capacitively degenerated cell. This implies that the novel cell 900 may be particularly useful for low-power low-noise design for frequencies above the transition frequency of the cross-coupled cell. This is because it does not generally require an increased bias current for a proportional increased g_m, which would also increase the noise from the transistor. FIG. 13 shows that the novel cell 900 has a slightly higher C_Eq in comparison with the simple capacitively degenerated cell between 2040 GHz, but this value is much smaller than the value of C_Eq of the cross-coupled cell. Additionally, in some embodiments the novel cell 900 shows an inductive impedance at low frequencies as shown in FIG. 13. This simulated inductance using an active device and capacitor has a lower Q in comparison with a passive inductor and, due to its large inductance value, it has minimal effect on the oscillator operation even if the tank is tuned within that frequency range. However, it shows that it is possible to build a parasitic capacitance free negative resistance cell.

The analysis results in FIG. 11 suggest that a BJT-BJT combination instead of a BJT-MOS combination may be preferred for better g_m matching for the novel cell. However, even though a BJT-BJT combination may result in a better R_Eq, the relatively high r_b of the BJT typically results in a low transition frequency, and its benefit reduces to the small effective capacitance only.

C. Common-Mode and Differential-Mode Oscillation

One distinct difference between the capacitively degenerated cell and the cross-coupled cell is its common-mode behavior. The common-mode input admittance for the ideal cross-coupled cell in FIG. 2 is near zero (Y_in≈0). FIG. 14 shows the common-mode equivalent circuit schematic for the capacitively degenerated cell. Unlike the cross-coupled cell, each half circuit of the capacitively emitter degenerated cell provides negative resistance. However, for common-mode signals, the emitter degeneration capacitor connected between two emitters in series (C_S) does not have any effect on the common-mode impedance. Only the capacitors connected to the ground act as a degeneration capacitor. Therefore, when C_S=0, each half of the circuit has the same effective resistance and capacitance as in the differential mode, i.e., R_EqD=R_EqC and C_EqD=C_EqC. In this case, the differential- and common-mode admittances can be described as $\begin{array}{cc}{R}_{\mathrm{EqH}}=R_{\mathrm{EqC}}=R_{\mathrm{EqD}}{C}_{\mathrm{EqH}}=C_{\mathrm{EqC}}=C_{\mathrm{EqD}}{Y}_{\mathrm{IN},C}=\frac{2}{R_{\mathrm{EqH}}}+\mathrm{j\omega 2}{C}_{\mathrm{EqH}}{Y}_{\mathrm{IN},D}=\frac{1}{2R_{\mathrm{EqH}}}+\mathrm{j\omega }\frac{C_{\mathrm{EqH}}}{2}.& \left(16\right)\end{array}$ The equations predict that the common-mode |R_Eq| is four times smaller than the differential-mode |R_Eq|, and common-mode C_Eq is four times larger than the differential-mode C_Eq. This implies that the capacitive emitter degeneration cell is more prone to oscillate in common-mode when C_S=0.

FIG. 15 shows the simulated common-mode and differential-mode R_Eq for a capacitively emitter-degenerated cell where C_S=0. As seen in FIG. 15, the common mode shows a much smaller |R_Eq|. When this type of negative resistance cell is used, it is desirable to design the tank bias network to prevent common-mode oscillation. FIG. 16 shows the LC tank with a center tapped inductor and capacitor including the bias network. If Z_biasL and Z_biasC are very small, the common-mode impedance to ground becomes (L/2∥2C), and the circuit can now oscillate at ω=1/√{square root over (L(C+C_EqH))} in the common mode. In fact, when Z_biasL and Z_biasC are zero, each half circuit becomes an independent oscillator, and there is no phase relationship constraint between two output signals. If Z_biasL and Z_biasC are very large, the common-mode impedance of the tank becomes very large, and the circuit cannot oscillate in the common mode. If the bias network impedance is zero, the circuit prefers to oscillate in the common mode. Thus, a large bias network impedance converts the oscillation mode from the common to differential mode. FIG. 17 shows the oscillation mode conversion from common mode to differential mode for the same circuit by simply altering the bias network impedance. The differential-mode signal is shifted down on this plot for graphical convenience only.

In the novel negative resistance cell with the cross-coupled MOS pair, the common-mode admittance of the MOS pair is near zero. Only the effective input capacitance of the buffer contributes to the common-mode negative resistance. This makes the novel cell less susceptible to common-mode oscillations as compared to a simple capacitively emitter-degenerated cell.

D. Wide Tuning Range

A wide tuning range is often important because it can accommodate more process and temperature variations. For high-frequency oscillator design, the effective capacitance from the negative resistance cell is one of the key factors that limit a wide tuning range. The novel capacitive emitter degenerating cell has a small effective capacitance. FIGS. 18A and 18B graphically show the mechanism that results in a small effective capacitance. In FIGS. 18A and 18B, Q3 and Q4 are buffer transistors. In the cross-coupled structure illustrated in FIG. 18A, the tank looks into the base of Q2, the collector of Q1, and the base of buffer transistor Q3. However, in the novel topology 1800 illustrated in FIG. 18B, the tank only looks into the base of Q1. Furthermore, the equivalent capacitance looking into the base of is much smaller than the C_π of Q1, as shown above.

FIG. 19 shows how the effective capacitance of a negative resistance cell affects the oscillator tuning range. For this simulation, a two-turn spiral inductor with 740-pH inductance with 17-fF parasitic capacitance and diode varactors with capacitance range from 28.6 to 68.4 fF are used. The tuning range and center frequency go down rapidly with increasing parasitic capacitance of the negative resistance cell. In particular, if the center frequency is kept constant by changing the varactor size, the tuning range reduces even more rapidly, as shown in FIG. 19. For example, if the load at the output port in FIG. 18 is 200 fF, the equivalent shunt capacitance looking into the base of Q3 is approximately 44.4 fF. This parasitic loading causes severe frequency and tuning range limitations for the cross-coupled topology, as can be seen in FIG. 19. However, in the novel topology disclosed herein, the equivalent shunt capacitance looking into the base of Q3 functions as part of the emitter-degenerating capacitance, and the effective parasitic capacitance loading the tank is further attenuated by Q1.

A small effective capacitance also provides more room to increase the inductor size in the tank. In many cases, the R_p of LC tank increases with increasing inductance value, so a large inductance enables large output signal power. Depending on the technology and the design constraint, the Q of the inductor can increase with increasing inductance. In this case, both the increased signal power and improved Q contributed by the small effective capacitance can result in lower phase noise, as can be seen in the modified Leeson's phase noise formula, described in J. W. M. Rogers, J. A. Macedo, and C. Plett, “The effect of varactor nonlinearity on the phase noise of completely integrated VCOs,” IEEE J. Solid-State Circuits, vol. 35, pp. 1360-1367, September 2000 and shown as follows: $\begin{array}{cc}L\left(\Delta f,K_{\mathrm{VCO}}\right)=10\log \left\{{\left(\frac{f_0}{2Q\Delta f}\right)}^2\left[\frac{\mathrm{FkT}}{2P_0}\left(1+\frac{f_C}{\Delta f}\right)\right]+\frac{1}{2}{\left(\frac{K_{\mathrm{VCO}}{\upsilon }_m}{2\Delta f}\right)}^2\right\}(1& \left(17\right)\end{array}$ where

• • L(Δf, K_VCO) phase noise in dBc/Hz;
  • f₀ frequency of oscillation in Hz;
  • Δf frequency offset from the carrier in Hz;
  • F noise figure of the transistor amplifier;
  • k Boltzmann's constant in J/K;
  • T temperature in K;
  • P₀ RF power produced by the oscillator in W;
  • f_C flicker noise corner frequency in Hz;
  • K_VCO gain of the VCO in Hz/V;
  • v_m total amplitude of all low-frequency noise sources in V/√{square root over (Hz)}. The first term within the log in equation (17) predicts a decreased phase noise with increasing tank and signal power. This discussion emphasizes that the small effective capacitance of the negative resistance cell is not only advantageous for high frequency and wide tuning design, but results in additional flexibility during the LC tank phase noise optimization process.

II. Experimental Results of a Particular Embodiment

In one embodiment, a 20-GHz VCO as described above with a 5-GHz tuning range has been designed using the IBM 0.25-m BiCMOS process. It is desirable to take into account the g_m1/g_m2 ratio for R_Eq optimization of various embodiments. The g_m1/g_m2 (δ) ratio in some embodiments is about 0.3. At 20 GHz, the simulated R_eq≈−500Ω and C_{EQ t}≈13 fF. This includes the effect of the buffer. It should be noted that C_Eq is about 1/9th the C_π of Q1, which is equal to 126 fF. In some embodiments, the VCO uses a two-stage emitter follower as buffers for each output. The capacitive impedance looking into this buffer works as a degeneration capacitance and contributes to the negative resistance. However, as described in the previous section, the degeneration using active devices is more desirable and the buffer has been designed to have minimal impact on this design. In some embodiments, two back-to-back junction diodes as described above are used as the varactor, and the anode is connected to the base of the BJT to minimize the N/substrate parasitic capacitance effect. The spiral inductor uses two turns to generate a 740-pH inductance. A single differential inductor is used for higher Q and to save area. This single inductor design without a center tap used in some embodiments also prevents common-mode oscillation. A chip microphotograph and VCO layout details according to an embodiment are shown in FIG. 20.

For the measurements, RF probes were used to directly connect to the bare die. A single-ended measurement setup has been used throughout. FIG. 21 shows the measured output power spectrum of the 20-GHz oscillation signal. The measured tuning range is compared with the simulated tuning range in FIG. 22(a). Measurement results show more than 5-GHz (25%) tuning range. This wide tuning was possible because of the low effective capacitance of the novel negative resistance cell. FIG. 22(b) shows simulated oscillation frequency at a fixed bias condition as a function of the temperature for different process corners. For these corner simulations, only the process corner parameter for bipolar devices has been considered, and six sigma variations have been considered. FIG. 22(b) shows that temperature and process variation results in about 4-GHz variation of the center frequency, clearly showing the desirability of a wide tuning range design that can tolerate temperature and process variations. The VCO core of some embodiments consumes only 2 mA, and each emitter follower branch drains 0.5 mA from a 4.5-V supply, respectively. This low bias current supports the low-power design capability of the novel topologies of the embodiments described above. Despite the wide tuning range, the maximum output power variation was less than 3.5 dBm over the whole frequency tuning range, as shown in FIG. 23.

A low-power signal close to the noise floor is injected at the opposite side of differential output to remove the random drifting of the free running VCO, as shown in FIG. 24A. The phase noise of the injected signal was 121 dBc/Hz at a 2-MHz offset from the 19.4-GHz carrier. At high injection levels, the phase noise of the VCO follows the phase noise of the injected signal source. However, at low injection power levels, the locking range reduces and the phase noise approaches its intrinsic level, as shown in FIG. 24B.

FIG. 25 shows the measured injection locking range as a function of injected signal power and the measured phase noise at an injected signal power of 58 dBm. At this injection level, the lock range is about 800 kHz. The actual power delivered to the tank is much smaller because of the attenuation through the buffer stage. The phase noise is measured at a 2-MHz offset from 19.4 GHz to eliminate the phase-noise attenuation through injection locking. The measured phase noise was 105.5 dBc/Hz. This value is obtained using an NMOS noise coefficient (γ) of ⅔ and no induced gate noise contribution. For short-channel devices, γ may reach 2.5, and induced gate noise should be included, as simulations underestimate the actual phase noise. It should be noted that the results detailed above are for a particular embodiment, and that other embodiments may exhibit different results.

III. CONCLUSION

In the previous sections, factors affecting the design of a negative resistance cell based LC VCOs have been discussed. The analysis included parasitics from the VCO core and the buffer stage. This discussion also analyzed the high-frequency performance and limitations of the capacitively degenerated negative resistance cell. Based on these analyses, a novel negative resistance cell topology is described that can overcome the limitations of the existing topologies. In some embodiments, the novel cell uses a cross-coupled MOS pair as a degeneration cell. The cross-coupled MOS pair contributes additional conductance and allows for the novel cell to have a higher maximum attainable oscillation frequency and better negative resistance characteristics in comparison with other topologies at high frequencies. These properties combined with its small effective capacitance enables low-power low-noise high-frequency VCO implementations. One embodiment includes a design for a 20-GHz fully integrated LC VCO implementation in the IBM SiGe 0.25-m BiCMOS technology.

Various embodiments of the invention have been described. The description of the exemplary embodiments of the invention is presented for the purposes of illustration and description, and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

As an example, the invention further contemplates a method for generating signals using a VCO as described herein, and well as methods for manufacture of the disclosed VCO. In addition, the VCO design described herein may be useful in a number of different applications, including wired and wireless communication systems. For example, a VCO as described herein may be implemented within a phase-locked loop (PLL) of a communication device.

The terminology used in this application is meant to include all of these environments. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. Therefore, it is manifestly intended that the inventive subject matter be limited only by the following claims and equivalents thereof.

The Abstract is provided to comply with 37 C.F.R. § 1.72(b) to allow the reader to quickly ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to limit the scope of the claims.

Claims

1. A voltage controlled oscillator (VCO) comprising: an inductor-capacitor (LC) tank; and a negative resistance cell coupled to the LC tank, wherein the negative resistance cell includes: a first bipolar transistor, a second bipolar transistor, and at least two field-effect transistors, wherein the first and second bipolar transistors are interconnected via the field-effect transistors.

2. The VCO of claim 1, wherein an emitter of the first bipolar transistor is coupled to a gate of a first one of the field-effect transistors and an emitter of the second bipolar transistor is coupled to a gate of a second one of the field-effect transistors.

3. The VCO of claim 2, wherein the emitter of the first bipolar transistor is coupled to a drain of the second one of the field-effect: transistors and the emitter of the second bipolar transistor is coupled to a drain of a first one of the field-effect transistors.

4. The VCO of claim 3, wherein the negative resistance cell further comprises a current source that is coupled to a source of each of the field-effect transistors.

5. The VCO of claim 1, wherein the LC tank is coupled to a base of the first bipolar transistor and a base of the second bipolar transistor.

6. The VCO of claim 1, further comprising a buffer circuit for buffering an output of the VCO.

7. The VCO of claim 6, wherein the buffer circuit comprises: a first buffer coupled to the emitter of the first bipolar transistor, and a second buffer coupled to the emitter of the second bipolar transistor.

8. The VCO of claim 7, wherein the first and second buffer comprise emitter-followers.

9. The VCO of claim. 1, wherein the field-effect transistors comprise metal-oxide-semiconductor field-effect transistors (MOSFETs).

10. The VCO of claim 1, wherein the field-effect transistors include NMOS devices.

11. A voltage controlled oscillator (VCO) comprising: a first pair of transistors; a second pair of transistors, wherein the transistors of the first pair are interconnected by cross-coupling the second pair of transistors; and an inductor-capacitor (LC) tank coupled to the first pair of transistors.

12. The VCO of claim 11, wherein the first and second transistors comprise one of bipolar transistors, field-effect transistors, or a combination of bipolar and field-effect transistors.

13. The VCO of claim 11, further comprising a current source coupled to the second pair of transistors.

14. The VCO of claim 11, wherein the VCO has a maximum operating frequency of at least 20 GHz.