Patent Application
20090102568
This invention relates generally to voltage controlled oscillators (VCOs), and more particularly, to a VCO having cascaded emitter follower buffer stages.
VCOs typically have to operate in narrow frequency bands. For example, in some Industrial, Scientific and Medical (ISM) applications VCOs may have to operate in a 120 MHz frequency window. VCOs are typically phase locked to an input signal using a phase locked loop (PLL) that includes a feedback to control the output frequency of the VCO. The PLL maintains the VCO in the narrow frequency band.
VCOs are used in many different applications. For example, VCOs are used in transmitters to control the operating frequency of the transmitters. In high frequency applications, for example, when using a 24 GHz VCO, such as, used in automotive or other short range radars, isolation between the VCO and the other portions of the transmitter is an issue. When proper isolation is not provided, the frequency of the VCO is changed, often referred to as frequency pulling, as a result of varying load conditions. The varying load conditions may be caused, for example, by a change in environmental conditions, such as from varying reflections from a changing environment near the antenna, or by other circuits connected to the VCO changing the operating mode or state. For example, the turning on/off of the switches in a pulsed radar transmitter may vary the load impedance presented to the VCO. These changes in load-impedance (and hence frequency) can occur within nanoseconds at a rate that the PLL cannot correct. The operating frequency of the VCO will thus be affected and that may cause the VCO to operate outside of a desired or required frequency band, as well as having other affects on circuit performance, which may be less detectable.
It is known to provide isolation for a VCO in a transmitter application using a cascode output configuration or using buffer stages. For example, a plurality of buffer stages may be added in a serial arrangement to provide isolation of the VCO. These buffer stages provided in a serial arrangement increase the amount of current needed due to each stage requiring a bias current. As a result of the increased current, direct current (DC) consumption is increased, thereby increasing the amount of DC power needed. The increased current also results in an increase in temperature of the VCO, which in applications that present harsh thermal environments may result in unacceptable operation of the VCO (e.g., VCO operating outside of required frequency band). Thus, although isolation of VCOs may be provided using these known methods, the overall operation of the system may be adversely affected.
In accordance with an exemplary embodiment, an output buffer for a voltage controlled oscillator (VCO) is provided. The output buffer includes a first buffer stage including a first transistor and a second buffer stage including a second transistor. The first and second transistors are connected in a cascaded emitter follower buffer arrangement.
In accordance with another exemplary embodiment, a voltage controlled oscillator is provided that includes an output buffer and a pull-down resistor network configured to generate an internal bias voltage operable to initiate oscillation in the absence of a signal from a charge pump of phase locked loop.
In accordance with yet another exemplary embodiment, a method for controlling a voltage controlled oscillator (VCO) is provided. The method includes configuring a first stage of an output buffer for the VCO in a cascaded configuration with a second stage of the output buffer. The method further includes isolating an output of the VCO using the first and second stages of the buffer.
For simplicity and ease of explanation, the invention will be described herein in connection with various embodiments thereof. Those skilled in the art will recognize, however, that the features and advantages of the various embodiments may be implemented in a variety of configurations. It is to be understood, therefore, that the embodiments described herein are presented by way of illustration, not of limitation.
As used herein, an element or step recited in the singular and proceeded with the word “a” or “an” should be understood as not excluding plural said elements or steps, unless such exclusion is explicitly stated. Furthermore, references to “one embodiment” of the present invention are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Moreover, unless explicitly stated to the contrary, embodiments “comprising” or “having” an element or a plurality of elements having a particular property may include additional such elements not having that property. Additionally, the arrangement and configuration of the various components described herein may be modified or change, for example, replacing certain components with other components or changing the order or relative positions of the components.
Various embodiments of the present invention provide a voltage controlled oscillator (VCO) having a cascaded emitter follower buffer configuration. The VCO also includes a resistor network (shown in
In various embodiments, a VCO 20 is provided that may form part of a phase locked loop (PLL) 22 as shown in
It should be noted that although the VCO 20 is described in connection with the PLL 22 shown in
In operation, the phase of the VCO 20 at an output 32 is locked using the PLL 22 and based on an input signal, for example, an input frequency signal (Fref) received at the PFD 26. The PLL 22 is essentially an electronic control system that generates a signal that is locked to the phase of the input or reference signal. The PLL 22 responds to both the frequency and the phase of the input signal and automatically increases or decreases the frequency of the VCO 20 until the output frequency of the VCO 20 is matched to the reference signal (times a divider ratio) in both frequency and phase (which may include an acceptable deviation). It should be noted that the VCO 20 generates a periodic output signal and the charge pump 24 sends a control signal to the VCO 20 based on feedback from the loop 30. For example, if initially the VCO 20 is at about the same frequency as the reference signal (times the divider ratio), then if the phase from the VCO 20 falls behind, the control voltage of the charge pump 24 is changed based on the change in frequency as detected by the PFD 26. The frequency of the VCO 20 is accordingly increased (e.g., oscillation speeds up). If the phase moves ahead, the control voltage is again changed, but to decrease the frequency of the VCO 20 (e.g., oscillation slows down).
The VCO 20 includes a plurality of transistors 40a and 40b provided in a cascaded configuration that defines a combined buffer stage 42 as shown in
The transistors 40a and 40b may be, for example, bipolar junction transistors (BJTs) provided in an NPN configuration. In this configuration, a base 44 of the first transistor 40a is connected to the output of the VCO core 21 through a capacitor 25 and a collector 46 of the first transistor 40a is connected to power (e.g., 5 volt also designated and commonly referred to as Vcc). An emitter 48 of the first transistor 40a is connected to a collector 50 of the second transistor 40b. A base 52 of the second transistor 40b is connected to the collector 50 of the second transistor 40b. An emitter 54 of the second transistor 40b is connected to ground through a current source 56. An output is provided at the emitter 54 of the second transistor 40b. Accordingly, in the illustrated embodiments, the transistors 40a and 40b are provided in a common emitter/source follower arrangement that isolates the VCO core 21 from the output. Thus, both stages of the combined buffer stage 42, namely the transistors 40a and 40b share the same current. Also, the buffer stages are AC coupled to the VCO core 21. In a conventional emitter follower arrangement, the reverse isolation is determined by the intrinsic base/emitter junction capacitance of the transistor(s). In the cascaded configuration of the various embodiments, the reverse isolation is determined by the series combination of two intrinsic base/emitter junction capacitances. Accordingly, this arrangement reduces the capacitance by half and thus doubles the reverse isolation if transistors 40a and 40b are of the same size. The output voltage swing in this cascaded configuration is the same as that in the conventional emitter follower such that the loss through the buffer stage is minimized. At the same time, the two transistors 40a and 40b use a common bias current. Therefore, this arrangement consumes the same DC power as the conventional emitter follower while providing improved reverse isolation.
In various embodiments, the VCO core 21 includes a varactor bias network 60 as shown in
It should be noted that the voltage applied to the varactor-diode 64 is variable. In various embodiments, the voltage applied to the varactor-diode 64 is counter proportional to changes in temperature as described in more detail below.
In operation, the resistor network 66 of the varactor bias network 60 (which forms part of the VCO core 21 shown in
Various embodiments of the invention also provide a temperature bias circuit 80 as shown in
In operation, as temperature increases, the junction capacitance of the transistor 86 and the varactor-diode 64 increases as a result of the build-in potential (φ) of the pn junction in these devices decreasing and as defined in the following equation:
Where C is the junction capacitance, Na and Nd are the doping concentrations of the p-type and n-type semiconductor, φ is the build-in potential across the p and n regions, Vreverse-bias is the reverse bias applied on the p-n junction, εs is the surface potential and q is the electron charge.
In order to compensate for this effect, the CTAT bias circuit 80 is used to bias a base 90 of the transistor 86 and an anode 91 of the varactor-diode 64. The compensation is counter proportional to temperature. For example, as temperature increases the CTAT voltage decreases as based on predetermined values (e.g., values based on empirical analysis and/or circuit simulations). Thus, the bias voltages of the transistor 86 and varactor-diode 64 are adjusted to minimize the change in junction capacitance, which determines the frequency shift over temperature.
Thus, a VCO 20 is provided as shown in
It should be noted that modifications and variations to the various embodiments are contemplated. For example, the number, relative positioning and operating parameters of the various components may be modified based on the particular application, use, etc. The modification may be based on, for example, different desired or required operating characteristics.
Accordingly, it is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with each other. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Dimensions, types of materials, orientations of the various components, and the number and positions of the various components described herein are intended to define parameters of certain embodiments, and are by no means limiting and are merely exemplary embodiments. Many other embodiments and modifications within the spirit and scope of the claims will be apparent to those of skill in the art upon reviewing the above description.
The scope of the various embodiments of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. Further, the limitations of the following claims are not written in means-plus-function format and are not intended to be interpreted based on 35 U.S.C. §112, sixth paragraph, unless and until such claim limitations expressly use the phrase “means for” followed by a statement of function void of further structure.
