Patent Application
20090167389
This invention relates to a voltage-controlled oscillator (VCO).
A voltage-controlled oscillator (or VCO) is an electronic oscillator which is designed to be controlled in oscillation frequency by a voltage input. The output oscillation frequency is varied by the application of a DC input voltage.
One application of the VCO is as a local oscillator in radio-frequency (RF) applications to produce an adjustable-carrier or heterodyning frequency. The local oscillator has an adjustable frequency that enables a transceiver to communicate over a chosen channel. The transceiver usually includes a phase-locked loop to ensure that the phase of the VCO is kept aligned with the phase of a reference frequency.
The invention comprises a calibration circuit for a voltage-controlled oscillator. The calibration circuit comprises a first counter for counting the number of cycles of a reference signal and a second counter for counting the number of cycles of a feedback signal produced by the voltage-controlled oscillator. The second counter is adapted to produce a difference value representative of the difference between the frequency of the reference signal and the frequency of the feedback signal. A memory comprising a plurality of memory locations stores a plurality of the difference values and associated capacitor selections. The associated capacitor selections are used to select capacitors in a capacitor bank in which the capacitor bank is connected to an input of the voltage-controlled oscillator. The presence of the memory locations with associated capacitor selections allows the fast and efficient control of the voltage-controlled oscillator since on initialization the values of the capacitor selections are stored in the memory locations.
In one aspect of the invention, a sweeper is used for selecting possible values of the capacitor selections and thus sweeping through possible combinations during the initialization of the voltage controlled oscillator.
The invention also includes a method for the calibration of a voltage-controlled oscillator which comprises the selecting of a capacitor selection in a capacitance bank connected to an input of the voltage-controlled oscillator, measuring the difference frequency between a frequency of a reference signal and a frequency of a feedback signal produced by the voltage-controlled oscillator and then storing a value representative of the difference frequency in a memory together with the capacitor selection.
This method is repeated with a new capacitor selection and then measuring a changed difference frequency and storing a further value representative of the changed difference frequency in the memory together with the new capacitor selection. The method is repeated until all of the possible capacitor selections have been selected.
The method is used in a phase-locked loop for aligning an output phase of a voltage-controlled oscillator with the input phase of the voltage-controlled oscillator. The phase-locked loop (or PLL) has a phase/frequency detector for detecting changes in the output phase of the voltage-controlled oscillator compared with the input phase of the voltage-controlled oscillator and the selectable capacitor bank attached to an input of the voltage-controlled oscillator. A look-up table is used for storing a plurality of values representative of the difference between the output phase of the voltage-controlled oscillator and the input phase of the voltage-controlled oscillator and for storing a plurality of values of capacitor selections adapted to select capacitors in the selectable capacitor bank.
In one aspect of the invention, the phase-locked loop has a frequency detector with input integer values and fractional values from a sigma-delta divider.
Finally, the invention includes a method of adjusting the frequency of a voltage controlled oscillator in which a difference value is measured between the output phase of the voltage-controlled oscillator and the input phase of the voltage-controlled oscillator. The difference value is used to look up in a memory a capacitor selection and the capacitor selection used to change a capacitance value at a capacitor bank attached to an input of the voltage-controlled oscillator.
The first VCO 10a, the second VCO 10b and the third VCO 10c are connected to a calibration machine 20 which function will be described later and to an integrator 30. The calibration machine 20 has as reference input a reference signal Fclk at 50 and a feedback signal Fin from a multiplexer 40. The multiplexer 40 has as its inputs the feedback signals from the first VCO 10a, the second VCO 10b and the third VCO 10c (divided by 8 as will be described later) and selects one of the feedback signals for passage to the calibration machine 20 and a sigma delta divider 70.
The phase-locked loop also includes the sigma delta (fractional) divider 70 having as inputs values SD and M and the feedback signal Fin from the multiplexer 40 at a multiplexer output 60. The output of the sigma delta divider 70 is passed to a phase frequency detector 80 and thence to a charge pump 90. The output of the charge pump 90 is passed to the integrator 30 where it control the output frequencies of the first VCO 10a, the second VCO 10b or the third VCO 10c.
The output of the first VCO 10a is passed to a first frequency divider 100a which produces at its output a signal with a frequency in the (IEEE) LBAND and to a second frequency divider 100b. and is also passed to a third frequency divider 100c. The output of the second frequency divider 100b has an output frequency in the UHF band The output of the third frequency divider 110c is passed to the multiplexer 40 and is also passed to a fourth frequency divider 100d. The fourth frequency divider 100d has an output frequency in the VHF band.
Similarly the output of the second VCO 10b is passed to a fifth frequency divider 110a which produces at its output a signal with a frequency in the (IEEE) LBAND and to a sixth frequency divider 110b. The output of the sixth frequency divider 110b has an output frequency in the UHF band and is also passed to a seventh frequency divider 110c. The output of the seventh frequency divider 110c is passed to the multiplexer 40 and is also passed to an eighth frequency divider 110d. The eighth frequency divider 110d has an output frequency in the VHF band.
Finally the output of the third VCO 10c is passed to a ninth frequency divider 120a from which the output of the ninth frequency divider 120a is passed to a tenth frequency divider 120b. The tenth frequency divider 120b produces an output signal with a frequency in the UHF band. The output of the tenth frequency divider 120b is also passed to an eleventh frequency divider 120c which passes its output to the multiplexer 40.
The calibration of one or all of the VCOs 10a-10c will now be described with respect to
The calibration is carried out on initialization of the circuit by initially sweeping through all the possible values of input capacitors at each of the VCOs 10a-10c to which the sweeper 230 is connected. The selection of the possible input capacitors is carried out one at a time by using the sweeper 230 and storing the value OUTVAL for each of the different selection of the possible input capacitors in the memory 240. This calibration procedure is done as follows.
In a first step, an initial selection of the possible input capacitors is made. The capacitors attached to the inputs of the VCOs 10a-10c are arranged as a bank of capacitors which can be selected by a binary number. In the example the binary number is a six bit number. However, this is not limiting of the invention.
In a second step, the second counter 210 measures the number of cycles of the feedback frequency Fin within a fixed time period. The fixed time period is calculated by counting a fixed number of cycles of the reference signal. Since the period of the reference signal is known, the fixed time period is determined as the product of the fixed number of cycles multiplied by the period of the reference signal. On reaching the fixed number of cycles a signal STOP_CNT is sent to the second counter 210 to stop the counting of the number of cycles of the feedback signal Fin. The value OUTVAL stored in the memory is the number of clock cycles of the feedback frequence Fin counted during a fixed number of the reference cycles derived from the reference signal Fclk.
As described above, the selection of the capacitors is done in one aspect of the invention using a six bit binary number. The same six bit binary number can also be used to address the memory at which the value OUTVALUE is stored
The value OUTVAL for this selection of capacitors (given from the sweeper 230) is stored in the memory 240 in the third step at the address indicated by the selection of the capacitors. The value OUTVAL can subsequently be recovered by selecting the memory address at which it is stored. Alternatively, the memory 240 is able accept as an input a request value and then return the memory address of the memory location which has the value OUTVAL closest to the request value. The memory 240 together with associated logic is then in a position to choose the value of the capacitance that needs to be applied to the input of the one of the VCOs 10a-10c used in order to adjust the output frequency of the VCO 10a-10c (which is eight times the frequency of the feedback signal Fin because of the frequency dividers 100a-100c; 110a-110c and 120a-120c). The value of the capacitance is selected by outputting the address of the location in the memory 240 at output 250 which is then transmitted to the capacitor bank situated at the input of the VCOs 10a-10c.
The operation of a selection circuit 260 will now be described. The selection circuit 260 comprises a change detector 270 which takes at its input 275 the values M and SD from the delta sigma divider 70. The change detector 270 detects a change in the values of SD and M and initiates a memory search 280. The change detector 270 calculates from the values of SD and M a difference value which is representative of the difference between the frequency of the feedback signal Fin counted during a fixed number of Fclk cycles (i.e. a value similar to the value OUTVAL from the calibration system 200). The memory search 280 passes the difference value as a request value to the memory 240. As discussed above, the memory 240 finds the closest value stored to the difference value. From the address of the memory location of the closest value store, associated logic is able to change the values of the capacitance at the input of the VCOs 10a-10c by switching the capacitor banks (as described above) and outputs on a second output 245 the closest value stored in the memory location (and now corresponding to the new capacitance at the inputs of the VCOs 10a-10c).
The values of SD and M give origin to a difference value that is then passed to a comparator 290 where the difference value are compared with the closest value received from the second output 245 of the memory. In block 295 a check is made to see whether the difference value from SD and M is the closest to the one received from the memory 240. If this is the case then no further search of the memory 240 is required. If, however, this is not the case, then a further search of the memory is initiated in the memory search 280 to determine a better closest value. This step is repeated until the closest values have been determined.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant arts that various changes in form and detail can be made therein without departing from the scope of the invention. For example, in addition to using hardware (e.g., within or coupled to a Central Processing Unit (“CPU”), microprocessor, microcontroller, digital signal processor, processor core, System on Chip (“SOC”), or any other device), implementations may also be embodied in software (e.g., computer readable code, program code and/or instructions disposed in any form, such as source, object or machine language) disposed, for example, in a computer usable (e.g., readable) medium configured to store the software. Such software can enable, for example, the function, fabrication, modeling, simulation, description and/or testing of the apparatus and methods described herein. For example, this can be accomplished through the use of general programming languages (e.g., C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, SystemC Register Transfer Level (RTL), and so on, or other available programs. Such software can be disposed in any known computer usable medium such as semiconductor, magnetic disk, optical disk (e.g., CD-ROM, DVD-ROM, etc.). Embodiments of the present invention may include methods of providing an apparatus described herein by providing software describing the apparatus and subsequently transmitting the software as a computer data signal over a communication network including the Internet and intranets.
It is understood that the apparatus and method embodiments described herein may be included in a semiconductor intellectual property core, (e.g., embodied in HDL) and transformed to hardware in the production of integrated circuits. Additionally, the apparatus and method embodiments described herein may be embodied as a combination of hardware and software. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalence. Furthermore, it should be appreciated that the detailed description of the present invention provided herein, and not the summary and abstract sections, is intended to be used to interpret the claims. The summary and abstract sections may set forth one or more but not all exemplary embodiments of the present invention.
