Patent Application
20250105735
Many types of voltage regulators are available. One type is a switching regulator in which the duty cycle of one or more switching transistors is controlled based on a feedback signal to regulator the output voltage of the regulator. One type of switching regulator is a boost converter which produces a regulated output voltage that is larger than its input voltage.
In one example, a circuit includes a comparator circuit having a first input, a second input, a first output and a second output. The circuit also includes the first input configured to receive an input voltage of a power supply circuit and the second input configured to receive an output voltage of the power supply circuit. Additionally, the circuit includes the first output to provide the larger of the input voltage or the output voltage and the second output to provide a logic low signal responsive to the input voltage being less than the output voltage, and to provide a logic high signal responsive to the input voltage being greater than or equal to the output voltage.
In an example, a circuit includes an inductor having a first terminal and a second terminal and a transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal coupled to the second terminal of the inductor. The circuit also includes a driver circuit having a first input, a second input, and an output, the output coupled to the control terminal of the transistor. Additionally, the circuit includes a comparator circuit having a first input, a second input, a first output, and a second output, the first input coupled to the first terminal of the inductor, the second input coupled to the second current terminal of the transistor, the first output coupled to the first input of the driver circuit, and the second output coupled to the second input of the driver circuit.
In an example, a circuit includes an inductor having a first terminal and a second terminal and a transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal coupled to the second terminal of the inductor. The circuit also includes a driver circuit having a first input, a second input, and an output, the output coupled to the control terminal of the transistor. The driver circuit includes a logic gate having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to the first input of the driver circuit and the second input terminal coupled to the input of the driver circuit and a switch having a current terminal and a control terminal, the control terminal coupled to the output terminal of the logic gate and the current terminal coupled to the output of the driver circuit.
A boost converter converts an input voltage to a higher output voltage. For some applications of a boost converter, the input power source to the boost converter has a relatively small input current limit. For example, some peripheral devices (e.g., barcode readers, cameras, etc.) receive their operating power from a universal serial bus (USB) Type-C cable. USB Type-C are capable of only relatively low power delivery to the peripheral device (e.g., 5V at 500 milliamperes (mA). For such limited input current power sources, it would be advantageous to control the average input current to make efficient use of the input current. Boost converters, whose control regulation circuits regulate the peak or valley input current, may not make efficient use of the full, yet limited, input current capability of the power source. The boost converter described herein has a control circuit that controls the average (DC) input current. The described boost converter also provides control for start-up or output short-circuit conditions.
The boost converter 100 of
The boost converter 100 further includes an ISO FET control circuit 120, an average current control circuit 130, a transconductance amplifier 102, a voltage-to-current (V2I) converter 104, and a PWM circuit 106. The ISO_FET control circuit 120 turns on the ISO_FET during normal operation, during which the ISO_FET operates in the linear region. Because the ISO_FET operates in the linear region, the ISO_FET represents a resistance between VP and SW, and thus functions as a sense resistor to produce a voltage between its drain and source that is proportional to IL. The average current control circuit 130 produces a current (IAVG_SNS) that is proportional to the average of IL and uses IAV_SNS to control the compensation (COMP) signal to the PWM circuit 106 to thereby control the duty cycle of M1. If the average level of IL increases, the average current control circuit 130 responds by decreasing the duty cycle of the PWM circuit 106 to cause the average level of IL to decrease. If the average level of IL decreases, the average current control circuit 130 responds by increasing the duty cycle of the PWM circuit 106 to cause the average level of IL to increase. The operation of the ISO FET control circuit 120 and the average current control circuit 130 is further explained below.
Resistors R1 and R2 are coupled in series between VOUT and ground and produce a scaled-down version of VOUT on feedback node FB) to a negative input of the transconductance amplifier 102. The positive input of the transconductance amplifier is coupled to a reference voltage VREF. The output of the transconductance amplifier is the compensation signal COMP, which is converted to a current by V2I 104. The current from V2I 104 flows into a resistor Rs, which converts the current to a voltage and which is coupled to the positive input of the PWM circuit 106. The negative input of the PWM circuit 106 is coupled to drain of M1. When M1 is on, current flows through M1 and, due to its drain-to-source resistance, a voltage (albeit relatively low) is produced on the drain of M1 that is proportional to the current through the inductor L1. Thus, the drain voltage of M1 is a current sense signal (ISNS).
The ISO FET control circuit 120 includes a VMAX circuit 122 coupled to an ISO FET driver 124. The VMAX circuit includes one or more comparators. The input signals to the VMAX circuit 122 are VIN and VOUT. The VMAX circuit 122 produces two output control signals—VMAX and VOUT_HI. VMAX is a voltage that is approximately equal to the larger of VIN and VOUT. That is, VMAX is approximately equal to VOUT during normal operation in which VOUT is larger than VIN, and VMAX is approximately equal to VIN during start-up or VOUT short-circuit conditions (when VIN is larger than VOUT). VMAX and VOUT_HI are provided to ISO FET driver 124. The control signal to turn on M1 is LSD_ON, and LSD_ON is also provided as input signal to the ISO FET driver 124. Further, both VP and SW are coupled to the ISO FET driver 124. An example implementation of the ISO FET driver 124 is shown in
Referring still to
Referring to the more detailed schematic of
When on (closed), S1 couples a boot strap voltage BOOT to the gate of the ISO_FET. BOOT is generated by bootstrap circuit (not shown) and is a predefined voltage above the voltage of SW. In one example, BOOT is 5V greater than SW. The source of the ISO_FET is coupled to SW. When S1 is turned on, the gate-to-source voltage (Vgs) of the ISO_FET is the BOOT voltage. In the example in which BOOT is SW+5V, the Vgs of the ISO_FET is 5V when S1 is on.
VMAX 122 forces VOUT_HI to be logic “1” responsive to VOUT being greater than VIN (normal boost operation). With one input of NOR gate being logic “1”, the output of NOR gate is logic “0” thereby turning off S2. The logic 0 from NOR gate 208, however, is inverted to a logic 1 by inverter 210 thereby turning on S1. ISO_FET is on and operating in the linear region, and functions as a current sense resistance to sense the inductor current (IL).
Referring still to
The source of SNS_FET is coupled to SW and to the BOOT voltage. The source of the SNS_FET is coupled to the source of the ISO_FET and to SW. The inverting (−) input of OP1 is coupled to the drain of the SNS_FET, and the non-inverting (+) input of OP1 is coupled to the drain of the ISO_FET. The drain of the ISO_FET is coupled to node VP. Because the voltage difference between the inverting and non-inverting inputs of an operational amplifier is approximately 0V, the drain of the SNS_FET is approximately equal to VP as well. When M1 is on, the ISO_FET operates in the linear region as noted above. The SNS_FET also operates in the linear region. The SNS_FET is a smaller transistor (size referring to the ratio of channel width (W) to channel length (L)). With their sources, drains, and gates having the same voltages, the current through the SNS_FET is proportional to, but smaller than, the current through the ISO_FET (IL). The current through the SNS_FET is labeled as I21 in
The current mirror 202 also mirrors I21 as IAVG_SNS through M4 to ILIM/current amplifier 134. The current amplifier includes a current mirror 230 formed by the two NMOS transistors M4 and M5. Current sources 120 provide, in one embodiment, the same current.
If IAVG_SNS is greater than ILIM, the excess current (the difference between IAVG_SNS and ILIM) flows into drain of M4 along with 120. In one embodiment, the mirror ratio of current mirror 230 is 1:1, and thus the current that flows through M4 also flows thorough M5. Accordingly, if IAVG_SNS is greater than ILIM, the drain current of M5 is larger than 120 and thus current flows from the gate of M2 thereby discharging gate of M2, which pulls COMP lower. Reciprocally, if IAVG_SNS is smaller than ILIM, the drain current of M5 is smaller than 120 and the excess current (120 less the drain current of M5) flows into the gate of M2 thereby charging its gate and transitioning M2 closer to the fully off state and thereby allowing COMP to increase.
During a start-up process, VIN will be greater than VOUT. VIN will also be larger than VOUT if VOUT were to be shorted to ground. Responsive to VIN being greater than VOUT, VMAX 122 forces VOUT_HI to be logic 0. With VOUT_HI being a 0, the output of NOR gate 208 is the logical inverse of LSD_ON. LSD_ON being a 1 causes M1 to turn on, and LSD_ON being a 0 causes M1 to turn off. Thus, when M1 is on (LSD_ON is a 1), the output of NOR gate 208 is a 0, which causes S2 to be off and, via inverter 210, S1 to be on. Alternatively stated, when M1 is on, S1 also is on thereby coupling the BOOT voltage to the gate of the ISO_FET. Reciprocally, when M1 is off (LSD_ON is a 0) when VIN is greater than VOUT, the output of NOR gate 208 is a 1, which causes S2 to be on and S1 to be off. Alternatively stated, when M1 is off, S2 is on (and S1 is off) and the gate of the ISO_FET is coupled through resistor R5 to SW. A control loop is created in this configuration to control the gate voltage of the ISO_FET to cause the ISO_FET to operate in the saturation region with a Vgs that regulates the current through the ISO_FET to approximately equal IL (which decreases when M1 is off). This control loop is further described below.
When VIN is greater than VOUT, VOUT_HI is 0, and the control loop operates according to two phases. One phase is when M1 is on (LSD_ON is 1). The other phase is when M1 is off (LSD_ON is 0), and is described below. When M1 is on, SW is approximately equal to ground, LSD_ON is 1, and the output of NOR gate 208 is 0. As a result, S2 is off and S1 is on. With S1 being on, the BOOT voltage is coupled to the gate of the ISO_FET.
When M1 is off, LSD_ON is 0. With both VOUT_HI and LSD_ON being 0, the output of NOR gate is a 1, which closes S2, and via inverter 210, opens S1. In this configuration, the gate of the ISO_FET is coupled to SW via resistor R5. The gate of MP is VMAX (the larger of VIN or VOUT). With VIN being greater than VOUT, VMAX is VIN and thus the gate of MP is VIN. The Vgs voltage of the ISO_FET decreases with the resistance of R5 as the load, so the drain-to-source on-resistance of the ISO_FET increases. The VP voltage will increase if the inductor current is not changed (the loop response is fast and thus the inductor current is generally unchanged). Once the VP voltage increases to higher than VIN by the sum of the forward voltage drop of diode D2 and the Vgs of MP, the MP transistor begins conducting and the source current flows through R5 to pull up the Vgs of the ISO_FET. Accordingly, a negative feedback loop is formed by the combination of MP, R5 and the ISO_FET. VP is approximately equal to the voltage on the gate of MP (VIN) plus the Vgs of MP plus the forward voltage drop across diode D2. The ISO_FET operates in the saturation region with a Vgs in the range of approximately 1 to 2 V.
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon field effect transistor (“MOSFET”) may be used in place of an n-type MOSFET with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)).
Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
This application is a continuation of U.S. patent application Ser. No. 18/525,317 filed Nov. 30, 2023, which is also a continuation U.S. patent application Ser. No. 17/563,255 filed Dec. 28, 2021, which applications are hereby incorporated herein by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18525317 | Nov 2023 | US |
| Child | 18976467 | US | |
| Parent | 17563255 | Dec 2021 | US |
| Child | 18525317 | US |
