Patent Application
20150293547
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2014-082026, filed Apr. 11, 2014, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a voltage-current conversion circuit and a power supply circuit.
A smartphone, a tablet or the like is driven by a battery, and to use the battery as long as possible, a power supply circuit called a low drop out (LDO) circuit is widely used to maintain battery life. However, as recent portable electronic devices, such as smartphones and tablets, or the like, are improved in performance every year, current consumption of each electronic component in the portable electronic device tends to increase. The more the current consumption of the portable electronic device increases, the more variation of output voltage of the LDO circuit increases, and in some cases, there is a possibility that the LDO circuit may not operate properly.
In order to prevent such a malfunction, a booster circuit may be connected to the LDO circuit, thereby suppressing variation of the output voltage from the LDO circuit. However, since the booster circuit also consumes current, the current consumption of the entire power supply circuit increases, and thus there is a possibility that a battery consumption increases.
Embodiments provide a voltage-current conversion circuit and a power supply circuit which may improve responsiveness of a current generated according to an input voltage.
In general, according to one embodiment, a voltage-current conversion circuit includes: an input port to which an input voltage is sent; a first transistor in which more current flows as the input voltage decreases; a second transistor in which more current flows as the input voltage increases; first current mirror circuitry that mirrors increased current flowing in the first transistor to an output port; second current mirror circuitry that mirrors increased current flowing in the second transistor to the output port.
Hereinafter, example embodiments are described with reference to the accompanying drawings. In the following examples, characteristic configurations and operations of the voltage-current conversion circuit and the power supply circuit are mainly described. However, configurations and operations which not specifically explained in the following description may exist in the voltage-current conversion circuit and the power supply circuit and will be apparent to those of ordinary skill in the art. These omitted configurations and operations are included in a scope of the disclosure.
The LDO circuit 2 includes a first-stage amplifier 4, a battery 5, a PMOS transistor (feedback transistor) 6, and a voltage dividing circuit 7. The voltage dividing circuit 7 generates a voltage related to the output voltage of the LDO circuit 2, that is, the voltage dividing circuit 7 generates a divided voltage related to the output voltage which is supplied as input to the first-stage amplifier 4. The battery 5 outputs a reference voltage. The first-stage amplifier 4 generates a signal according to a difference voltage between the reference voltage and the divided voltage. This signal is input to a gate of the PMOS transistor 6 which thus outputs, from a drain terminal of the PMOS transistor 6, a voltage according to an output signal of the first-stage amplifier 4. This voltage becomes the output voltage of the LDO circuit 2.
The first-stage amplifier 4 is a differential amplifier, and is configured with a circuit such as that illustrated in
The current adjustment port 26 is connected to a junction of the sources of a pair of NMOS transistors 21 and 22 and the current source 25. A current flowing in the first-stage amplifier 4 is varied by a current flowing in the current adjustment port 26, thereby adjusting the speed of response of the first-stage amplifier 4, and thus, a frequency characteristic of the first-stage amplifier 4 may be adjusted. That is, as illustrated in
The low consumption booster circuit 3 includes an input port BstIN, an output port BstOUT, first to eighth transistors Q1 to Q8, a first bias circuit 8, a second bias circuit 9, and a first current source 10. The output voltage Vo of the LDO circuit 2 is input to the input port BstIN. The current flowing in the output port BstOUT flows into the current adjustment port 26 of the LDO circuit 2. Hereinafter, a current flowing between the drain and the source of a transistor is simply referred to as a current flowing in a transistor.
A source of a first transistor Q1 configured with an NMOS transistor and a source of a second transistor Q2 configured with a PMOS transistor are connected together to the input port BstIN of the low consumption booster circuit 3. The first bias circuit 8 supplies a bias voltage to a gate of the first transistor Q1. The first bias circuit 8 includes a ninth transistor Q9 which is configured with an NMOS transistor with a gate connected to a gate of the first transistor Q1, and a second current source 11 which supplies a bias current to the ninth transistor Q9. The second bias circuit 9 supplies a bias voltage to a gate of the second transistor Q2. The second bias circuit 9 includes a tenth transistor Q10 which is configured with a PMOS transistor with a gate connected to a gate of the second transistor Q2, and a third current source 12 which supplies a bias current to the tenth transistor Q10. Each source of the ninth transistor Q9 and the tenth transistor Q10 is connected to one end of a capacitor 14. The other end of the capacitor 14 is connected to the ground node, and an impedance element 13 is connected between the one end of the capacitor 14 and the input port BstIN of the low consumption booster circuit 3.
In addition, a circuit configuration of the first bias circuit 8 and the second bias circuit 9 is not limited to a circuit illustrated in
A drain of the third transistor Q3 configured with a PMOS transistor is connected to a drain of the first transistor Q1, and the third transistor Q3 causes a current to flow according to the current flowing in the first transistor Q1. A drain of a fourth transistor Q4 configured with an NMOS transistor is connected to a drain of the second transistor Q2, and the fourth transistor Q4 causes a current to flow according to the current flowing in the second transistor Q2.
A fifth transistor Q5 configured with a PMOS transistor operates together with the third transistor Q3 to form a current mirror circuit, and the fifth transistor Q5 mirrors the current flowing in the third transistor Q3.
A sixth transistor Q6 configured with an NMOS transistor together with the fourth transistor Q4 forms a current mirror circuit, and the sixth transistor Q6 mirrors the current flowing in the fourth transistor Q4.
A drain of the sixth transistor Q6 is connected to the output port BstOUT of the low consumption booster circuit 3 and a first current source 10.
A drain of the fifth transistor Q5 is connected to a drain of a seventh transistor Q7 configured with an NMOS transistor, and the seventh transistor Q7 causes a current to flow according to the current flowing in the fifth transistor Q5. A gate of an eighth transistor Q8 configured with an NMOS transistor and a gate of the seventh transistor Q7 are connected together, and the eighth transistor Q8 mirrors the current flowing in the seventh transistor Q7. A drain of the eighth transistor Q8 is connected to the output port BstOUT of the low consumption booster circuit 3.
The first to third current sources 10 to 12 in the low consumption booster circuit 3 supply a minimum current (for example, approximately several nano-amperes) required for operating the first to tenth transistors Q1 to Q10, and when the output voltage Vo of the LDO circuit 2 is suddenly changed by a variation (hereinafter, load variation) of current consumed by the load 20, the current flowing in the output port BstOUT has a value determined by an amount of change of the output voltage Vo and by a response characteristic of the first or second transistor Q1 or Q2, only when the output voltage Vo is changed. That is, each gate of the first and second transistors Q1 and Q2 has a fixed voltage at a normal state, and the low consumption booster circuit 3 does not operate. When the low consumption booster circuit 3 does not operate, the current of the first current source 10 is set so as to be equal to a sum (IQ6+IQ8) of a current IQ6 flowing in the sixth transistor Q6 and a current IQ8 flowing in the eighth transistor Q8. Thus, when the low consumption booster circuit 3 does not operate, no current is transferred into or out of the output port BstOUT of the low consumption booster circuit 3. In contrast, if the output voltage Vo of the LDO circuit 2 changes, a gate-to-source voltage of the first transistor Q1 or the second transistor Q2 changes, and a current flowing in the first transistor Q1 or the second transistor Q2 increases. A value of the current flowing in the first transistor Q1 or the second transistor Q2 is a value determined by a voltage level of the output voltage Vo which is supplied to the sources of the transistors Q1 and Q2, and by resistance between the gates and the sources of the transistors Q1 and Q2. If the current flowing in the first transistor Q1 or the second transistor Q2 increases, the current flowing in the sixth transistor Q6 or the eighth transistor Q8 increases, but the increased current is not supplied by the first current source 10, and thus a current is supplied via the current adjustment port 26 of the first-stage amplifier 4 in the LDO circuit 2.
The operation of the power supply circuit 1 of
Conversely, if the output voltage Vo of the LDO circuit 2 suddenly increases from the normal operating state, an input voltage of the input port BstIN of the low consumption booster circuit 3 increases, and as a result, a source voltage of the second transistor Q2 increases, and the current flowing in the second transistor Q2 increases. As a result, the current flowing in the fourth transistor Q4 also increases, and the current flowing in the sixth transistor Q6 which configures the current mirror circuit together with the fourth transistor Q4 also increases. A drain of the sixth transistor Q6 is connected to the output port BstOUT of the low consumption booster circuit 3, and more current is drawn from the output port BstOUT and flows to the sixth transistor Q6. Thus, in the same manner as the decreased output voltage Vo, more current flows from the current adjustment port 26 of the first-stage amplifier 4 in the LDO circuit 2 to the output port BstOUT, and the frequency characteristic and responsiveness of the first-stage amplifier 4 are improved. Thus, in order to suppress the increase of the output voltage Vo, the LDO circuit 2 rapidly decreases the output voltage Vo.
In this way, in the first embodiment, if the output voltage Vo of the LDO circuit 2 varies, the current according to the output voltage Vo is rapidly generated in the low consumption booster circuit 3 according to the variation, and the current is drawn from the current adjustment port 26 of the first-stage amplifier 4 in the LDO circuit 2 to the sixth transistor Q6 or the eighth transistor Q8 in the low consumption booster circuit 3 via the output port BstOUT. As a result, the current flowing in the first-stage amplifier 4 increases, the capability (speed) of the first-stage amplifier 4 to charge or discharge the gate capacitance of the PMOS transistor 6 is improved. This means that the frequency characteristic and responsiveness of the first-stage amplifier 4 are improved, and the variation of the output voltage Vo of the LDO circuit 2 maybe rapidly suppressed. The first to third current sources 10 to 12 in the low consumption booster circuit 3 consume a minimum current required for operating the first to tenth transistors Q1 to Q10, and only when the output voltage Vo of the LDO circuit 2 varies, does the current determined by an amount of the variation and the response characteristic of the first or second transistor Q1 or Q2 temporarily flow. Thus, the low consumption booster circuit 3 may be operated by only an extremely small bias current, and without increasing the current consumption of the LDO circuit 2 of a low power consumption and the whole of the power supply circuit 1, the variation of the output voltage Vo maybe suppressed such that the responsiveness is improved, and the LDO circuit 2 may stably operate.
In addition, the output port BstOUT of the low consumption booster circuit 3 is connected to the current adjustment port 26 of the first-stage amplifier 4 in the LDO circuit 2. Since the current adjustment port 26, as illustrated in
Although the first embodiment described above uses a differential amplifier in which the first-stage amplifier 4 in the LDO circuit 2 are NMOS transistors, it is also possible to use a differential amplifier in which the first-stage amplifier 4 in the LDO circuit 2 has PMOS transistors. This may be preferable in some contexts because a requirement of lowering a voltage level of the battery 5 which is connected to the first-stage amplifier 4 has been recently increasing. Generally, when the voltage level of the battery 5 which is connected to the first-stage amplifier 4 is less than 0.5 V, configuring the first-stage amplifier 4 using the NMOS transistors is not easy, and configuring the first-stage amplifier 4 using the PMOS transistors is necessary. Therefore, the second embodiment described below exemplifies the differential amplifier in which the first-stage amplifier 4 in the LDO circuit 2 uses the PMOS transistors.
The LDO circuit 2 in
The low consumption booster circuit 3 in
In addition, the low consumption booster circuit 3 in
The operation of the power supply circuit 1 in
In contrast, if the output voltage Vo of the LDO circuit 2 is suddenly increased by the load variation, the current flowing in the second transistor Q2 in the low consumption booster circuit 3 increases, the current increases in a sequence of the fourth transistor Q4, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8, and then the current flowing from the output port BstOUT to the current adjustment port 26 of the first-stage amplifier 4 in the LDO circuit 2 increases. As a result, the frequency characteristic of the first-stage amplifier 4 is improved, the responsiveness of the LDO circuit 2 is improved, and an operation of rapidly pulling down the output voltage Vo is performed.
In this way, in the second embodiment, even if the first-stage amplifier 4 in the LDO circuit 2 is configured with the PMOS transistors, when the output voltage Vo of the LDO circuit 2 varies, the current flowing from the output port BstOUT to the current adjustment port 26 of the first-stage amplifier 4 may be increased, without increasing the current consumption in the low consumption booster circuit 3. Accordingly, the frequency characteristic of the first-stage amplifier 4 is improved, the LDO circuit 2 operates rapidly, and thereby the variation of the output voltage Vo may be reduced.
Although the first and second embodiments described above use MOS transistors in the low consumption booster circuit 3 and in the first-stage amplifier 4 in the LDO circuit 2, bipolar transistors may be used instead of the MOS transistors. In addition, the conductivity type of each transistor in the low consumption booster circuit 3 illustrated in
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-082026 | Apr 2014 | JP | national |
