Voltage division method for protection a gainst load dump conditions

Abstract

A protection circuit for a load dump condition employs a voltage division circuit to reduce the voltage applied to the system under test so that the peak applied voltage is reduced to permit the use of a lower voltage rating for power MOSFETs in the system under test. The voltage division circuit employs a resistor and switch in which the switch is closed at voltages higher than a given value at the terminals of the system under test; and is opened when the applied voltage reduces below the given value.

Description

FIELD OF THE INVENTION

[0002] This invention relates to electronics for automotive application and more specifically relates to a novel protection circuit against load dump test conditions.

BACKGROUND OF THE INVENTION

[0003] Automotive electronic systems are required to survive an over voltage condition, commonly known as “load dump” in which inductive components in an automotive circuit produce a voltage spike when the circuit is opened while carrying current. In this test, voltages of over 50 volts can be applied to the automotive electronics. In order to survive this test, power electronics devices, in the circuit under test, such as power MOSFETs and IGBTs, are rated to have breakdown voltages of about 55 volts or, if a zener diode clamp is used, at 38 volts, the devices can be rated at about 40 volts. The on resistance of a MOSFET increases as its reverse voltage rating increases. Thus, devices needed to withstand the load dump condition will have a higher on resistance (RDSON) than lower rated voltage devices (rated at the ordinary operating voltage of the system) resulting in a higher power loss.

[0004] It would be desirable to configure a protection circuit which would permit lower voltage power electronics devices to adequately pass the load dump test.

SUMMARY OF THE INVENTION

[0005] The circuit of the invention is a very small circuit which can reside on a PCB in every automotive electronic module which is required to pass the load dump test. In accordance with the invention, the internal resistance of the test set up is used to divide the voltage seen by the electronics system to voltages as low as 28 volts, thus permitting the use of lower RDSON MOSFETs rated at about 30 volts instead of the higher voltage (40 volts with a zener clamp and 55 volts without the clamp) and higher RDSON.

[0006] The resulting circuit has a lower cost than prior art solutions which have included use of zener diode to clamp the bus voltage to 38 volts because:

[0007] 1. Prior art solutions require the use of 40V (when a zener diode clamp is used) or 55V (if no zener diode clamp is used) rated devices which have a significantly higher Rds(on) than 30V rated devices. That means that for the same Rds(on), a 30V device will have a significantly lower cost than a 40V or 55V part, allowing the system to be lower cost.

[0008] 2. If sized properly, the bill of material cost of the invention (using 30V devices) is lower than that using the zener diode and a 40V device.

[0009] 3. Zener diodes can not be safely used to clamp the voltage at 30V because the wide variations of the reverse characteristics of the zener diode and its ‘soft slope’ would cause the zener to dissipate considerable power in double battery condition (24V).

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 shows a load dump test circuit.

[0011] FIG. 2 shows the input voltage to the circuit being tested in FIG. 1 as a function of time.

[0012] FIG. 3 shows the circuit of the invention.

[0013] FIG. 4 shows the input voltage produced by the circuit of FIG. 3.

DETAILED DESCRIPTION OF THE DRAWINGS

[0014] Referring first to FIG. 1, the test circuit for the system 10 under test is shown. The circuit contains a large capacitor 11 which is charged by a dc source (not shown) to about 100 volts. When test switch 12 connects the test network of resistors 13, 14 and 15 to the system terminals 16 and 17 the capacitor voltage spikes up as shown in FIG. 2. Note that battery 18 and diode 19 are in parallel with resistor R.

[0015] The voltage V at terminal 16 is shown in FIG. 2. Thus, at time t1, the switch 12 is closed. The system voltage of about 100 (volts dc is then applied to the system 10 with the voltage Vat terminal 16 rising immediately to about 51 volts and then decaying in about 300 milliseconds to the normal battery voltage of 90 volts.

[0016] In order to survive this test, the power electronics devices in system 10 must withstand the peak voltage of about 50 volts and are typically chosen to be about 55 volts with their attendant higher RDSON.

[0017] The circuit of the invention uses the internal resistance of the test setup to divide the voltage seen by the system down to about 30V, in which case 30V devices can be used, which have a lower on resistance value than the 40 colt, zener protected or 55 volt unprotected devices. It is also possible to change the component values and get a higher peak impressed voltage such as 38V (in which case 40V devices could be used).

[0018] Thus, as shown in FIG. 3 a resistor 20, comparator 21 and a vertical conduction MOSFET 22, or the like are added to the circuit of FIG. 1. Comparator 21 monitors the incoming voltage V and once it is above a predetermined level, turns on the switch 22 (MOSFET, or Bipolar transistor). This causes a given current to flow through the resistor 20. The resistor 14 thus has an increased current flowing through it which increases the voltage dropped across resistor 14. At a predetermined level of the voltage V, the comparator 21 turns off this current which causes the voltage to rise, but, by this time, the capacitor 11 has discharged sufficiently to allow the voltage to rise to an acceptable level. This operation is shown in FIG. 4.

[0019] Therefore, a considerably lower voltage is applied across the system 10 so that the MOSgated device in that system can be derated, for example, to 30 volt devices so that they have a lower power loss in operation.

[0020] Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein.

Claims

1. A protection circuit for protecting a system under test against applying a load dump test voltage; said system under test containing at least one power MOSFET which has first and second main power terminals; said protection comprising a source of d-c voltage; a capacitor connected across said source of d-c voltage; a first switch; a first resistor; a controllable conductive switch and a second resistor; said capacitor, said first switch, said first resistor and said first and second main power terminals connected in a closed series circuit; said second resistor and said controllable conductive switch being connected in closed series relation with said first and second main power terminals; and a control circuit for said controllable conductive device; said control circuit being connected across said main power terminals and being operable to turn on said controllably conductive switch when the voltage between said main power terminals exceeds a predetermined value whereby the voltage drop on said first resistor is increased.

2. The circuit of claim 1, wherein said controllably conductive device is a MOSFET and wherein said control circuit includes a comparator circuit connected to at least one of said first or second main power terminals.

3. The circuit of claim 1, which further includes a third resistor connected in closed series with said capacitor and said first switch.

4. The circuit of claim 2, which further includes a third resistor connected in closed series with said capacitor and said first switch.

5. The circuit of claim 1, wherein said given value is below about 38 volts.

6. The circuit of claim 2, wherein said given value is below 38 volts.

7. A load dump circuit for an automotive system including a power MOSgated device; said load dump circuit comprising an input d-c voltage derived from an automotive battery; a first and second resistor connected together at a node; a capacitor connected across said d-c voltage; a switch means operable to connect said capacitor across said series connected resistors; one of said resistors connected across the power terminals of said MOSgated device; a second switch means connected in series with said second resistor and a control circuit coupled to said power terminals for closing said second switch when the potential across said power terminals exceeds a given value.

8. The circuit of claim 7, wherein said given value is below about 38 volts.

9. The circuit of claim 7, wherein said controllably conductive device is a MOSFET and wherein said control circuit includes a comparator circuit connected to at least one of said first or second main power terminals.

10. A load dump circuit for an automotive system which includes at least one power MOSgated device having power terminals; said load dump circuit comprising an input d-c voltage derived from an automotive battery; a first and second resistor connected in a predetermined circuit relative and having a pair of output terminals; a capacitor connected across said d-c voltage and coupled to said first and second resistors; a first switch connected to said capacitor and to said first and second resistors for the changing circuit relation between said first and second resistors to change the voltage output at said first and second terminals; a second switch means connected is series with at least one of said first and second resistors; and control circuit coupled to the power terminals of said MOSgated device for operating said second switch to change the output voltage at said first and second terminals when the potential across said power terminal exceeds a given value.

11. The circuit of claim 10, wherein said given value is below 38 volts.

12. The circuit of claim 10, wherein said controllably conductive device is a MOSFET and wherein said control circuit includes a comparator circuit connected to at least one of said first or second main power terminals.