Patent Application
20060103453
This application is based upon and claims priority from prior European Patent Application No. 4 105 351.3, filed Oct. 28, 2004, the entire disclosure of which is herein incorporated by reference.
The present invention relates to a voltage down converter, and in particular to a voltage down converter for use in a semiconductor memory device, such as a non-volatile memory device.
Nowadays, many semiconductor memory devices are designed so as to be adapted to operate with low supply voltages, such as supply voltages down to 1.8 V. Considering, for example, a non-volatile semiconductor memory device (e.g., an E2PROM of flash type), the use of a relatively low supply voltage permits the use of technologies with very thin gate oxide layers (e.g., with a thickness lower than 50 Å). Accordingly, it is possible to implement semiconductor memory devices that are more compact, and that feature low power consumption.
There are however a number of applications in which the memory devices, albeit adapted to operate at very low power supply voltage values, are nevertheless required to operate at higher supply voltages, such as supply voltages of 3 V (nominal) or more. This is, for example, the case when a memory device of a new generation has to be exploited in a system, e.g., a printed circuit board, of a previous generation that operates at a higher supply voltage.
In order to avoid the necessity of fully redesigning all the existing electronic system environments in which the memory devices can be used to reduce the power supply value, countermeasures are taken by the memory device manufacturers so as to render their products directly exploitable in existing electronic system designs operating at a higher supply voltage, while at the same time avoiding damage to the tiny structures of the memory device.
As a typical countermeasure, dc-dc voltage down converters are used, for down-converting, i.e., lowering the externally received supply voltage to a suitable lower voltage. Preferably, the voltage down converters are integrated, i.e., embedded in the same chip as the memory device.
Conventional voltage down converters have a voltage regulator coupled to an internal voltage supply line (internal to the chip) that distributes a properly down-converted voltage through the memory device chip providing it to different circuits of the memory device.
An implementation of these conventional voltage down converters is an operational amplifier coupled to a MOS transistor, which can be either an NMOS or a PMOS transistor, in negative feed-back configuration. Particularly, an output terminal of the operational amplifier is coupled to the gate terminal of the MOS transistor. The MOS transistor is coupled to the internal voltage supply line, and the current sunk by the MOS transistor, regulated by the operational amplifier, is exploited to satisfy the current requests of circuits of the memory devices. For performing a regulation of the down-converted voltage, the internal voltage supply line coupled to the MOS transistor is feed-back connected to one of the input terminals of the operational amplifier, while the other input terminal receives a reference voltage. Any variation of the voltage difference at the input terminals of the operational amplifier implies a change in the drive for the MOS transistor, and consequently a variation of the current sunk by the MOS transistor. By properly sizing the feed-back circuit branch, the internal voltage supply line can be kept at the desired down-converted voltage.
A problem of such a conventional device is the output voltage stability (response speed is limited by heavy frequency compensation), because capacitive loads coupled to the internal voltage supply line dynamically vary depending on the operations performed on the memory device (different circuits may be activated, depending on the operations). The voltage down converter circuit cannot track the relatively fast changes in the requested current.
Another conventional device decouples the feed-back circuit branch of the voltage regulator from the internal voltage supply line by adding a further MOS transistor that has, as the MOS transistor inserted in the feed-back loop, its gate terminal connected to the output terminal of the operational amplifier. In this case, the regulation of the voltage at the nodes of the feed-back circuit branch is not influenced by any variation of the loads on the internal voltage supply line, and a current request of the circuits of the memory device can be satisfied by the further MOS transistor that has the gate terminal biased at the same voltage as the gate terminal of the MOS transistor of the voltage regulator.
However, this further, open-loop solution, in which the internal voltage supply line is decoupled from the voltage regulator, does not permit there to be maintained the desired down-converted voltage at the internal voltage supply line because of the dynamical variations of the loads during the operation of the memory device (the regulation characteristic of the circuit has in fact a relatively high slope).
In addition, in both the above-described conventional devices, transients in the down-converted voltage value caused by variations of the loads can have a relatively long duration, at best some tens of nanoseconds. This is not compatible with the operation of a flash memory device, which requires current pulses of amplitude of tens of milliamperes and duration of less than ten nanoseconds, and that must respect response times (access times) on the order of 50 ns.
In view of the problems described above, it is an object of the present invention to provide an improved voltage down converter for use in an integrated circuit such as a semiconductor memory device.
Another object of the present invention is to provide a voltage down converter that is stable, with relatively low response times, and which permits the regulation of the down-converted voltage when the loads dynamically change.
One embodiment of the present invention provides a voltage down converter that includes a voltage regulator circuit and at least two voltage driver circuit branches. The voltage regulator circuit receives a first voltage, has a regulation node for providing a regulated second voltage that is lower than the first voltage, and has a control node for providing a control voltage corresponding to the second voltage. One voltage driver circuit branch receives the first voltage, and includes a variable-conductivity element that has a control terminal coupled to the control node for controlling a current sunk by the variable-conductivity element from the first voltage. This one voltage driver circuit branch has a voltage supply node for supplying a down-converted voltage corresponding to the second voltage, with the voltage supply node being decoupled from the regulation node. At least one additional voltage driver circuit branch receives the first voltage, and is coupled to the voltage supply node. Each of the at least one additional voltage driver circuit branches includes a further variable-conductivity element that has a control terminal coupled to the control node for controlling a current sunk by the further variable-conductivity element from the first voltage, and a switching circuit for selectively enabling the further variable-conductivity element so as to keep the down-converted voltage at a prescribed value depending on the regulated second voltage.
Thus, according to a preferred embodiment of the present invention, there is provided a modulation of the size (for example, in the case of MOS transistors, the channel width W), and thus, of the current capability, of a hypothetical variable-conductivity element that is equivalent to the combination of the variable-conductivity element in the one voltage driver circuit branch and the further variable-conductivity element(s) in the at least one additional voltage driver circuit branch. When more current is required, the size of the hypothetical equivalent variable-conductivity element is increased, whereas the contrary takes place when the current consumption decreases.
Another embodiment of the present invention provides a method of down-converting a voltage. According to the method, a regulated voltage having a prescribed value that is lower than the voltage is generated by controlling in a closed regulation loop a first variable-conductivity element through a control signal. The control signal is used to control a second variable-conductivity element that generates a down-converted voltage from the first voltage, and the control signal is used to control at least one third variable-conductivity element external to the regulation loop, such that the at least one third variable-conductivity element cooperates with the second variable-conductivity element in generating the down-converted voltage. The at least one third variable-conductivity element is selectively enabled depending on a detected relation between the down-converted voltage and the regulated voltage.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.
Preferred embodiments of the present invention will be described in detail hereinbelow with reference to the attached drawings.
The integrated circuit 100 further includes a dc-dc Voltage Down Converter (VDC) 125 that is coupled to a voltage supply terminal 130 and to a reference voltage terminal 135 of the integrated circuit. When the memory is in use (for example, it is mounted on a printed circuit board), the voltage supply terminal 130 and the reference voltage terminal 135 are respectively connected to an external voltage supply line Vdd and to an external reference voltage supply line GND. The voltage supply line Vdd provides a supply voltage Vdd, for example +3V, relative to a reference voltage (or ground) provided by the reference voltage supply line GND. The VDC 125 generates, internally to the chip, a down-converted voltage Vo, which is supplied to the different circuits of the flash memory 110, such as the decoders and the read/write circuits; the down-converted voltage Vo takes a down-converted voltage value, such as 1.8 V. In this way, although the memory is designed and fabricated in a low-voltage technology so as to be adapted to operate at low voltages, the integrated circuit 100 can be exploited in environments in which the supply voltage values are still relatively high.
The voltage regulator 205 further includes an NMOS transistor Tr that has its gate terminal connected to an output terminal of the operational amplifier 210, so that the output terminal supplies a gate drive voltage Vg to the gate terminal of the transistor Tr. The drain terminal of the NMOS transistor Tr is coupled to the voltage supply line Vdd.
The voltage regulator 205 also includes a negative feed-back circuit branch 212 between the output terminal and an inverting input terminal “−” of the operational amplifier 210. The negative feed-back circuit branch 212 includes a first bipole Z1 and a second bipole Z2, for example both being resistors of suitable resistances. In detail, the first bipole Z1 has a first terminal connected to the source terminal of the transistor Tr and a second terminal connected to the inverting input terminal “−” of the operational amplifier 210 together with a first terminal of the second bipole Z2; the second bipole Z2 has a second terminal connected to ground. In operation, the voltage regulator 205 causes the source terminal of the transistor Tr to reach a prescribed, regulated voltage Vr.
The VDC 125 further includes a stand-by voltage driver 220 for providing the down-converted voltage Vo to circuits of the flash memory during a memory stand-by condition. Particularly, the stand-by voltage driver 220 includes an NMOS transistor Tsb and a capacitor C. The transistor Tsb has its gate terminal connected to the output terminal of the operational amplifier 210 so as to be driven by the same gate voltage Vg as the transistor Tr. The drain terminal of the transistor Tsb is coupled to the (voltage supply terminal 130 and thus to the) supply voltage line Vdd, while the source terminal is connected to a first terminal of the capacitor C; a second terminal of the capacitor C is connected to ground. In operation, particularly during stand-by, the first terminal of the capacitor C is intended to reach the down-converted voltage Vo.
The down-converted voltage Vo is provided to the flash memory 110 and thus to its internal circuits by a down-converted voltage supply line (identified in the drawings by the same reference numeral Vo), which is accordingly coupled to electric loads which vary depending on the operations to be performed on the flash memory. The capacitor C, decoupled from the voltage regulator 205, is sized in such a way as to hold a desired voltage Vo by a current sunk by the transistor Tsb during the stand-by condition of the flash memory; for example, the capacitor C has a capacitance of only about 2 nF.
Furthermore, the VDC 125 according to the presently described embodiment of the present invention comprises at least one, and preferably a number N (for example, 60) of additional voltage drivers 225-1 to 225-N connected in parallel to the stand-by voltage driver 220 between the voltage supply Vdd and the ground. Each generic additional voltage driver 225-i (where i is an index equal to 1 to N) includes an NMOS transistor T-1 to T-N having its gate terminal coupled to the output terminal of the operational amplifier 210 so as to driven by the same gate voltage Vg as the transistors Tr and Tsb, and its source terminal coupled to the down-converted voltage supply line Vo. In this exemplary embodiment, all the transistors T-1 to T-N of the additional voltage drivers 225-1 to 225-N have the same size and the same current drive capability of 0.7 mA.
Each generic additional voltage driver 225-i also includes a switch SW-i for selectively decoupling the respective NMOS transistor T-i from the voltage supply line Vdd. In this exemplary embodiment, the switch SW-i (e.g., simply implemented by a PMOS transistor, although any other implementation is suitable) has a first terminal connected to the drain terminal of the transistor T-i and a second terminal coupled to the (voltage supply terminal 130, and thus to the) voltage supply line Vdd.
The VDC 125 further comprises a control unit 230 that receives the down-converted voltage Vo and the regulated voltage Vr, and that provides enabling signals EN-1 to EN-N for selectively enabling (activating) respective switches SW-1 to SW-N in accordance with a result of a comparison of the down-converted voltage Vo and the regulated voltage Vr. During a stand-by condition of the flash memory, all the switches SW-1 to SW-N are preferably kept disabled.
The VDC 125 has to provide the down-converted voltage Vo at the desired value when the flash memory is operating, and the loads coupled to the down-converted voltage supply line Vo vary depending on the operations to be performed. Particularly, the VDC 200 has to provide the down-converted voltage Vo approximately equal to the regulated voltage Vr at a node of the voltage regulator 205 that is decoupled from the down-converted voltage supply line Vo.
The voltage regulator 205 permits there to be obtained the desired regulated voltage Vr thanks to the negative feed-back that varies the current sunk by the transistor Tr depending on the difference between the band-gap reference voltage Vbg and a voltage V− at the inverting input terminal “−” of the operational amplifier 210. In detail, if the voltage V− is lower than the band-gap reference voltage Vbg, the gate voltage Vg increases, in turn causing an increase in the current sunk by the transistor Tr. Accordingly, a current flowing through the two bipoles Z1 and Z2 increases, thereby causing an increase in the voltages Vr and, as a consequence, V−. Otherwise, if the voltage V− is higher than the band-gap reference voltage Vbg, the gate voltage Vg decreases, in turn causing a decrease in the current sunk by the transistor Tr. Accordingly, the current flowing through the two bipoles Z1 and Z2 decreases causing a decrease in the voltages Vr and V−. As a consequence, the negative feed-back regulates the voltage Vr at a node of the feed-back circuit branch 212 according to the equalization of the voltages at the two input terminals of the operational amplifier 210. By properly sizing the transistor Tr and the two bipoles Z1 and Z2, the regulated voltage Vr at the source terminal of the transistor Tr takes a desired down-converted voltage value, such as for example 1.8 V or even lower.
The gate voltage Vg reached at the output terminal of the operational amplifier 210 also properly biases the gate terminals of the transistor Tsb of the stand-by voltage driver 220 and the transistors T-1 to T-N of the additional voltage drivers 225-1 to 225-N, in such a way that they are made conductive. However, the number of additional voltage drivers 225-1 to 225-N enabled to sink a current from the voltage supply line Vdd is controlled by the control unit 230, which dynamically compares the regulated voltage Vr and the down-converted voltage Vo during the operation of the flash memory.
A variation of the current required by the flash memory circuits coupled to the down-converted voltage supply line Vo inevitably causes a variation of the value of the down-converted voltage Vo. The VDC 125 according to this embodiment of the present invention is responsive to such a variation, and the need for a greater or smaller current is compensated by the enabling or the disabling of a number of switches SW-1 to SW-N that depends on the comparison between the current value of the down-converted voltage Vo and the value of the regulated voltage Vr.
By enabling or disabling one or more (e.g., a number) of the switches SW-1 to SW-N, the control unit 230 performs a sort of modulation of the width W of a hypothetic, equivalent single transistor that is formed by the parallel of the MOS transistors Tsb and T-1 to T-N considered as a whole. By modulating the transistor width W, a variation of the transistor transconductance shown by the MOS transistors Tsb and T-1 to T-N in parallel considered as a whole permits there to be increased or decreased the current sunk from the voltage supply line Vdd during the operation of the flash memory.
Accordingly, if the down-converted voltage Vo is lower than the regulated voltage Vr, the control unit 230 enables a greater number of switches SW-1 to SW-N (thereby increasing the width W of the hypothetic equivalent single transistor). Otherwise, if the down-converted voltage Vo is higher than the regulated voltage Vr, the control unit 230 disables a required number of switches SW-1 to SW-N (thereby reducing the width W of the hypothetic equivalent single transistor). For example, at the power-on of the flash memory the control unit enables half of the switches SW-1 to SW-N. Successively, if the down-converted voltage Vo decreases with respect to the regulated voltage Vr, the control unit 230 enables some more, and possibly all, of the switches SW-1 to SW-N; whereas, if the down-converted voltage Vo increases with respect to the regulated voltage Vr, the control unit 230 disables some, and possibly all, of the switches SW-1 to SW-N.
The VDC 125 according to the described embodiment of the present invention is stable irrespective of the variation of the loads at the down-converted voltage supply line Vo. This VDC, easily integratable in the same chip as the flash memory, is flexible and adaptive to the load variations, because it permits there to be regulated the down-converted voltage at the desired value also when the loads dynamically change. In addition, this VDC is adapted to also work when the external supply voltage Vdd increases (e.g., up to 4 V) or decreases (e.g., down to 2.4 V) with respect to the typical value of 3 V. Furthermore, this VDC works even if the external supply voltage Vdd is lower (e.g., below about 2.3 V). For this purpose, a small, internal charge pump 216 may be provided, which turns on when the external supply voltage Vdd falls below a prescribed threshold (e.g., 2.3 V) in order to sustain the working potential of the internal nodes of the operational amplifier 210. In this condition, VDC current consumption increases a little (e.g., up to 9 μA), but not to an unacceptable extent.
The comparator 300 includes a reference circuit branch 305 comprising a PMOS transistor PI and an NMOS transistor N1. The transistors P1 and N1 have their drain terminals connected together and their gate terminals connected together; furthermore, both the transistors N1 and P1 are diode connected (i.e., they have their gate terminal connected to their drain terminal). The source terminal of the transistor P1 receives the regulated voltage Vr, while the source terminal of the transistor N1 is connected to ground; in this way the gate terminals of the transistors N1 and P1 reach a bias voltage Vb depending on the regulated voltage Vr. Depending on a ratio of the sizes of the transistors N1 and P1, the bias voltage Vb can be equal, for example, to about Vr/2 (a current flowing through the reference circuit branch 305 is equal, for example, to only about 30 μA).
The comparator 300 further includes a comparison circuit branch 310 comprising a PMOS transistor P2 and an NMOS transistor N2; for example, the transistors N2 and P2 have substantially the same sizes as the transistors N1 and P1, respectively. The transistors P2 and N2 have their drain terminals connected together and their gate terminals connected to the gate terminals of the transistors N1 and P1, and thus biased at the bias voltage Vb. The source terminal of the transistor P2 receives the down-converted voltage Vo, while the source terminal of the transistor N2 is connected to ground. Accordingly, the drain terminals of the transistors N2 and P2 reach a comparison voltage Vm depending on both the down-converted voltage Vo and the bias voltage Vb (and thus on the regulated voltage Vr).
The comparator 300 further includes a first amplifying stage 315 and a second amplifying stage 320, cascade-connected, for providing the control signal M, whose logic value corresponds to the comparison voltage Vm, and which takes a voltage value that is necessary to be correctly read by further control logic circuits of the control unit.
In detail, the first amplifying stage 315 comprises an inverter I1 having an input terminal receiving the comparison voltage Vm. The first amplifying stage 315 further comprises a PMOS transistor P3 and an NMOS transistor N3 having their source terminals connected together to the input terminal of the inverter I1 and their gate terminals connected together to an output terminal of the inverter I1 (i.e., the transistors P3 and N3 are both feed-back connected in source-follower configuration with the inverter I1). The drain terminal of the transistor P3 is coupled to ground, while the drain terminal of the transistor N3 is coupled to the voltage supply line Vdd.
The second amplifying stage 320 comprises an inverter 12 having an input terminal connected to the output terminal of the inverter I1 and an output terminal that provides the control signal M.
If the down-converted voltage Vo is equal to the regulated voltage Vr, a current flowing through the comparison circuit branch 310 is equal to a current flowing through the reference circuit branch 305, because the gate and source terminals of the transistors N1, N2, P1 and P2 are biased at the same voltage.
In this condition the transistors P3 and N3, feed-back connected in source-follower configuration with the inverter I1, allow the input to the inverter I1 to be maintained in its trigger region, so as to make possible a fast successive switching of the inverter I1 when the comparison voltage Vm departs from a balance condition, corresponding to the down-converted voltage Vo being substantially equal to the regulated voltage Vr.
If the down-converted voltage Vo increases with respect to the regulated voltage Vr, a current sunk by the transistor P2 increases with respect to a current sunk by the transistor N2 and, then, the comparison voltage Vm increases. This increase of the comparison voltage Vm triggers the switching of the inverter I1 and, accordingly, the cascade-connection of the two inverters I1 and 12 brings the control signal M to a voltage value (such as the down-converted voltage Vo) corresponding to the high logic value ‘1’.
Otherwise, if the down-converted voltage Vo decreases with respect to the regulated voltage Vr, a current sunk by the transistor P2 decreases with respect to a current sunk by the transistor N2 and, then, the comparison voltage Vm decreases. This decrease of the comparison voltage Vm triggers the switching of the inverter I1 and, accordingly, the cascade-connection of the two inverters I1 and 12 brings the control signal M at a voltage value (such as ground) corresponding to the low logic value ‘0’.
The control signal M provides an indication of the necessity to increase/decrease the current conduction capability of the voltage drivers, and can be exploited for controlling one or more of the switches SW-1, SW-2, . . . , SW-N.
Simulations have been performed for evaluating the rising and falling times of the above-described comparator 300.
Initially, the down-converted voltage Vo is at a voltage value higher than the regulated voltage Vr, with a difference of less than ten millivolts and, thus, the control signal M takes a voltage value equal to the down-converted voltage Vo corresponding to the high logic value ‘1’. Successively, the down-converted voltage Vo decreases by about 15 mV and, after only about 2 ns, the control signal M falls to the voltage value corresponding to the low logic value ‘0’ (i.e., the ground).
In this case, initially, the down-converted voltage Vo is at a voltage value lower than the regulated voltage Vr, with a difference of less than ten millivolts and, then, the control signal M takes a voltage value equal to the ground. Successively, the down-converted voltage Vo increases by about 15 mV and, after only about 1 ns, the control signal M rises to the voltage value corresponding to the high logic value ‘1’ (i.e., the down-converted voltage Vo).
Thus, the comparator has relatively low falling and rising times when little variations of the down-converted voltage Vo with respect to the regulated voltage Vr occur (in the example of only 15 mV). This permits there to be implemented a VDC having relatively low response times compatible with the operation of a flash memory, as well as a comparator with a simple architecture that operates with low power consumption.
By providing a suitable number of comparators similar in structure to the comparator shown in
With respect to the comparator of
In detail, the first further comparison circuit branch 505 includes a PMOS transistor P4 and an NMOS transistor N4 having their drain terminals connected together. The gate terminals of the transistors P4 and N4 are connected to the gate terminals of the transistors P1 and N1 so as to be biased at the bias voltage Vb. The source terminal of the transistor P4 is connected to the voltage supply line Vdd and the source terminal of the transistor N4 is connected to ground. The sizes of the transistors P4 and P1 are such that a ratio thereof is equal to about 0.8, while the sizes of the transistors N4 and N1 are equal. The size ratio of the transistors P4 and P1, being lower than 1, introduces a negative voltage offset in the comparison between the regulated voltage Vr and the down-converted voltage Vo.
The second further comparison circuit branch 510 includes a PMOS transistor P5 and an NMOS transistor N5 having their drain terminals connected together. The gate terminals of the transistors P5 and N5 are connected to the gate terminals of the transistors P1 and N1 so as to be biased at the bias voltage Vb. The source terminal of the transistor P5 is connected to the voltage supply line Vdd and the source terminal of the transistor N5 is connected to ground. The sizes of the transistors P5 and P1 are such that a ratio thereof is equal to about 1.2, while the sizes of the transistors N5 and N1 are equal. The size ratio of the transistors P5 and P1, being higher than 1, introduces a positive voltage offset in the comparison between the regulated voltage Vr and the down-converted voltage Vo.
A first further comparison voltage V1 at the drain terminals of the transistors P4 and N4 is provided, similarly to the comparison voltage Vm, to two further amplifying stages 315 and 320 for providing a first further control signal L. The first further control signal L takes, for example, a high logic value ‘1’ when the down-converted voltage Vo is higher than the regulated voltage Vr plus the negative voltage offset (e.g., Vr −25 mV) and a low logic value ‘0’ when the down-converted voltage Vo is lower than the regulated voltage Vr plus the negative voltage offset (hereinafter the first further control signal L is referred to as the low control signal L).
Similarly, a second further comparison voltage Vh at the drain terminals of the transistors P5 and N5 is provided to two further amplifying stages 315 and 320 for providing a second further control signal H. The second further control signal H takes, for example, a high logic value ‘1’ when the down-converted voltage Vo is higher than the regulated voltage Vr plus the positive voltage offset (e.g., Vr +25 mV) and a low logic value ‘0’ when the down-converted voltage Vo is lower than the regulated voltage Vr plus the positive voltage offset (hereinafter the second further control signal H is referred to as the high control signal H).
Thus, the comparator 500 provides three control signals L, M, and H which can be exploited for controlling the switches SW-1, SW-2, . . . , SW-N for a fine modulation of the transistor width W of the parallelly-connected voltage drivers of the down converter according to embodiments of the present invention. For example, the plurality of N additional voltage drivers is logically partitioned into three subsets (for example, each one containing the same number of additional voltage drivers) and each control signal L, M, and H is exploited to control a respective subset of additional voltage drivers.
The precision of the voltages Vl, Vm, and Vh is not relevant, since some trimming structures can be provided in the flash memory (for example, based on non-volatile storage elements) and can be exploited for storing an information used to adjust them during a memory testing phase.
The number of comparison branches in the comparator can be lower than three, for example two comparison branches, or higher than three, for an even finer control of the modulation of the current delivery capability of the voltage drivers, and thus of the down-converted voltage.
The comparators according to the two described embodiments of the present invention, in addition to having relatively short rising and falling times, have a very flexible architecture, and a relatively low power consumption. These comparators are easily modifiable for introducing desired voltage offsets in the comparison between the down-converted voltage Vo and the regulated voltage Vr.
Although the present invention has been disclosed and described by way of an embodiment, it is apparent to those skilled in the art that several modifications to the described embodiment, as well as other embodiments of the present invention are possible without departing from the scope thereof as defined in the appended claims.
For example, the comparison circuit branches of the comparator can be in a number greater than three and can include, as the reference circuit branch, a different number of transistors. A different number of control signals can drive a different number of subsets of voltage drivers, for a finer control of the down-converted voltage Vo. The voltage regulator and the voltage drivers can be implemented in a different way, for example, by exploiting a different number of transistors and switches.
Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 04 105 351.3 | Oct 2004 | EP | regional |
