Patent Application
20070296487
The above and/or other aspects and advantages will become more apparent and more readily appreciated from the following detailed description of example embodiments taken in conjunction with the accompanying drawings of which:
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Embodiments may, however, be in many different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope to those skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.
It will be understood that when a component is referred to as being “on,” “connected to” or “coupled to” another component, it can be directly on, connected to or coupled to the other component or intervening components may be present. In contrast, when a component is referred to as being “directly on,” “directly connected to” or “directly coupled to” another component, there are no intervening components present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one component or feature's relationship to another component(s) or feature(s) as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, and/or components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference will now be made to example embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like components throughout.
The static current circuit 10 may include an operational amplifier 11, a first PMOS transistor 12, and/or a first resistor 13. A reference potential VREF may be provided to an inverted input node (−) of the operational amplifier 11. A drain and gate of the first PMOS transistor 12 may be connected to the non-inverted input node (+) and an output node of the operational amplifier 11, respectively. A source of the first PMOS transistor 12 may be connected to a power source voltage VCC. The first resistor 13 may be connected between the drain of the first PMOS transistor 12 and a ground.
The current mirror 20 may include second and third PMOS transistors 21 and 24, first and second NMOS transistors 22 and 25, and/or second and third resistors 23 and 26.
A source of the second PMOS transistor 21 may be connected to the power source voltage VCC, and/or a gate of the second PMOS transistor 21 may be coupled to the gate of the first PMOS transistor 12. A drain and gate of the first NMOS transistor 22 may be connected to each other and/or connected to a drain of the second PMOS transistor 21. The second resistor 23 may be connected between a source of the first NMOS transistor 22 and the ground.
A source of the third PMOS transistor 24 may be connected to the power source voltage VCC, and/or a gate and drain of the third PMOS transistor 24 may be connected to each other. A drain of the second NMOS transistor 25 may be connected to the drain of the third PMOS transistor 24 and a gate of the second NMOS transistor 25 may be connected to the gate of the first PMOS transistor 22. The third resistor 26 may be connected between a source of the second NMOS transistor 25 and the ground. An output terminal 27 of the voltage generation circuit 100 may be connected to the source of the second NMOS transistor 25.
If the reference potential VREF is applied to the inverted input node (−) of the operational amplifier 11, the operational amplifier 11 may operate to maintain a source potential of the first PMOS transistor 12 at the reference potential VREF. If the resistance of the first resistor 13 is R1, a current I1 flowing through the first resistor 13 is I1=VREF/R1. Because the first PMOS transistor 12 and the first resistor 13 form a source follower, the first PMOS transistor 12 may operate to maintain the current I1.
For example, if the first and second PMOS transistors 12 and 21 have the same gate width to length (W/L) ratio, a current I2 flowing through the second resistor 23 may be the same as the current I1 flowing through the first resistor 13 because an output voltage of the operational amplifier 11 is applied to the gates of the first and second PMOS transistors 12 and 21. For example, I1=I2. Accordingly, if the resistance of the second resistor 23 is R2 and a terminal voltage across the second resistor 23 to the ground is V2, V2=I2*R2=(R2/R1)*VREF.
If the gate width to length (W/L) ratios of the third PMOS transistor 24 and the second NMOS transistor 25 are a number n times the gate width to length (W/L) ratios of the second PMOS transistor 21 and the first NMOS transistor 22, a current I3 flowing through the third resistor 26 of the current mirror 20 may be I3=n*I2. If the resistance R3 of the third resistor 26 is set to 1/n of the resistance R2 of the second resistor 23, a terminal voltage V3 across the third resistor 26 to the ground is V3=I3*R3=n*I2*R2/n=I2*R2=V2.
Therefore, in a case of requiring a smaller static voltage less than 1.0V, the voltage generation circuit 100 may be able to receive a substantially constant voltage of about 1.25V, regardless of temperature and/or voltage variation, by generating the reference potential VREF from a bandgap reference circuit. For example, a smaller static voltage less than 1.0V may be obtained from optimizing the resistance R2 of the resistor 23.
In a case of transitioning a load into the smaller voltage from the ground, the voltage generation circuit 100 may be able to charge the load at a higher frequency because the second NMOS transistor 25 driving the load may operate in the form of a source follower. The gate width to length (W/L) ratios of the third PMOS transistor 24 and the second NMOS transistor 25 may be the number n times the gate width to length (W/L) ratio of the second PMOS transistor 21 and/or the current I1 may be maintained by the first PMOS transistor 12 to increase an active drivability. The resistance R3 of the third resistor 26 may be 1/n of the resistance R2 of the second resistor 23. Accordingly, it may be possible to set n times drivability to a larger capacity of load.
The first resistor 13, the second resistor 23, and the third resistor 26 may include a polysilicon layer, a diffusion layer, or a composite of a polysilicon layer and a diffusion layer. Accordingly, a process imbalance may be lightened, for example, as compared to a process imbalance of a transistor-type device, and/or a stabilized smaller voltage or a larger current may be enabled because of lower temperature dependence by resistors.
A memory cell array 59 may include a plurality of memory cells of floating-gate field effect transistors (FETs) that are coupled to the row and column lines. The memory cells may be arranged in a matrix pattern. The row decoder 58 included in the flash memory device may drive control gates of the memory cells. The floating-gate FET may include a source and drain that are formed in a P-type well settled within an N-type well of a semiconductor substrate, a floating gate formed over the substrate through an insulation film between the source and drain, and/or a control gate formed over the floating gate through an intergate insulation film.
For example, a procedure of erasing the flash memory may include biasing gates with a negative voltage, e.g., about −9V. Sources and drains may be conditioned in open states and/or a substrate may be biased with a static voltage, e.g., about 5˜9V. Under the aforementioned bias conditions, electrons accumulated in a floating gate may be discharged into the substrate and thereby the memory cells may be erased.
For example, because discharging directions of electrons from the floating gate are irregular, threshold voltages of memory cells may be partially set to be lower than a desired, or alternatively, a permissible range of distribution. If there are memory cells having lower threshold voltages in the memory cell array, there may be a current flowing through a column line in a deselected state for which a row line voltage is 0V. Accordingly, it may be impossible to read information from a selected memory cell with the sense amplifier 56.
In determining if threshold voltages of the memory cells of the memory cell array 59 are conditioned lower than a desired, or alternatively, a permissible range of distribution, all row lines of the memory cells are deselected. The sense amplifier 56 may check a status of threshold voltages of the memory cell array by using an assistant power source of about 0.2-0.3V of the row decoder 58 as a potential of deselected row lines. For example, the internal power control circuit 55 may include the voltage generation circuit of example embodiments, and the voltage control circuit may provide a smaller voltage as the power source for a potential of deselected row lines so that the sense amplifier 56 may check a status of threshold voltages of the memory cell array.
Therefore, by providing the internal power control circuit 55 with the voltage generation circuit according to example embodiments and/or operating the internal power control circuit 55 with the controller 52, the NOR-type flash memory device may be able to check a status of threshold voltages of the memory cell array 59 during the erasing operation.
The level shifter 40 may include a fourth PMOS transistor 28 and/or a third NMOS transistor 29. A source of the fourth PMOS transistor 28 may be connected to the power source voltage VCC, and/or a gate of the fourth PMOS transistor 28 may be coupled to the gate of the first PMOS transistor 12. A drain and gate of the third NMOS transistor 29 may be commonly connected to a drain of the fourth NMOS transistor 28 and/or a source of the third NMOS transistor 29 may be grounded.
The current mirror 30 may include a first NMOS transistor 22′ having a source connected to the ground and/or a gate coupled to a gate of the third NMOS transistor 29, a second PMOS transistor 21′ having a drain and gate commonly connected to a drain of the first NMOS transistor 22′, a second resistor 23′ connected between a source of the second PMOS transistor 21′ and the power source voltage VCC, a second NMOS transistor 25′ having a source connected to the ground and/or a drain and gate coupled to each other, a third PMOS transistor 24′ having a drain connected to a drain of the second NMOS transistor 25′ and/or a gate coupled to the gate of the second PMOS transistor 21′, a third resistor 26′ connected between a source of the third PMOS transistor 24′ and the power source voltage VCC, and/or an output terminal 27′ connected to the source of the third PMOS transistor 24′.
Referring to
The gate voltage Vgp3 may be applied to the gate of the first NMOS transistor 22′. The first NMOS transistor 22′ may have the same gate width to length ratio (W/L) as the third NMOS transistor 29. Accordingly, a current I2′ flowing through the first NMOS transistor 22′ may be the same as the current I1′. Gate width to length (W/L) ratios of the third PMOS transistor 24′ and the second NMOS transistor 25′ may be a number n times the gate width to length ratios (W/L) of the second PMOS transistor 21′ and the first NMOS transistor 22′. Accordingly, the current mirror 30 may operate to induce a current I3′ (=n*I2′) through the third resistor 26′.
The resistance R3′ of the third resistor 26′ may be 1/n of the resistance R2′ of the second resistor 23′ and/or a terminal voltage to the power source voltage VCC of the second resistor 23′ is referred to as V2′. Accordingly, a terminal voltage V3′ to the power source voltage VCC across the third resistor 26′ is V3′=I3*′R3′=n*I2′*R2′/n=I2′*R2′=V2′.
In a case of requiring a smaller voltage lower than 1.0V, by generating the reference voltage VREF with the band gap reference circuit, a voltage generation circuit 100 may be able to receive a substantially constant voltage of about 1.25V regardless of variation of power source voltage or temperature. Accordingly, by optimizing the resistance R2′ of the second resistor 23′, a smaller static voltage less than 1.0V, for example a smaller static voltage infinitesimally smaller than the power source voltage VCC, may be obtained.
In transitioning a load into the smaller voltage from the power source voltage VCC, the voltage generation circuit 100 may be able to charge the load at a higher frequency because the third PMOS transistor 24′ driving the load is a source follower. In order to set larger drivability, the current I1′ may be maintained by the first PMOS transistor 12, the gate width to length (W/L) ratios of the third PMOS transistor 24′ and the second NMOS transistor 25′ may be a number n times the gate width to length (W/L) ratios the second PMOS transistor 21′ and the first NMOS transistor 22′, respectively, and/or the resistance R3′ of the third resistor 26′ may be designed to be 1/n the resistance R2′ of the second resistor 23′. Accordingly, it may be possible to set n times drivability to a larger-capacity load.
The first resistor 13, the second resistor 23′, and the third resistor 26′ may include a polysilicon layer, a diffusion layer, or a composite of a polysilicon layer and a diffusion layer. Accordingly, a process imbalance may be lightened, for example, as compared to a transistor-type device, and/or a stabilized smaller voltage or a larger current may be enabled because of lower temperature dependence by resistors.
The voltage generation circuit according to example embodiments may be able to set a supply current using a smaller voltage. Accordingly, a faster voltage transition of a load may be conducted. The resistors of the static current circuit setting a static current may be formed to generate a stabilized smaller voltage or a larger current because of their lower temperature dependence and/or smaller process imbalance, for example, as compared to a transistor-type device. Moreover, by applying the voltage generation circuit 100 of example embodiments, threshold voltage conditions of a memory cell array may be checked during an erasing operation.
The voltage generation circuit according to example embodiments may be able to set a supply current at a desired, or alternatively, a predetermined rate, to conduct a faster voltage transition. The resistors of the static current circuit setting a static current may be formed to generate a stabilized smaller voltage or a larger current because of their lower temperature dependence and/or smaller process imbalance, for example, as compared to a transistor-type device.
Although example embodiments have been shown and described in this specification and figures, it would be appreciated by those skilled in the art that changes may be made to the illustrated and/or described example embodiments without departing from their principles and spirit.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2006-0171646 | Jun 2006 | JP | national |
