Voltage level converting circuit and display apparatus including the same

Abstract

A voltage level converting circuit may include a first transistor including a first terminal coupled with a first terminal supplying a first voltage, and a control terminal coupled with an input terminal, a second transistor including a first terminal coupled with a second terminal supplying a second voltage lower than the first voltage, and a control terminal coupled with the input terminal, a third transistor including a first terminal coupled with a third terminal supplying a third voltage higher than the first voltage, a second terminal coupled with an output terminal, and a control terminal coupled with a second terminal of the second transistor, and a fourth transistor including a first terminal coupled with a fourth terminal supplying a fourth voltage lower than the second voltage, a second terminal coupled with the output terminal, and a control terminal coupled with a second terminal of the first transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

FIG. 1 illustrates a circuit diagram of a voltage level converting circuit according to an exemplary embodiment of the present invention;

FIG. 2 illustrates a circuit diagram of a voltage level converting circuit according to another exemplary embodiment of the present invention;

FIG. 3 illustrates a circuit diagram of a voltage level converting circuit according to another exemplary embodiment of the present invention; and

FIG. 4 illustrates a circuit diagram of a voltage level converting circuit according to another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 10-2006-0090456, filed on Sep. 19, 2006, in the Korean Intellectual Property Office, and entitled: “Voltage Level Converting Circuit and Display Apparatus Comprising the Same,” is incorporated by reference herein in its entirety.

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout the specification.

FIG. 1 illustrates a circuit diagram of a voltage level converting circuit 100 according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the voltage level converting circuit 100 may include a first power supply terminal 31, a second power supply terminal 32, a third power supply terminal 33, a fourth power supply terminal 34, an input terminal 35, an output terminal 36, first through fourth switching transistors Q1 through Q4, and first through seventh resistors R1 through R7.

A first voltage may be applied to the first power supply terminal 31, and a second voltage, which may be lower than the first voltage, may be applied to the second power supply terminal 32. For example, in some embodiments of the invention, the first voltage may be 5 V and the second voltage may be a ground voltage. Embodiments of the invention are not, however, limited thereto.

A high-level input signal including the first voltage or a low-level input signal including the second voltage may be applied to the input terminal 35. In some embodiments of the invention, e.g., a low voltage of a TTL-level (0-5 V) may be applied to the input terminal 35.

A third voltage +VCC, which may be higher than the first voltage, may be applied to the third power supply terminal 33. A fourth voltage −VEE, which may be lower than the second voltage, may be applied to the fourth power supply terminal 34.

In some embodiments of the invention, a high-level output signal obtained by amplifying the third voltage +VCC, or a low-level output signal obtained by amplifying the fourth voltage −VEE may be output to the output terminal 36.

In embodiments in which a general transistor is employed as the third switching transistor Q3, the third voltage +VCC may rise to a maximum voltage of about 50V. In embodiments in which a high voltage transistor is employed as the third switching transistor Q3, a voltage higher than 50V may be output.

The first switching transistor Q1 may be a pnp bipolar transistor. In such embodiments employing a pnp bipolar transistor as the first switching transistor Q1, an emitter of the first switching transistor Q1 may be coupled with the first power supply terminal 31, a base of the first switching transistor Q1 may be coupled with the input terminal 35, and a collector of the first switching transistor Q1 may be coupled with a base of the fourth switching transistor Q4. If the first voltage of a high level, e.g., 5V, is applied to the input terminal 35, the first switching transistor Q1 may be turned off. If the second voltage of a low level, e.g., 0V, is applied to the input terminal 35, the first switching transistor Q1 may be turned on.

The first resistor R1 may be coupled between the first power supply unit 31 and the emitter of the first switching transistor Q1. The first resistor R1 may limit emitter current and the collector current of the first switching transistor Q1.

The second switching transistor Q2 may be a npn bipolar transistor. In such embodiments employing a npn bipolar transistor as the second switching transistor Q2, an emitter of the second switching transistor Q2 may be coupled with the second power supply terminal 32, a base of the second switching transistor Q2 may be coupled with the input terminal 35, and a collector of the second switching transistor Q2 may be coupled with a base of the third switching transistor Q3. When the first voltage of a high level, e.g., 5V, is applied to the input terminal 35, the second switching transistor Q2 may be turned on. When the second voltage of a low level, e.g., 0V, is applied to the input terminal 35, the second switching transistor Q2 may be turned off.

The second resistor R2 may be coupled between the second power supply terminal 32 and the emitter of the second switching transistor Q2. The second resistor R2 may limit emitter current and collector current of the second switching transistor Q2.

A first terminal of the seventh resistor R7 may be coupled with the ground voltage, and a second terminal of the seventh resistor R7 may be coupled with the base of the first switching transistor Q1 and the base of the second switching transistor Q2. When the input terminal 35 is open, the seventh resistor R7 may allow application of a voltage of 0V.

The third switching transistor Q3 may be a pnp bipolar transistor. In such embodiments employing a pnp bipolar transistor as the third switching transistor Q3, an emitter of the third switching transistor Q3 may be coupled with the third power supply terminal 33, a collector of the third switching transistor Q3 may be coupled with the output terminal 36, and the base of the third switching transistor Q3 may be coupled with the collector of the second switching transistor Q2. When the second switching transistor Q2 is turned on, the third switching transistor Q3 may also be turned on.

The third resistor R3 may be coupled between the third power supply terminal 33 and the emitter of the third switching transistor. Q3. The third resistor R3 may limit emitter current and collector current of the third switching transistor Q3.

A first terminal of the fifth resistor R5 may be coupled with the third power supply terminal 33, and a second terminal of the fifth resistor R5 may be coupled with the base of the third switching transistor Q3 and the collector of the second switching transistor Q2. The fifth resistor R5 may provide a constant and/or substantially constant voltage to the base of the third switching transistor Q3 and the collector of the second switching transistor Q2. When the second switching transistor Q2 is turned on, a voltage obtained by subtracting a voltage drop due to the fifth resistor R5 from the third voltage +VCC may be provided to the base of the third switching transistor Q3 and the collector of the second switching transistor Q2, and accordingly the third switching transistor Q3 may also be turned on. In order to turn on the third switching transistor Q3, the fifth resistor R5 may have a resistance greater than that of the third resistor R3.

The fourth switching transistor Q4 may be a npn bipolar transistor. In such embodiments employing a npn bipolar transistor as the third switching transistor Q3, an emitter of the fourth switching transistor Q4 may be coupled with the fourth power supply terminal 34, a collector of the fourth switching transistor Q4 may be coupled with the output terminal 36, and the base of the fourth switching transistor Q4 may be coupled with the collector of the first switching transistor Q1. When the first switching transistor Q1 is turned on, the fourth switching transistor Q4 may also be turned on.

The fourth resistor R4 may be coupled with the fourth power supply terminal 34 and the emitter of the fourth switching transistor Q4. The fourth resistor R4 may limit emitter current and collector current of the fourth switching transistor Q4.

A first terminal of the sixth resistor R6 may be coupled with the fourth power supply terminal 34, and a second terminal of the sixth resistor R6 may be coupled with the base of the fourth switching transistor Q4 and the collector of the first switching transistor Q1. The sixth resistor R6 may provide a constant and/or substantially constant voltage to the base of the fourth switching transistor Q4 and the collector of the first switching transistor Q1. When the first switching transistor Q1 is turned on, a voltage obtained by adding a voltage increase value due to the sixth resistor R6 to the fourth voltage −VEE may be provided to the base of the fourth switching transistor Q4 and the collector of the first switching transistor Q1. Accordingly, the fourth switching transistor Q4 may also be turned on. In order to turn on the fourth switching transistor Q4, the sixth resistor R6 may have a resistance greater than that of the fourth resistor R4.

Hereinafter, exemplary operation of the exemplary embodiment voltage level converting circuit 100 of FIG. 1 will be described in detail.

A low voltage of a TTL-level (0-5 V) may be applied to the input terminal 35. In such cases, e.g., a high-level input signal including a first voltage, e.g., 5V, or a low-level input signal including a second voltage, e.g., OV, may be applied to the input terminal 35.

When the low-level input signal is applied to the input terminal 35, the first switching transistor Q1 may be turned on and the second switching transistor Q2 may be turned off. When the first switching transistor Q1 is turned on, a constant and/or substantially constant voltage may be applied to the collector of the first switching transistor Q1 and the base of the fourth switching transistor Q4. Accordingly, the fourth switching transistor Q4 may be turned on and the fourth voltage −VEE may be output through the output terminal 36.

When the high-level input signal is applied to the input terminal 35, the first switching transistor Q1 may be turned off and the second switching transistor Q2 may be turned on. When the second switching transistor Q2 is turned on, a constant and/or substantially constant voltage may be applied to the collector of the second switching transistor Q2 and the base of the third switching transistor Q3. Accordingly, the third switching transistor Q3 may be turned on and the third voltage +VCC may be output through the output terminal 36.

In embodiments in which a general transistor is employed as the third switching transistor Q3, the third voltage +VCC may rise to a maximum voltage of about 50V, and thus, an output voltage swing may be increased to a relatively high voltage of about 50V. In embodiments in which a high voltage transistor is employed as the third switching transistor Q3, a voltage higher than 50V may be output, and thus, an output voltage swing may be increased to a voltage higher than about 50V.

In embodiments of the invention, because the output voltage may swing between the third voltage +VCC and the fourth voltage −VEE, it is possible to vary the output voltage swing by changing the third voltage +VCC and the fourth voltage −VEE.

FIG. 2 illustrates a circuit diagram of a voltage level converting circuit 200 according to another exemplary embodiment of the present invention.

Hereinafter, in general, only differences between the exemplary voltage level converting circuit 200 illustrated in FIG. 2 and the exemplary voltage level converting circuit 100 illustrated in FIG. 1 will be described.

Referring to FIG. 2, as compared to the exemplary voltage level converting circuit 100 of FIG. 1, the exemplary voltage level converting circuit 200 may further include first through fourth diodes D1 through D4.

A cathode of the first diode D1 may be coupled with the collector of the second bipolar transistor Q2, and an anode of the first diode D1 may be coupled with the base of the third bipolar transistor Q3. A cathode of the second diode D2 may be coupled with the collector of the second bipolar transistor Q2, and an anode of the second diode D2 may be coupled with the collector of the third bipolar transistor Q3.

An anode of the third diode D3 may be coupled with the collector of the first bipolar transistor Q1, and a cathode of the third diode D3 may be coupled with the collector of the fourth bipolar transistor Q4. An anode of the fourth diode D4 may be coupled with the collector of the first bipolar transistor Q1 and a cathode of the fourth bipolar transistor Q4 may be coupled with the base of the fourth bipolar transistor Q4.

When the first through fourth diodes D1 through D4 are coupled as illustrated in FIG. 2, switching speeds of the third bipolar transistor Q3 and the fourth bipolar transistor Q4 may be significantly improved.

More particularly, e.g., before an emitter-base voltage of the third bipolar transistor Q3 enters a saturation area, the second diode D2 may be switched on so as to bypass the base current of the third bipolar transistor Q3 to the collector of the third bipolar transistor Q3. As a result, the third bipolar transistor Q3 may be prevented from operating in the saturation area, and accordingly, the switching speed of the third bipolar transistor Q3 may be improved.

Likewise, before an emitter-base voltage of the fourth bipolar transistor Q4 enters the saturation area, the third diode D3 may be switched on so as to bypass the base current of the fourth bipolar transistor Q4 to the collector of the fourth bipolar transistor Q4. As a result, the fourth bipolar transistor Q4 may be prevented form operating in the saturation area, and accordingly, the switching speed of the fourth bipolar transistor Q4 may be improved.

FIG. 3 illustrates a circuit diagram of an exemplary voltage level converting circuit 300 according to another exemplary embodiment of the present invention.

Hereinafter, in general, only differences between the exemplary voltage level converting circuit 300 illustrated in FIG. 3 and the exemplary voltage level converting circuit 100 illustrated in FIG. 1 will be described.

Referring to FIG. 3, as compared to the exemplary voltage level converting circuit 100 of FIG. 1, the voltage level converting circuit 300 may include a first schottky diode SD1 and a second schottky diode SD2, and may not include the fifth resistor R5 and the sixth resistor R6.

A cathode of the first schottky diode SD1 may be coupled with the base of the third bipolar transistor Q3, and an anode of the first schottky diode SD1 may be coupled with the collector of the third bipolar transistor Q3.

An anode of the second schottky diode SD2 may be coupled with the base of the fourth bipolar transistor Q4, and a cathode of the second schottky diode SD2 may be coupled with the collector of the fourth bipolar transistor Q4.

When the first schottky diode SD1 and the second schottky diode SD2 are coupled as illustrated in FIG. 3, like the case where the first through fourth diodes D1 through D4 are coupled as illustrated in FIG. 2, the switching speeds of the third bipolar transistor Q3 and the fourth bipolar transistor Q4 may be improved.

Before an emitter-base voltage of the third bipolar transistor Q3 enters the saturation area, the first schottky diode SD1 may be switched on so as to bypass the base current of the third bipolar transistor Q3 to the collector of the third bipolar transistor Q3. As a result, the third bipolar transistor Q3 may be prevented from operating in the saturation area, and accordingly, the switching speed of the third bipolar transistor Q3 may be improved.

Likewise, before an emitter-base voltage of the fourth bipolar transistor Q4 enters the saturation area, the second schottky diode SD2 may be switched on so as to bypass the base current of the fourth bipolar transistor Q4 to the collector of the fourth bipolar transistor Q4. As a result, the fourth bipolar transistor Q4 may be prevented from operating in the saturation area, and accordingly, the switching speed of the fourth bipolar transistor Q4 may be improved.

When the first through fourth diodes D1 through D4 are coupled as illustrated in FIG. 2, or the first schottky diode SD1 and the second schottky diode SD2 are coupled as illustrated in FIG. 3, a rising time period and a falling time period of an output signal may be reduced to a maximum of about 100 ns. Accordingly, the exemplary voltage level converting circuits 200, 300 illustrated in FIGS. 2 and 3 may perform high-speed switching operations.

FIG. 4 illustrates a circuit diagram of an exemplary voltage level converting circuit 400 according to another embodiment of the present invention.

Hereinafter, in general, only differences between the exemplary voltage level converting circuit 400 illustrated in FIG. 4 and the exemplary voltage level converting circuit 100 illustrated in FIG. 1 will be described.

Referring to FIG. 4, as compared to the exemplary voltage level converting circuit 100 of FIG. 1, the voltage level converting circuit 400 may employ, e.g., first through fourth MOS transistors M1 through M4, instead of, e.g., pnp or npn bipolar transistors, for the first through fourth switching transistors Q1 through Q4.

The first switching transistor M1 may be a PMOS transistor. In such embodiments employing a PMOS transistor as the first switching transistor M1, a first terminal of the first switching transistor M1 may be coupled with the first power supply terminal 31 via the first resistor R1, a gate of the first switching transistor M1 may be coupled with the input terminal 35, and a second terminal of the first switching transistor M1 may be coupled with a gate of the fourth switching transistor M4.

The second switching transistor M2 may be a NMOS transistor. In such embodiments employing a NMOS transistor as the second switching transistor M2, a first terminal of the second switching transistor M2 may be coupled with the second power supply terminal 32 via the second resistor R2, a gate of the second switching transistor M2 may be coupled with the input terminal 35, and a second terminal of the second switching transistor M2 may be coupled with a gate of the third switching transistor M3.

The third switching transistor M3 may be a PMOS transistor. In such embodiments employing a PMOS transistor as the third switching transistor M3, a first terminal of the third switching transistor M3 may be coupled with the third power supply unit 33 via the third resistor R3, a second terminal of the third switching transistor M3 may be coupled with the output terminal 36, and the gate of the third switching transistor M3 may be coupled with the second terminal of the second switching transistor M2.

The fourth switching transistor M4 may be an NMOS transistor. In such embodiments employing a NMOS transistor as the fourth switching transistor M4, a first terminal of the fourth switching transistor M4 may be coupled with the fourth power supply terminal 34 via the fourth resistor R4, a second terminal of the fourth switching transistor M4 may be coupled with the output terminal 36, and the gate of the fourth switching transistor M4 may be coupled with the second terminal of the first switching transistor M1.

The first and second terminals of each of the first through fourth switching transistors M1 through M4 may be a source and a drain, respectively, however, embodiments of the present invention are not limited thereto.

Embodiments of the invention may provide voltage level converting circuits capable of obtaining a voltage swing output with a large amplitude, as compared to conventional voltage level converting circuits including analog switches and OP-AMPs.

Embodiments of the invention may separately provide voltage level converting circuits employing a switching speed enhancement device that allows a bipolar transistor to operate in a non-saturation area.

Embodiments of the invention may separately provide voltage level converting circuits capable of having faster and/or improved rising speed(s) and falling speed(s) of a voltage swing output therefrom.

Embodiments of the invention may separately provide voltage level converting circuits employing relatively inexpensive devices, and thus, capable of being manufactured at relatively lower cost than conventional voltage level converting circuits.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

Exemplary embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims

1. A voltage level converting circuit, comprising: a first switching transistor including a first terminal coupled with a first power supply terminal to which a first voltage is applied, and a control terminal coupled with an input terminal;a second switching transistor including a first terminal coupled with a second power supply terminal to which a second voltage lower than the first voltage is applied, and a control terminal coupled with the input terminal;a third switching transistor including a first terminal coupled with a third power supply terminal to which a third voltage higher than the first voltage is applied, a second terminal coupled with an output terminal, and a control terminal coupled with a second terminal of the second switching transistor; anda fourth switching transistor including a first terminal coupled with a fourth power supply terminal to which a fourth voltage lower than the second voltage is applied, a second terminal coupled with the output terminal, and a control terminal coupled with a second terminal of the first switching transistor.

2. The circuit as claimed in claim 1, wherein when a high-level input signal including the first voltage or a low-level input signal including the second voltage is applied to the input terminal, a high-level output signal obtained by amplifying the third voltage or a low-level output signal obtained by amplifying the fourth voltage is output through the output terminal.

3. The circuit as claimed in claim 1, further comprising a first resistor coupled with the first power supply terminal and the first terminal of the first switching transistor, a second resistor coupled with the second power supply terminal and the first terminal of the second switching transistor, a third resistor coupled with the third power supply terminal and the first terminal of the third switching transistor, and a fourth resistor coupled with the fourth power supply terminal and the first terminal of the fourth switching transistor.

4. The circuit as claimed in claim 3, further comprising at least one of a fifth resistor coupled with the third power supply terminal and the control terminal of the third switching transistor, and a sixth resistor coupled with the fourth power supply terminal and the control terminal of the fourth switching transistor.

5. The circuit as claimed in claim 4, wherein the fifth resistor has a larger resistance than the third resistor, and the sixth resistor has a larger resistance than the fourth resistor.

6. The circuit as claimed in claim 1, further comprising a seventh resistor coupled with the input terminal and a ground voltage.

7. The circuit as claimed in claim 1, wherein the second voltage is a ground voltage.

8. The circuit as claimed in claim 1, wherein the first through fourth switching transistors are bipolar transistors.

9. The circuit as claimed in claim 8, wherein the first and third switching transistors are pnp bipolar transistors, and the second and fourth switching transistors are npn bipolar transistors.

10. The circuit as claimed in claim 8, wherein the first terminal of each of the first through fourth switching transistors is an emitter, the second terminal of each of the first through fourth switching transistors is a collector, and the control terminal of each of the first through fourth switching transistors is a base.

11. The circuit as claimed in claim 8, further comprising switching speed enhancement devices respectively coupled with the third bipolar transistor and the fourth bipolar transistor.

12. The circuit as claimed in claim 10, further comprising: a first diode including a cathode coupled with the collector of the second bipolar transistor, and an anode coupled with the base of the third bipolar transistor;a second diode including a cathode coupled with the collector of the second bipolar transistor, and an anode coupled with the collector of the third bipolar transistor;a third diode including an anode coupled with the collector of the first bipolar transistor, and a cathode coupled with the collector of the fourth bipolar transistor; anda fourth diode including an anode coupled with the collector of the first bipolar transistor, and a cathode coupled with the base of the fourth bipolar transistor.

13. The circuit as claimed in claim 10, further comprising: a first schottky diode including a cathode coupled with the base of the third bipolar transistor, and an anode coupled with the collector of the third bipolar transistor; anda second schottky diode including an anode coupled with the base of the fourth bipolar transistor, and a cathode coupled with the collector of the fourth bipolar transistor.

14. The circuit as claimed in claim 1, wherein the first through fourth transistors are MOS transistors.

15. The circuit as claimed in claim 14, wherein the first and third switching transistors are PMOS transistors, and the second and fourth switching transistors are NMOS transistors.

16. The circuit as claimed in claim 14, wherein the first terminal of each of the first through fourth transistors is a source, the second terminal of each of the first through fourth transistors is a drain, and the control terminal of each of the first through fourth transistors is a gate.

17. The circuit as claimed in claim 1, wherein at least the third switching transistor is a high voltage transistor.

18. A display apparatus comprising a display unit including a plurality of pixels, and a driver unit including a voltage level converting circuit in order to drive the plurality of pixels, wherein the voltage level converting circuit comprises: a first switching transistor including a first terminal coupled with a first power supply terminal to which a first voltage is applied, and a control terminal coupled with an input terminal;a second switching transistor including a first terminal coupled with a second power supply terminal to which a second voltage lower than the first voltage is applied, and a control terminal coupled with the input terminal;a third switching transistor including a first terminal connected to a third power supply terminal to which a third voltage higher than the first voltage is applied, a second terminal coupled with an output terminal, and a control terminal coupled with a second terminal of the second switching transistor; anda fourth switching transistor including a first terminal coupled with a fourth power supply terminal to which a fourth voltage lower than the second voltage is applied, a second terminal coupled with the output terminal, and a control terminal coupled with a second terminal of the first switching transistor.

19. The display apparatus as claimed in claim 18, wherein when a high-level input signal including the first voltage or a low-level input signal including the second voltage is applied to the input terminal, a high-level output signal obtained by amplifying the third voltage or a low-level output signal obtained by amplifying the fourth voltage is output through the output terminal.

20. The display apparatus as claimed in claim 18, wherein the voltage level converting circuit further comprises a first resistor coupled with the first power supply terminal and the first terminal of the first switching transistor, a second resistor coupled with the second power supply terminal and the first terminal of the second switching transistor, a third resistor coupled with the third power supply terminal and the first terminal of the third switching transistor, and a fourth resistor coupled with the fourth power supply terminal and the first terminal of the fourth switching transistor.