Patent Application
20140062448
1. Technical Field
The present disclosure relates to an electronic device with a voltage level converting circuit.
2. Description of Related Art
Electronic devices include a voltage level converting chip for converting internal logic levels (such as transistor-transistor logic (TTL)) to standard interface line levels (such as RS-232 voltage levels) for transmitting through a serial port. For example, in the TTL logic mode, the logic voltage level of “1” is a voltage ranging from 3.6˜5V, and the logic voltage level “0” is a voltage ranging from 0˜2.4V; in the RS-232 logic mode, the logic voltage level “0” is a voltage ranging from 3˜15V, and the logic voltage level “1” is a voltage ranging from −3˜15V. The voltage level converting chip is an integrated circuit, a complicated circuit with a plurality of electronic parts. However, a new chip is needed when one of internal electronic parts in the chip is damaged.
Therefore, there is room for improvement in the art.
Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout two views.
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at “least one.”
The power supply 10 provides a first voltage, a second voltage, and a pulse voltage with a predetermined duty cycle to the voltage level converting circuit 40 when the electronic device 100 is powered on. The first voltage is higher than the second voltage. In the embodiment, the power supply 10 is an internal battery.
The processing module 20 is capable of generating or receiving logic voltage levels in the first mode.
The communicating module 30 is capable of outputting logic voltage levels in the second mode. In the embodiment, the communicating module 30 is a serial port, such as a RS232 port.
The voltage level converting circuit 40 is connected between the processing module 20 and the communicating module 30 and receives the first voltage, the second voltage, and the pulse voltage from the power supply 10. The voltage level converting circuit 40 converts the logic voltage levels between the first mode and the second mode. The voltage level converting circuit 40 comprises a voltage converting module 41, a first converting module 43, and a second converting module 45. The voltage converting module 41 converts the received pulse voltage into a third voltage.
The first converting module 41 converts the logic voltage levels in the first mode generated by the processing module 20 into the logic voltage levels in the second mode based on the first voltage, the second voltage, and the third voltage, and transmits the logic voltage levels in the second mode to the communicating module 30. The second voltage is larger than the third voltage.
The second converting module 45 converts the logic voltage levels in the second mode received through the communicating module 30 into the logic voltage levels in the first mode based on the second voltage, and transmits logic voltage levels in the first mode to the processing module 20.
Referring to
The processing module 20 includes an input terminal I1 and an output terminal O1. The input terminal I1 is connected to the second converting module 45, and the output terminal O1 is connected to the first converting module 43.
The communicating module includes an input pin P1 and an output pin P2. The input pin P1 is connected to the output terminal O1 through the second converting module 43, and the output pin P2 is connected to the input terminal I1 through the first converting module 45.
The voltage converting module 41 includes a first transistor Q1, a first pull-up resistor R1, a first resistor Ra, a first capacitor C1, a second capacitor C2, an electrolytic capacitor C3, a first diode D1, a second diode D2, and a node A1. A base of the first transistor Q1 is connected to the pulse voltage terminal Vp through the first resistor Ra. An emitter of the first transistor Q1 is grounded. A collector of the first transistor Q1 is connected to the first voltage terminal V1 through the first pull-up resistor R1. An anode of the first diode D1 is connected to the collector of the first transistor Q1 through the first capacitor C1. A cathode of the first diode D1 is connected to the emitter of the first transistor Q1. An anode of the second diode D2 is connected to the first converting module 43. A cathode of the second diode D2 is connected to the collector of the first transistor Q1 through the first capacitor C1. Opposite terminals of the second capacitor C2 are connected to the anode of the second diode D2 and the emitter of the first transistor Q1. An anode of the electrolytic capacitor C3 is connected to the emitter of the first transistor Q1, and a cathode of the electrolytic capacitor C3 is connected to the anode of the second diode D2 through the node A1. In the embodiment, the first transistor Q1 is an npn type bipolar junction transistor; the capacitance of the electrolytic capacitor C3 is ten times more than the capacitance of the first capacitor C1.
The first converting module 43 includes a MOSFET (metal oxide semiconductor field effect transistor) T1, a second transistor Q2, a second pull-up resistor R2, a third pull-up resistor R3, a fourth pull-up resistor R4, and second resistor Rb. A gate of the MOSFET T1 is connected to the second voltage terminal V2. A source of the MOSFET T1 is connected to the output terminal O1. A drain of the MOSFET T1 is connected to the first voltage terminal V1 through the second pull-up transistor R2. A base of the second transistor Q2 is connected to the drain of the MOSFET T1 through the second resistor Rb. An emitter of the second transistor Q2 is connected to the first voltage terminal V1. A collector of the second transistor Q2 is connected to the input pin P1. Opposite ends of the fourth pull-up transistor R4 are respectively connected to the anode of the second diode D2 and the collector of the second transistor Q2. In the embodiment, the MOSFET T1 is an n-channel enhancement type metal oxide semiconductor field effect transistor; the second transistor Q2 is a pnp type bipolar junction transistor.
The second converting module 45 includes a third transistor Q3, a fifth pull-up resistor R5, and a third resistor Rc. A base of the third transistor Q3 is connected to the output pin P2 through the third resistor Rc. An emitter of the third transistor Q3 is grounded. A collector of the third transistor Q3 is connected to the input pin P1. Opposite terminals of the fifth pull-up resistor R5 are connected to the collector of the third transistor Q3 and the second voltage terminal V2. In the embodiment, the third transistor Q3 is an npn type bipolar junction transistor.
When the pulse voltage is in a low level, the difference between the base and the emitter of the first transistor Q1 is less than 0.7V, and the first transistor Q1 is turned off. The first diode D1 is turned on and the second diode D2 is turned off. The first pull-up resistor R1, the first capacitor C1, the first diode D1, and the electrolytic capacitor C3 form a charging path to charge the electrolytic capacitor C3. Based on the first voltage, the voltage difference between the anode and the cathode of the electrolytic capacitor C3 is 5V when the charging processing is ended. As the anode of the electrolytic capacitor C3 is grounded, the voltage at node A1, i.e. the third voltage, is −5V. When the pulse voltage is at the high level, the difference between the base and the emitter of the first transistor Q1 is more than 0.7V, the first transistor Q1 is turned on and the voltage at the collector of the transistor Q1 is almost 0V. The first diode D1 is turned off and the second diode D2 is turned on. The electrolytic capacitor C3, the second diode D2, the first capacitor C1, the collector of the first transistor Q1, and the emitter of the first transistor Q2 form a discharging path. The cathode of the electrolytic capacitor C3 provides the third voltage to the first converting module 43 through the node A1. Based on the pulse voltage of the predetermined duty cycle, the third voltage will always be −5V.
When the output terminal O1 generates a logic high voltage level in the first mode, the different between the gate and the source of the MOSFET T1 is less than 0.7V, and the MOSFET T1 is turned off. The voltage at the base of the second transistor Q2 is equal to the first voltage outputted by the first voltage terminal V1. The difference between the base and the emitter of the second transistor Q2 is less than 0.7V, thus the second transistor Q2 is turned off. The voltage of the input pin P1 is equal to the third voltage, as a logic high voltage level in the second mode. When the output terminal 01 generates a logic low voltage level in the second mode, the difference between the gate and the source of the MOSFET T1 is more than 0.7V, and the MOSFET T1 is turned on. The base of the second transistor Q2 is grounded, thus the difference between the base and the emitter of the second transistor Q2 is more than 0.7V. The second transistor Q2 is turned on. The voltage of the input pin P1 is equal to the first voltage outputted by the first voltage terminal V1, as a logic low voltage level in the second mode. Thus, the logic voltage levels in the first mode generated by the output terminal O1 are converted into the logic voltage levels in the second mode received by the input pin P1.
When the output pin P2 generates a logic high voltage level in the second mode, the different between the base and the emitter of the third transistor Q3 is less than 0.7V, thus the third transistor Q3 is turned off. The voltage of the input terminal I1 is equal to the second voltage outputted by the second voltage terminal V2, as the logic high voltage level in the first mode. When the output pin P2 generates a logic low voltage level in the second mode, the difference between the base and the emitter of the third transistor Q3 is more than 0.7V, and the third transistor Q3 is turned on. The input terminal I1 is grounded, as a logic low voltage level in the first mode. Thus, the logic voltage levels in the second mode generated by the output pin P1 are converted into the logic voltage levels in the first mode which is received by the input terminal I1.
When any internal parts of the voltage level converting circuit 40 are damaged, only the damaged/non-functioning part(s) must be replaced, there is no need to replace the whole voltage level converting circuit 40. Therefore, the voltage level converting circuit 40 is simpler, and the cost for repairing a voltage level converting circuit 40 is reduced.
It is to be understood, however, that even though information and advantages of the present embodiments have been set forth in the foregoing description, together with details of the structures and functions of the present embodiments, the disclosure is illustrative only; and changes may be made in detail, especially in the matters of shape, size, and arrangement of parts within the principles of the present embodiments to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
| Number | Date | Country | Kind |
|---|---|---|---|
| 101131302 | Aug 2012 | TW | national |
