Claims
- 1. A voltage level converting circuit for converting the voltage level of an input signal to a desired level, comprising:
- an input terminal to which an input signal may be applied;
- voltage level detecting means connected to said input terminal for detecting the voltage level of said input signal and supplying a high level output signal when said input signal has been detected to be equal to or higher than a predetermined voltage level or a low level output signal when said input signal has been detected to be lower than said predetermined voltage level, said voltage level detecting means including a first P-channel MOSFET and a first N-channel MOSFET which are connected in series between said input terminal and a first reference voltage and which have their gates connected to a second reference voltage, said voltage level detecting means further including a depletion type N-channel MOSFET which is connected in series between said input terminal and said series connected first P-channel and N-channel MOSFETs and which has its gate connected to said second reference voltage;
- inverting means having an input and an output, said input of said inverting means being connected to the junction between said first P-channel and first N-channel MOSFETs of said voltage level detecting means for inverting the output signal supplied from said voltage level detecting means; and
- a CMOS device including a pair of second P-channel and second N-channel MOSFETs which are connected in series between said input terminal and said first reference voltage, the gate of each of said second P-channel and second N-channel MOSFETs being connected to said output of said inverting means and the junction between said second P-channel and second N-channel MOSFETs being connected to an output terminal of said circuit.
- 2. A circuit of claim 1 wherein said second reference voltage is equal to said predetermined voltage level.
- 3. A circuit of claim 2 wherein said first reference voltage is ground voltage and said second reference voltage is a supply voltage.
- 4. A voltage level converting circuit for converting the voltage level of an input signal to a desired level, comprising:
- an input terminal to which an input signal may be applied;
- voltage level detecting means connected to said input terminal for detecting the voltage level of said input signal and supplying a high level output signal when said input signal has been detected to be equal to or higher than a predetermined voltage level or a low level output signal when said input signal has been detected to be lower than said predetermined voltage level, said voltage level detecting means including a first P-channel MOSFET and a first N-channel MOSFET which are connected in series between said input terminal and a first reference voltage and which have their gates connected to a second reference voltage, said voltage level detecting means further including at least one enhancement type N-channel MOSFET which is connected in series between said input terminal and said series connected first P-channel and N-channel MOSFETs and which has its gate connected to its source/drain region located closer to said input terminal;
- inverting means having an input and an output, said input of said inverting means being connected to the junction between said first P-channel and first N-channel MOSFETs of said voltage level detecting means for inverting the output signal supplied from said voltage level detecting means; and
- a CMOS device including a pair of second P-channel and second N-channel MOSFETs which are connected in series between said input terminal and said first reference voltage, the gate of each of said second P-channel and second N-channel MOSFETs being connected to said output of said inverting means and the junction between said second P-channel and second N-channel MOSFETs being connected to an output terminal of said circuit.
- 5. A circuit of claim 4 wherein said second reference voltage is equal to said predetermined voltage level.
- 6. A circuit of claim 5 wherein said first reference voltage is ground voltage and said second reference voltage is a supply voltage.
- 7. A voltage level detecting circuit for detecting the voltage level of an input signal supplied thereto for supplying a high level output signal as its output when said input signal has been detected to be equal to or higher than a predetermined voltage level or a low level output signal when said input signal has been detected to be lower than said predetermined voltage level, comprising:
- an input terminal for receiving said input signal;
- a depletion type MOSFET having a first source/drain region connected to said input terminal, a second source/drain region, and a first gate;
- a first enhancement type MOSFET having a third source/drain region connected to said second source/drain region of said depletion type MOSFET, a fourth source/drain region, and a second gate; and
- a second enhancement type MOSFET having a fifth source/drain region connected to said fourth source/drain region and to an output terminal of said circuit, a sixth source/drain region connected to a first reference voltage, and a third gate which is connected to said first and second gates and to a second reference voltage.
- 8. A circuit of claim 7 wherein said first enhancement type MOSFET is a P-channel MOSFET and said second enhancement type MOSFET is an N-channel MOSFET.
- 9. A circuit of claim 8 wherein said first reference voltage is ground voltage and said second reference voltage is a supply voltage.
- 10. A voltage level detecting circuit for detecting the voltage level of an input signal supplied thereto for supplying a high level output signal as its output when said input signal has been detected to be equal to or higher than a predetermined voltage level or a low level output signal when said input signal has been detected to be lower than said predetermined voltage level, comprising:
- an input terminal for receiving said input signal;
- at least one first enhancement type MOSFET having a first source/drain region connected to said input terminal, a second source/drain region, and a first gate connected to said first source/drain region;
- a second enhancement type MOSFET having a third source/drain region connected to said second source/drain region of said first enhancement type MOSFET, a fourth source/drain region, and a second gate; and
- a third enhancement type MOSFET having a fifth source/drain region connected to said fourth source/drain region and to an output terminal of said circuit, a sixth source/drain region connected to a first reference voltage, and a third gate which is connected to said second gate and to a second reference voltage.
- 11. A circuit of claim 10 wherein said first and third MOSFETs are N-channel MOSFETs and said second MOSFET is a P-channel MOSFET.
- 12. A circuit of claim 11 wherein said first reference voltage is ground voltage and said second reference voltage is a supply voltage.
Priority Claims (1)
Number |
Date |
Country |
Kind |
57-34769 |
Mar 1982 |
JPX |
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CROSS-REFERENCES TO RELATED APPLICATIONS
This is a continuation-in-part of application Ser. No. 471,859, filed Mar. 3, 1983, now abandoned.
US Referenced Citations (7)
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
471859 |
Mar 1983 |
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