Patent Application
20080231356
The present invention relates to analog circuits, and more particularly, to switched-capacitor circuits that may be used for voltage margining and equalization.
Voltage margining is a method for testing the ability of a transmitter or receiver to tolerate poor or marginal signal quality by purposely reducing the amplitude of voltage swings of an input signal. One approach to voltage margining is to use a high-speed tester. A tester should be able to generate a pattern of logical ones and zeros at high speed, such as for example at a speed of 6.4 GTS (Giga-Transfers-per-Second). The tester should also be able to adjust the amplitude of the input voltage swings. However, such a tester may be expensive.
In the description that follows, the scope of the term “some embodiments” is not to be so limited as to mean more than one embodiment, but rather, the scope may include one embodiment, more than one embodiment, or perhaps all embodiments.
Embodiments of the present invention provide voltage margining, and share components with an equalizer circuit that may be used in a receiver. As a result, a separate tester is not required if the equalizer circuit is already employed in the device to be tested. Making use of the components in the an existing equalizer circuit is economically efficient.
The equalizer circuit is the subject of the patent application “Switched Capacitor Equalizer with Offset Voltage Canceling,” by Luke A. Johnson and Yueming He, Ser. No. 11/396,393, filed Mar. 31, 2006, hereinafter referred to as “switched capacitor equalizer”, and assigned to the same assignee as the present patent application.
A circuit according to an embodiment of the present invention is illustrated in
An enable signal is indicated in
The voltage source comprising current source 102, pMOSFETs P1 and P2, and resistors R1 and R2, serves the function of a DAC-controlled (Digital-to-Analog Converter) voltage source. In the embodiment of
Although a description of the equalization function of the embodiment of
Assume that amplifier 104 has an offset voltage VOS, and let A denote the gain of amplifier 104. In the embodiment of
Denoting the input voltages by VIP and VIM as indicated in
Suppose now that the clock signals transition so that clock signal φ1 goes LOW and clock signal φ2 goes HIGH. The input voltages VIP and VIM will, in general, change in value from what they were before the clock transition. To distinguish these new values, a time discrete time index n is introduced, so that we may represent the old input voltage values as VIP[n−1] and VIM[n−1] and the new voltage values as VIP[n] and VIM[n]. This notation may be applied to the other voltages in the circuit. With this notation, we have before the clock transition the relationships VC1[n−1]−VC2[n−1]≈VOS and VC3[n−1]−VC4[n−1]≈VIM[n−1]−VIP[n−1]+VOS. For the new clock transition, switches SW1 and SW2 close, and switches SW3, SW4, SW5, and SW6 open, and as a result there is, in general, a transfer of charge among capacitors C1 and C3 such that their voltage drops are equal to each other, and a transfer of charge among capacitors C2 and C4 so that their voltage drops are equal to each other.
The magnitude of the charge transferred among capacitors C1 and C3, denoted as ΔQ13, is ΔQ13=|VC3[n−1]−VC1[n−1]|(CE∥C1), and the magnitude of the charge transferred among C2 and C4, denoted as ΔQ24, is ΔQ24=|VC4[n−1]−VC2[n−1]|(CE∥C1) where (CE∥C1) is the capacitance of capacitors C3 and C1 (or C4 and C2) in parallel. As a result of this charge transfer, the new voltage at the positive input port of amplifier 104 at time index n is VIP[n]+VC3[n−1]−(VC3[n−1]−VC1[n−1])(CE∥CI)/CE, and the new voltage at the negative input port of amplifier 104 at time index n at is VIM[n]+VC4[n−1]−(VC4[n−1]−VC2[n−1])(CE∥C1)/CE. If y[n] denotes the differential output voltage y[n]=VOP[n]−VOM[n], and x[n] denotes the differential input voltage x[n]=VIP[n]−VIM[n], then from the previous expressions for the voltages at the negative and positive input ports of amplifier 104 and the relationships VC1[n−1]−VC2[n−1] VOS and VC3[n−1]−VC4[n−1]≈VIM[n−1]−VIP[n−1]+VOS, it follows that
y[n]≈2A(x[n]−Kx[n−1]),
where the scalar multiplier K is given by K=CE/(CE+C1).
In the above displayed equation, the discrete-time analog output y[n] is readily identified as the sum of the output of a discrete-time differentiator and the output of a linear amplifier. The effective combination of a discrete-time differentiator with a linear amplifier results in an equalization filter, or equalizer. This equalizer may be employed to help mitigate the effects of intersymbol interference in a bandlimited channel, and may be used in many transmit pre-emphasis and de-emphasis schemes.
In practice, there are other circuit components that may be used in an equalizer circuit. For example, switches may be employed to cross-couple the output ports of amplifier 104 to its input ports so that after an evaluation of the signal, the output voltages of amplifier 104 are latched and driven to full rail. See, for example, the switched capacitor equalizer patent application. Furthermore, the equalizer circuit may be replicated, but where the clock signals are interchanged for the replica, so that the resulting combination of equalizer circuits may perform equalization on opposite clock phases.
In the above discussion, it was noted that for large amplifier gain A, VC1−VC2≈VOS. In a sense, capacitors C1 and C2 store the offset voltage, and the offset voltage is cancelled from the input voltage to amplifier 104. It may also be shown that because of charge sharing with other components in the circuit of
The DAC-controlled voltage source comprising current source 102, pMOSFETs P1 and P2, and resistors R1 and R2, should be designed so that the voltages generated at nodes n1 and n2 also have the same common mode voltage as the differential input voltage applied to the VIP and VIM input ports. of amplifier 104.
As a result of the above discussion, when the circuit of
This may be illustrated by considering a simple numerical example. Suppose Vcc is 1V and that the offset voltage is zero. Because of charge sharing, the common mode voltage 500 mV is placed on the input ports of amplifier 104. If the circuit is configured as an equalizer without voltage margining, then when switches SW5 and SW6 are closed; the voltage at the terminals of capacitors C1 and C2 coupled together via switches SW5 and SW6 is at 250 mV; the voltage drop across capacitor C1 is 250 mV (the voltage on the terminal of capacitor C1 connected to amplifier 104 is 250 mV higher than the other terminal of capacitor C1); and the voltage drop across capacitor C2 is 250 mV (the voltage on the terminal of capacitor C2 connected to amplifier 104 is 250 mV higher than the other terminal of capacitor C2). Suppose pMOSFETs P1 and P2 are set so that the steady state voltages at nodes n1 and n2 are set to 300 mV and 200 mV, respectively. When voltage margining is enabled so that nMOSFETs Q1 and Q2 are ON, and when switches SW5 and SW6 are closed (switches SW1 and SW2 are open), the voltage drop across capacitor C1 drops to 200 mV (the voltage on the terminal of capacitor C1 connected to amplifier 104 is 200 mV higher than the other terminal of capacitor C1), and the voltage drop across capacitor C2 rises to 300 mV (the voltage on the terminal of capacitor C2 connected to amplifier 104 is 300 mv higher than the other terminal of capacitor C2).
As a result, when the clock signal φ1 is LOW so that switches SW5 and SW6 (and switches SW3 and SW4) are now opened, and the clock signal φ2 is HIGH so that switches SW1 and SW2 are now closed, the differential voltage applied to the input ports of amplifier 104 is now 100 mV less than it would be if the voltage drops on capacitors C1 and C2 were each equal to 250 mv. That is, for example, if the voltage VIM is at 0 mV, and the voltage VIP is at 500 mV, then the voltage difference between the input ports of amplifier 104 is reduced to 400 mV instead of the 500 mV it would have been if no voltage margining were applied.
In this way, embodiments provided voltage margining to amplifier 104.
Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below. For example, the voltages generated at node n1 and n2 need not be generated by a DAC-controlled current source, but analog-controlled current sources may also be utilized.
It is to be understood in these letters patent that the meaning of “A is connected to B”, where A or B may be, for example, a node or device terminal, is that A and B are connected to each other so that the voltage potentials of A and B are substantially equal to each other. For example, A and B may be connected together by an interconnect (transmission line). In integrated circuit technology, the interconnect may be exceedingly short, comparable to the device dimension itself. For example, the gates of two transistors may be connected together by polysilicon, or copper interconnect, where the length of the polysilicon, or copper interconnect, is comparable to the gate lengths. As another example, A and B may be connected to each other by a switch, such as a transmission gate, so that their respective voltage potentials are substantially equal to each other when the switch is ON.
It is also to be understood in these letters patent that the meaning of “A is coupled to B” is that either A and B are connected to each other as described above, or that, although A and B may not be connected to each other as described above, there is nevertheless a device or circuit that is connected to both A and B. This device or circuit may include active or passive circuit elements, where the passive circuit elements may be distributed or lumped-parameter in nature. For example, A may be connected to a circuit element that in turn is connected to B.
It is also to be understood in these letters patent that a “current source” may mean either a current source or a current sink. Similar remarks apply to similar phrases, such as, “to source current”.
It is also to be understood in these letters patent that various circuit components and blocks, such as current mirrors, amplifiers, etc., may include switches so as to be switched in or out of a larger circuit, and yet such circuit components and blocks may still be considered connected to the larger circuit.
