Patent Application
20150301092
1. Technical Field
The present disclosure generally relates to DC/DC convertors and methods for DC/DC conversion. More particularly, it concerns a voltage polarity detection circuit adapted for the detection of Continuous Conduction Mode (CCM) to Discontinuous Conduction Mode (DCM) boundary of a switched DC/DC converter.
It finds application, for instance, in power-management platforms for wireless devices such as mobile phones, smart phones, digital audio players, PDAs, e-books readers, or the like.
2. Related Art
The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
A DC/DC converter is an electronic circuit which converts a source of direct current (DC) from one voltage level to another, higher or lower voltage level. Electronic Switched Mode Power Supply (SMPS) circuits convert one DC voltage level to another, by controlling a switch to store the input energy temporarily and then release that energy to the output at a different voltage. The storage may be in either magnetic field storage components (inductors, transformers) or electric field storage components (capacitors). In magnetic DC/DC converters, the energy is periodically stored into and released from a magnetic field in an inductor or a transformer, typically in the range from 300 kHz to 10 MHz. By adjusting the duty cycle of the switching, i.e., the ratio of ON/OFF time of the switch, the amount of energy transferred to the output can be controlled. Usually, this is applied to control the output voltage, and therefore a switch driving circuit is adapted to sense the output voltage and generate a control signal for driving the switch.
With reference to
Depending on the arrangement of the inductor L, switch S, capacitor C and rectifying diode D, the DC/DC converter can be of the Buck, Boost or Buck-Boost type. A DC/DC converter of the Buck type (as shown in
The efficiency of such DC/DC converters has increased thanks to the use of synchronous rectification, by replacing the flywheel diode with a power-MOS with lower ON-resistance, thereby reducing losses and allowing generation of supply voltages of lower value.
As shown in
Discontinuous Conduction Mode (DCM) is a mode of operation of the DC/DC converter wherein in order to protect inductance current IL against polarity inversion during the conduction cycle of the power switch S, the power stage is disconnected (said power stage is in high impedance state). Likewise, Continuous conduction Mode (CCM) is a mode of the operation of DC/DC converter wherein the inductance current IL is not inverted during the conduction cycle. The converter operates in DCM when low current is drawn by the load R, and in CCM at higher load current levels. Indeed, when the amount of energy required by the load R is small enough to be transferred in a time lower than the switching period, the current through the inductor falls to zero during part of this period.
The DCM/CCM boundary detection is a fundamental functionality of each modern DC/DC convertor, enabling the convertor to be operated in various operating modes, for instance pure PWM mode or pulse-skipping mode. Pulse skipping mode is an operation mode which enables to decrease the power consumption of the DC/DC converter and thus to increase the battery-life of the mobile device, e.g, mobile phone. The accurate detection of the boundary between DCM and CCM is an important issue having a major role on the power efficiency and reliability of the DC/DC converter.
The boundary between the DCM and CCM is defined by the zero-valley inductor current, i.e. zero-current at the end of the NMOS conduction cycle. If this zero-current is not properly detected, the conduction on the PMOS transistor body-diode occurs, which considerably increases the power losses of the converter. In fact, when inductor current is inverted, the output capacitor is discharged by the power stage. This is opposite compared to the required features of the power stage, which is supposed to drive the power into the output capacitor during the whole PWM conduction cycle.
Therefore, and as shown further in
There are two methods which may be used in practice to detect the current polarity of the inductor current IL at the end of NMOS conduction period. In a first method used in DC/DC convertors with low operating frequencies, the conduction on the body-diodes of the power-MOS is observed. In a second method suitable for DC/DC converters with higher switching frequency (when the non-overlapping time is not properly defined), the voltage VDS on the power-MOS drain is observed.
The present disclosure addresses DC/DC converters relying on this second polarity detection method.
With reference to
The voltage VDS(t=TCLK) at the end of NMOS conduction period is equal to:
V
DS
=I
L
·R
DS
N (1)
where RDS
Zero-current detection solutions known in the art are based on a comparator having a differential input pair. In order to ensure the required accuracy, this comparator must either be trimmed after fabrication (which is expensive) or must use a special design technique, leading to important silicon surface and current consumption. When the comparator is not trimmed, the system must exhibit a high robustness due to increased dispersion, which considerably lowers the power efficiency of the convertor. Sometimes, an additional sensing resistance is inserted to increase the VDS voltage, which leads to additional power losses.
Other existing solutions also use sampling of the VDS voltage at the end of NMOS conduction period, which is subsequently evaluated with a slower, but more accuracy, differential pair based comparator.
Reference US 2011/291632 discloses a power converter which includes a power converting unit and a switch driving circuit. A zero-current detector is configured to adjust the offset voltage based on a first detection voltage signal generated by a switch driving circuit and to generate a zero-current detecting signal based on the offset voltage. The offset voltage and the zero-current detecting signal are associated with a current in the power converting unit.
This solution requires a high performance, i.e., high speed and high accuracy comparator, however leading to high power consumption, or requires post-fabrication trimming of the comparator to enhance its quality. Obtaining such high quality comparator contributes to an important part of the DC-DC convertor design, and it costs lots of resources.
An accurate CCM to DCM boundary detection would allow to improve the converter device features such as efficiency, and reliability of the control. This is a challenging improvement in particular for the devices having very low resistance of power switches. The design of a new offset-free polarity detection circuit can allow further improvement of the DC-DC convertors efficiency, mainly for higher switching frequencies, as required by the new power-management platforms for e.g. wireless devices.
To address these needs, embodiments of the proposed solution rely on detecting the inversion of the coil current at the end of the NMOS conduction cycle, defining the crossing of the DCM/CCM boundary, by using a design based on dynamic current mirror and auto-zero comparator providing an offset-free and very fast polarity detection.
More particularly, a first aspect relates to a voltage polarity detection circuit adapted for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a power switch in a switched DC/DC converter, said circuit comprising:
The dynamic current mirror acts as an input memory element and a first comparator stage, whereas the auto-zero comparator acts as a fast output stage providing additional voltage gain of the voltage polarity detection circuit. As it will become apparent from reading the following description of embodiments, the proposed circuit has the further advantages of having no inherent comparison offset and of having a very high detection speed (in the order of a few nanoseconds), along with very low power consumption.
A second aspect relates to a method of detecting a voltage polarity for the detection of a Continuous Conduction Mode to Discontinuous Conduction Mode boundary of a power switch used in a switched DC-DC converter, comprising:
A third aspect relates to a DC-DC converter comprising a voltage polarity detection circuit according to the first aspect.
A fourth aspect relates to a wireless device comprising a Power Management Unit (PMU) having a DC-DC converter circuit according to the third aspect.
Embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements and in which:
Various example embodiments will now be described more fully with reference to the accompanying drawings in which some embodiments are shown. The proposed inventive concepts may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, example embodiments are provided so that this disclosure is thorough and complete and fully conveys these inventive concepts to those skilled in the art.
Referring to
Embodiments rely on the association of a dynamic current mirror (also known as “current copier”) together with a simple, i.e., low performance and low cost auto-zero comparator. In a dynamic current mirror, one and the same transistor is sequentially used at the input and the output of the mirror. Such current mirror is independent of the intrinsic and unavoidable mismatch between the at least two transistors of standard current mirrors or differential input pair, and thus has a very high accuracy. More details about dynamic current mirrors can be consulted in the book “Analogue IC Design: The Current-Mode Approach”—Chris Toumazou, F. J. Lidgey, David Haigh—1993—pp 302-303, Chapter 7.4 entitled “Principle of dynamic current mirrors”.
In the contemplated implementation, the dynamic current mirror acts as the input memory element and a first comparator stage, whereas the auto-zero comparator acts as a fast output stage providing additional voltage gain of the voltage polarity detection circuit. As it will become apparent from reading the following description of embodiments, the proposed circuit has the further advantages of having no inherent comparison offset and of having a very high detection speed (in the order of a few nanoseconds), along with very low power consumption.
As shown in
In the embodiment shown if
Embodiments of the proposed polarity detection circuit 30 used for the detection of the Direct Current Mode (DCM) of the power switch M2 comprise a dynamic current mirror and an auto-zero comparator, the combination of which provides a fast, accurate and offset-free polarity detection.
As shown in
Further, the auto-zero comparator may comprise a standard two stage Operational Amplifier (OA) whose non inverting input “+” is connected to the drain of M1, whose inverting input “−” is connected to the ground through a capacitor C2, and whose output is connected to its inverting input “−” through a fourth switch SW4. Let us call VC2 the voltage across capacitor C2, and VOUT the voltage at the output of the AO. Voltage VOUT is also the output voltage of the auto-zero comparator and, hence, the voltage at the output 32 of the polarity detection circuit 30.
In one example, switches SW1, SW2, SW3 and SW4 each comprise, for instance are implemented by, e.g., a NMOS transistor M7, M9, M5 and M12, respectively.
Switches SW1, SW3 and SW4 on one hand, and switch SW2, on the other hand, are driven by two complementary clock signals φ1 and φ2, respectively.
The operation of the circuit of
The first chronogram at top of
The operation of the polarity detection circuit 30 is cyclic, one cycle corresponding to a period of the complementary clock signals Φ1 and Φ2. A cycle is divided in two phases of operation.
A first phase of operation is defined by the time when clock signal Φ1 is active, for example at the high logical state, and control signal Φ2 is inactive, at the low logical state in such example. Conversely, the second phase of operation is defined by the time when clock signal Φ1 is inactive and control signal Φ2 is active. In view of the above convention, the first phase of operation will sometimes be referred to as phase Φ1, and the second phase of operation will be referred to as phase Φ2, in what follows.
The NMOS transistor M2 of the power stage is conductive during the first phase of operation (i.e., phase Φ1), and is blocked during the second phase of operation (i.e., phase Φ2). Stated otherwise, the first phase of operation of the polarity detection circuit corresponds to the conduction period of the power transistor M2 of the DC-DC converter. Also, the switches SW1, SW3 and SW4 are closed during the first phase of operation, and are open during the second phase of operation. Conversely, switch SW2 is open during the first phase of operation, and is closed during the second phase of operation.
During phase Φ1, the drain-source voltage VDS of the power NMOS transistor M2 is applied to the first terminal (1) of the memory capacitor C1 through the closed switch SW1. Switch SW3, being closed, configures the transistor M1 to be diode-connected. The terminal (2) of capacitor C2 on the side of switch SW3 is at the voltage gate-source voltage VGS(M1) of transistor M1, which is therefore given by:
where:
If follows that, during phase Φ1, the voltage VC1 across the capacitor C1 is given by:
V
C1
=V
GS(M1)
−V
DS(M2) (3)
where VDS(M2) is the drain-source voltage of the power transistor M2.
It will be appreciated that voltage VC1 is thus directly representative of voltage VDS(M2)(t), since the drain current ID is flowing through M1 is equal to the constant current I0 from current source 61 (ID=I0), so that voltage VGS(M1) is constant during phase Φ1. Voltage VC1 across capacitor C1 as a function of time is shown by the fifth chronogram from the top of
During this phase φ1, the auto-zero comparator, namely the Operational Amplifier OA, is configured as a voltage follower (switch SW4 being closed). Thus, the substantially constant voltage VHZ at the high-impedance node corresponding to the drain of transistor M1, is recopied to the capacitor C2 as voltage VC2. Voltage VHZ as a function of time is shown in the sixth chronogram from the top of
Let us now describe the configuration of the circuit in the second phase φ2. In phase φ2, terminal (1) of capacitor C1 on the side of switch SW2 is connected to the ground GND through closed switch SW2, and switches SW1, SW3 and SW4 are open. Whatever the polarity of the drain-source VDS of M1 voltage at the end of first phase Φ1 (noted VDS(t=TCLK) in
V
C1
=V
GS(M1) (4)
Thus, comparing above relations (3) and relation (4) at t=TCLK, gives the following changes in the gate-source voltage VGS(M1) of transistor M1:
This implies the following changes in the drain-source voltage VDS of transistor M1, as shown in the sixth chronogram from the top of
Let us now concentrate on the operation of the auto-zero comparator.
In phase φ1, the switch SW4 is closed thereby connecting the output voltage of the AO to its inverting, i.e., negative or “−” input. The AO is thus configured to operate as a voltage follower, as already stated above. Its output voltage, which thus corresponds to the VHZ voltage plus any offset value of the AO, is charged into capacitor C2.
In phase φ2, the switch SW4 is open and the AO thus operates as a comparator, whereby its output voltage is at +Vsat if VHZ>VC2, and at −Vsat if VHZ<VC2, where +Vsat and −Vsat are the positive and negative saturation voltages, respectively, of the AO, which corresponds to its high supply voltage and its low supply voltage, respectively. In one example, the high supply voltage corresponds to the battery voltage VI of the device, and the low supply voltage corresponds to the potential of the ground GND, namely 0 Volt.
To summarize, and as is illustrated by the last chronogram at the bottom of
In other words, the output signal VOUT at the output of the zero-current detector 30 is indicative of the polarity of the drain-source voltage VDS(t=TCLK) of the power transistor M2 at the end of its conduction phase φ1. Yet in other words, this output signal VOUT is representative of the result of the CCM/DCM boundary detection. Signal VOUT is used by the switch driving circuit 20 as shown in
As can be understood by the one with ordinary skills in the art, using an auto-zero comparator as described above allows removing the effect of any offset of the AO, thus achieving an offset-free comparison result.
Besides, as the input voltage variation in gate-source voltage VGS of transistor M1 from phase φ1 to phase φ2 can be very low, the voltage excursion in the VHZ node during phase φ2 can be very slow. Nevertheless, one further advantage of the association of the dynamic current mirror with an auto-zero comparator is that voltage VHZ(Φ2) is compared with voltage VHZ(Φ1) (stored in C2) by the auto-zero comparator whose output response is very fast. Therefore, as illustrated by the fifth, sixth and seventh chronograms from the top of
Further improvements of the proposed design will now be described with reference to the more elaborated schematic circuit diagram of
One key aspect of the accuracy of proposed solution as described above is to protect the capacitor voltage VC1 during the switching from phase Φ1 to phase Φ2. This is because the capacitor C1 stores the information about the compared voltage VDS of the power NMOS transistor M2 of the DC-DC converter, and it is critical not to alter this information VDS(t=TCLK) at the end of the conduction phase φ1 of the power transistor M2.
It will be noted that small amount of error current is passing through capacitor C1. This is due to the constant voltage at the plate (2) given by Eq. (2), and a small variation of the VDS(M2) during the conduction of the NMOS transistor M2. This variation is caused by the triangular shape of IL (see shape of VC(1) in the fifth graph from top of
Thus, some refinements of the basic design may be implemented, which will now be explained in more details. It will be appreciated, however, that these further embodiments may or not be implemented, either separately or in combination, in any manner suitable for the specific implementation. Stated otherwise, these further embodiments provide additional advantages but are not necessary for implementing the inventive principle of the proposed solution.
In one embodiment, for instance, provision can be made of a regulated cascode arrangement 63 for stabilising the VDS voltage of transistor M1. This solution allows preventing eventual detection errors which may be caused by the charge injection through the drain-to-gate parasitic capacitance of transistor M1.
This result may be achieved by the stabilisation of VDS voltage of M1 with the help of at least one cascode stage in the dynamic current mirror, said cascode stage comprising two additional transistors M3 and M4. The source of M3 is connected to the source of the main transistor M1, its drain being connected to the battery voltage through an additional current source 62 delivering an additional constant current IAUX, and it control gate being connected to the drain of the main transistor M1. Transistor M4 is cascaded with transistor M1, i.e. arranged in series within the drain path of transistor M1. More precisely, transistor M4 is connected by its source to the drain of transistor M1, and by its drain to the main current source 61 which delivers the main current I0, having its control gate connected to the drain of transistor M3 in the current path comprising the additional current source 62.
The stabilisation effect of this cascode arrangement is obtained at the cost of consumption of a small additional current IAUX of e.g. a few micro-amperes (μA).
In other embodiments, dummy switches may be used to prevent the “clock feed-through” effect from the clock signals. By “dummy switches”, it must be understood dummy transistors, that is to say transistors of same technology as their associated main transistor, and having their current path short-circuited, namely their drain permanently connected to their source at silicon level. In the application considered here, the gate of any dummy transistor used as dummy switch receives a control clock signal which is complementary to the clock signal received by the gate of their associated main transistor.
For example, one or two such dummy switches may be associated to the third switch SW3. For example, these dummy switches may be dummy transistors which have a size 0.5×W and 1×L, as compared with the size W and L of the main transistor M5 of switch SW3, respectively, and are provided in the current path of said main transistor M5. In the shown example, one such dummy transistor is connected on each side of transistor M5, namely on the drain side and the other on the source side of M5. The former is adapted to prevent charge injection from transistor M5 to the second capacitor C2, and the latter is adapted to prevent charge injection from transistor M5 to the first capacitor C1. To that end, these dummy transistors are each controlled by the clock signal φ2 which is complementary to the clock signal φ1 controlling the transistor M5 which implements the control switch SW3.
It shall be appreciated that, other and possibly all control switches used in the zero-current may have one or two associated dummy switches. For instance, a dummy transistor may also be associated to the transistor M12 of switch SW4, as shown in
In still other embodiments, provision can be made of a serially connected series and shunt switching arrangement 64, avoiding leakage of the inductor voltage VLX at the drain of the power NMOS transistor M2 when its body-diode is conducting.
In the shown example, such series and shunt switching arrangement is implemented at the first switch SW1. Stated otherwise, the circuit comprises a series and shunt switching arrangement associated to the first switch SW1. It may thus comprise, in addition to the serially connected transistor M7 of switch SW1 as described above, another serially connected transistor NMOS M6 which is controlled by the same clock signal φ1 as transistor M7, and a parallel connected (i.e. shunt) NMOS transistor Mg controlled by a clock signal which is complementary to φ1, for instance by the clock signal φ2.
In yet other embodiments, the clock signals φ1 and φ2 are generated by the switch driving circuit so as to be slightly non-overlapping, in order to avoid the cross-conduction current through the switches SW2 and SW3. By “non-overlapping” it must be understood that both signals are not active, i.e. for instance at the logical high state, at the same time. As shown by the three first chronograms from the top of
In further embodiments the voltage polarity detection circuit may further comprise a reference ground switching arrangement 65. This allows that that the reference ground is the power ground GND_POWER of the power stage of the DC/DC converter during the first phase of operation φ1, and is a “clean” ground GND_CLEAN, distinct from said power ground, during the second phase of operation φ2. Indeed, it is better that the reference ground of the voltage polarity detection circuit be the power ground of the power stage of the DC/DC converter during the first phase of operation φ1 because this provides a better accuracy of the copy of the drain-source voltage VDS(M2) of the power MOS transistor M2 in the first transistor C1. However, in the remaining of the time, that is to say during the second phase of operation φ2, it is better that the reference ground the voltage polarity detection circuit be distinct from the power ground of the power stage of the DC/DC converter, because the latter may vary depending on the load current and may convey various kinds of interferences.
This result may be achieved, as shown in
Finally, some embodiments may implement a dynamic bias in order to provide very low current consumption. According to such embodiments, the circuit is powered during the first phase of operation φ1 of the DC/DC converter, only until the voltage VHZ at the first input of the auto-zero comparator crosses the voltage VC2 at the second input of said auto-zero comparator, and is then turned off to save current consumption until the beginning of the next conduction cycle of the power switch M2 of the DC/DC converter, that is to say until the beginning of the next iteration of the first phase of operation φ1 of the DC/DC converter. In other words, the circuit is switched off and is placed e.g. in a sleep mode, until the beginning of the next NMOS conduction cycle.
The design presented above has a major impact on the efficiency and reliability of the DC/DC converter for e.g. mobile-phone platforms. Using such architecture can bring a significant advancement compared to existing solutions and can also find usage in similar products, such as any type of wireless devices.
The block diagram in
The device 100 as shown comprises a control unit 101 such as a processor (CPU), and a number of functional units such as, for instance, a communication unit 102 for transmitting and receiving information to and from the outside, in particular by modulating a radio frequency carrier, a memory 103 which can store information in digital form, for example a piece of music, etc. The processor 101 communicates with the functional units like 102 and 103, via a communication bus 120. Each of the CPU and the functional units is powered from the battery voltage Vbat delivered by a battery 106, through a Power Management Unit (PMU) 130.
To generate supply voltages from the battery voltage Vbat, the PMU 130 comprises at least one voltage DC/DC converter 131 of the SMPS type, for which embodiments have been described above. More than one such DC/DC converter may be provided for generating a plurality of supply voltages Vdd1, Vdd2, . . . of different values for e.g. supplying respective groups of functional units, and/or respective functional blocks thereof. The DC/DC converters may be of any one of the buck, boost or buck-boost type, as previously described with reference to
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of inventive concepts.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of inventive concepts. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural aims as well, unless the context clearly indicates otherwise.
Also; expressions such as “comprise”, “include”, “incorporate”, “contain”, “is” and “have” are to be construed in a non-exclusive manner when interpreting the description and its associated claims, namely construed to allow for other items or components which are not explicitly defined also to be present. Reference to the singular is also to be construed in be a reference to the plural and vice versa.
While there has been illustrated and described what are presently considered to be the preferred embodiments of the present invention, it will be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from the true scope of the present invention. Additionally, many modifications may be made to adapt a particular situation to the teachings of the present invention without departing from the central inventive concept described herein. Furthermore, an embodiment of the present invention may not include all of the features described above. Therefore, it is intended that the present invention not be limited to the particular embodiments disclosed, but that the invention include all embodiments falling within the scope of the appended claims.
The present invention can be implemented in hardware, software, or a combination of hardware and software. Any processor, controller, or other apparatus adapted for carrying out the functionality described herein is suitable. A typical combination of hardware and software could include a general purpose microprocessor (or controller) with a computer program that, when loaded and executed, carries out the functionality described herein.
The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which—when loaded in an information processing system—is able to carry out these methods. Computer program means or computer program in the present context mean any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language. Such a computer program can be stored on a computer or machine readable medium allowing data, instructions, messages or message packets, and other machine readable information to be read from the medium. The computer or machine readable medium may include non-volatile memory, such as ROM, Flash memory, Disk drive memory, CD-ROM, and other permanent storage. Additionally, a computer or machine readable medium may include, for example, volatile storage such as RAM, buffers, cache memory, and network circuits. Furthermore, the computer or machine readable medium may comprise computer or machine readable information in a transitory state medium such as a network link and/or a network interface, including a wired network or a wireless network, that allow a device to read such computer or machine readable information.
A person skilled in the art will readily appreciate that various parameters disclosed in the description may be modified and that various embodiments disclosed and/or claimed may be combined without departing from the scope of the invention.
It is stipulated that the reference signs in the claims do not limit the scope of the claims, but are merely inserted to enhance the legibility of the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 12306464.4 | Nov 2012 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2013/074764 | 11/26/2013 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 61735173 | Dec 2012 | US |
