Patent Application
20240430597
The present disclosure relates to a voltage ramp generator, an analog-to-digital converter and a solid-state imaging device. More particularly, the present disclosure relates to a voltage ramp generator for an analog-to-digital converter of a solid-state imaging device with high dynamic range.
Image sensors in solid-state imaging devices include photoelectric conversion elements generating a photocurrent in proportion to the received radiation intensity. A pixel circuit transforms the small photocurrent generated by the photoelectric conversion element into a voltage signal (pixel output signal) and outputs the pixel output signal on a data line (vertical signal line). A downstream ADC (analog-to-digital converter) converts the analog pixel output signal into a digital pixel value. The ADC may be a ramp compare ADC that includes a comparator and a counter. The comparator compares the pixel output voltage with a voltage ramp and outputs an active comparator signal when the voltage ramp exceeds or falls below the pixel output voltage. The counter counts events that occur at regular intervals in a count period between the start of the voltage ramp and the start of the active comparator signal. The count value at the end of the count period gives the result of the analog-to-digital conversion and defines the digital pixel value.
The data signal line is shared by a plurality of pixel circuits assigned to the same pixel column and the pixel output signals of the pixel column are output individually in a time multiplex regime. A column signal processing unit sequentially receives and processes the pixel output signals of the pixels assigned to the same pixel column.
Photoelectric conversion elements saturate when they receive too much light. Thus pixel circuits for high dynamic range solid-state imaging devices typically combine a large photoelectric conversion element and a small photoelectric conversion element. The large photoelectric conversion element has high light sensitivity but saturates at low light intensities. The small photoelectric conversion element saturates only at high light intensities but has low light sensitivity.
In a solid-state imaging device with pixel circuits combining photoelectric conversion elements with different light sensitivities, the output signals can be combined in a way that the solid-state imaging device processes the output signal of the large photoelectric conversion element for dark scenes and the output signal of the small photoelectric conversion element for bright scenes, wherein the digital pixel value for the less sensitive photoelectric conversion element is multiplied by a value (digital gain) representing the difference in sensitivity between the large photoelectric conversion element and the small photoelectric conversion element.
For example, if the sensitivity of the large photoelectric conversion element is 240 times the sensitivity of the small photoelectric conversion element, until the output of the large photoelectric conversion element is saturated, the output of the large photoelectric conversion element is adopted as the combined pixel value. In case the output of the large photoelectric conversion element saturates, the output of the small photoelectric conversion element is multiplied by the digital gain of 240, and the result of the multiplication is adopted as the combined pixel value.
The digital gain, however, degrades the resolution of the analog-to-digital conversion. Thus a relative intensity resolution (constant resolution, ConRes) at the beginning of the light intensity range covered by the small photoelectric conversion device is low. However, some applications for solid-state imaging devices such as computer vision applications require high relative intensity resolution across the entire light intensity range.
An analog-to-digital converter comparing the pixel output signal with a non-linear voltage reference signal has been proposed to mitigate shortcomings of high dynamic range pixel circuits that include two photoelectric conversion elements.
The present disclosure mitigates further shortcomings of analog-to-digital converters used for the intensity read-out of high dynamic range pixels.
To this purpose, a voltage ramp generator according to the present disclosure includes a resistor network that includes resistor elements electrically connected in series between a first supply node and a second supply node, wherein circuit nodes are formed between neighboring resistor elements. The voltage ramp generator further includes electronic switches, wherein each electronic switch is operable to connect one of the circuit nodes with a switch arrangement output. A reference voltage circuit is configured to supply a reference voltage to one of the circuit nodes.
The reference voltage circuit allows the voltage ramp generator to output a multi-part voltage ramp with sections of different slope angles also referred to as a “non-linear voltage ramp”, wherein the voltage ramp is stable to variable operating conditions and process variations during manufacturing. In addition, the voltage ramp may be programmable and reconfigurable during operation.
Further, an analog-to-digital converter according to the present disclosure includes a voltage ramp generator and a comparator circuit. The voltage ramp generator includes a resistor network including resistor elements electrically connected in series between a first supply node and a second supply node, wherein circuit nodes are formed between neighboring resistor elements. The voltage ramp generator further includes electronic switches, wherein each electronic switch is operable to connect one of the circuit nodes with a switch arrangement output. A reference voltage circuit is configured to supply a reference voltage to one of the circuit nodes. The comparator circuit is configured to compare two comparator input signals and to receive a voltage ramp signal from the switch arrangement output as one of the comparator input signals.
A solid-state imaging device according the present disclosure includes a voltage ramp generator and a comparator circuit. The voltage ramp generator includes a resistor network including resistor elements electrically connected in series between a first supply node and a second supply node, wherein circuit nodes are formed between neighboring resistor elements. The voltage ramp generator further includes electronic switches, wherein each electronic switch is operable to connect one of the circuit nodes with a switch arrangement output. A reference voltage circuit is configured to supply a reference voltage to one of the circuit nodes. The comparator circuit is configured to compare two comparator input signals and to receive a voltage ramp signal from the switch arrangement output as one of the comparator input signals.
A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments for implementing techniques of the present disclosure (also referred to as “embodiments” in the following) will be described below in detail using the drawings. The techniques of the present disclosure are not limited to the described embodiments, and various numerical values and the like in the embodiments are illustrative only. The same elements or elements with the same functions are denoted by the same reference signs. Duplicate descriptions are omitted.
Connected electronic elements may be electrically connected through a direct, permanent low-resistive connection, e.g., through a conductive line. The terms “electrically connected” and “signal-connected” may also include a connection through other electronic elements provided and suitable for permanent and/or temporary signal transmission and/or transmission of energy. For example, electronic elements may be electrically connected or signal-connected through resistors, capacitors, and electronic switches such as transistors or transistor circuits, e.g. FETs (field effect transistors), transmission gates, and others. The load path of a transistor is the controlled path of a transistor. For example, a voltage applied to a gate of a FET controls by field effect the current flow through the load path between source and drain.
Though in the following a technology for increasing dynamic range for pixel sensors is described in the context of certain types of high dynamic range image sensors for intensity readout, the technology may also be used for other types of image sensors.
The image sensor assembly 10 may include a pixel array unit 11, a row decoder 12, a pixel driver unit 13, a column signal processing unit 14, and a sensor controller 15.
The pixel array unit 11 includes a plurality of pixel circuits 100. The pixel circuit 100 may be any active pixel sensor for intensity readout with high dynamic range. In the illustrated embodiment, each pixel circuit 100 includes a first photoelectric conversion element SP1 and a second photoelectric conversion element SP2 and a number of FETs (field effect transistors) for controlling the pixel output signal of the pixel circuit 100. The first photoelectric conversion element SP1 has a higher sensitivity to electromagnetic radiation than the second photoelectric conversion element SP2.
The first photoelectric conversion devices SP1 of the pixel array unit 11 may be arranged matrix-like in columns and rows. A subset of pixel circuits 100 assigned to the same column of first photoelectric conversion devices SP1 forms a pixel column. The outputs of the pixel circuits 100 of the same pixel column are successively supplied to a data signal line (vertical signal line) VSL.
The row decoder 12 and the pixel driver unit 13 control driving of each pixel circuit 100 disposed in the pixel array unit 11. In particular, the row decoder 12 may supply control signals for selecting the pixel circuit 100 or the row of pixel circuits 100 to be driven to the pixel driver unit 13 according to an address latch signal from the sensor controller 15. The pixel driver unit 13 may control the FETs of the selected pixel circuit 100 or the FETs of the selected pixel row according to driver timing signals supplied from the sensor controller 15 and the control signals supplied from the row decoder 12.
The data signal lines VSL pass the output signals of the pixel circuits 100 (pixel output signals Vout) to the column signal processing unit 14.
The column signal processing unit 14 may include one or more ADCs (analog-to-digital converters 20. The column signal processing unit 14 may include as much ADCs 20 as the pixel array unit 11 includes data signal lines VSL. Alternatively, the number of ADCs 20 may be lower than the number of data signal lines VSL and each ADC 20 may be multiplexed between two or more of the data signal lines VSL. Each ADC 20 performs an analog-to-digital conversion of the pixel output signals successively passed from the pixel column into digital pixel values and passes digital pixel data DPXS containing the digital pixel values to the signal processing unit 80.
The sensor controller 15 controls the components of the image sensor assembly 10. For example, the sensor controller 15 may generate and pass the address latch signals to the row decoder 12, and may generate and pass driving timing signals to the pixel driver unit 13. In addition, the sensor controller 15 may generate and pass one or more control signals to the column signal processing unit 14, e.g. to the ADCs 20.
In each pixel circuit 100, each of the photoelectric conversion elements SP1, SP2 photoelectrically converts incident electromagnetic radiation into electric charges. The amount of electric charge generated in the photoelectric conversion element SP1, SP2 corresponds to the intensity of the incident electromagnetic radiation. For example, each photoelectric conversion element SP1, SP2 may include or consist of a photodiode which converts electromagnetic radiation incident on a detection surface into a detector current by means of the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation and/or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein in the intensity range of interest the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.
The first photoelectric conversion element SP1 has a higher sensitivity to light than the second photoelectric conversion element SP2. Typically, the first photoelectric conversion element SP1 is larger than the second photoelectric conversion element SP2. The sensitivity of the first photoelectric conversion element SP1 differs from the sensitivity of the second photoelectric conversion element SP2 by a sensitivity gain.
In addition to the photoelectric conversion elements SP1, SP2, the illustrated configuration example of the pixel circuit 100 includes a floating capacitor FC for storing charge supplied from the second photoelectric conversion element SP2, a floating diffusion region FD for storing charge supplied from the first photoelectric conversion element SP1 and/or the second photoelectric conversion element SP2, a first transfer transistor 101 for the first photoelectric conversion element SP1, a second transfer transistor 106 for the second photoelectric conversion element SP2, a first gate transistor 104 for the floating diffusion region FD, a second gate transistor 105 for the floating capacitor FC, a reset transistor 102, an amplification transistor 103, and a selection transistor 109. Each of the transistors is or includes an FET.
A load path of the first transfer transistor 101 is electrically connected between the cathode of the first photoelectric conversion element SP1 and the floating diffusion region FD. The first transfer transistor 101 serves as transfer element for transferring charge from the first photoelectric conversion element SP1 to the floating diffusion region FD. The floating diffusion region FD serves as temporary local charge storage. A first transfer signal TG1 is supplied to the gate (first transfer gate) of the first transfer transistor 101 through a first transfer control line. The first transfer signal TG1 has an active signal level and an inactive signal level. In response to an active first transfer signal TG1, the first transfer transistor 101 may transfer electrons photoelectrically converted by the first photoelectric conversion element SP1 to the floating diffusion region FD. A load path of the second transfer transistor 106 is electrically connected between the cathode of the second photoelectric conversion element SP2 and the floating capacitor FC. The second transfer transistor 106 serves as transfer element for transferring charge from the second photoelectric conversion element SP2 to the floating capacitor FC. The floating capacitor FC serves as temporary local charge storage. A second transfer signal TG2 is supplied to the gate (second transfer gate) of the second transfer transistor 102 through a second transfer control line. The second transfer signal TG2 has an active signal level and an inactive signal level. In response to an active second transfer signal TG2, the second transfer transistor 106 may transfer electrons photoelectrically converted by the second photoelectric conversion element SP2 to the floating capacitor FC.
A load path of the reset transistor 102 is electrically connected between a power supply line to which a positive supply voltage VDD is supplied and an auxiliary node AN. A reset signal RST is supplied to the gate of the reset transistor 102 through a reset control line. The reset signal RST has an active signal level and an inactive signal level.
A load path of the first gate transistor 104 is electrically connected between the auxiliary node AN and the floating diffusion region FD. A floating diffusion gate signal FDG is supplied to the gate of the first gate transistor 104 through a floating diffusion control line. The floating diffusion gate signal FDG has an active signal level and an inactive signal level.
A load path of the second gate transistor 105 is electrically connected between the auxiliary node AN, the floating capacitor FC and the second transfer transistor 106. A floating capacitor gate signal FCG is supplied to the gate of the second gate transistor 106 through a floating capacitor control line. The floating capacitor gate signal FCG has an active signal level and an inactive signal level.
The reset transistor 102 serves as a reset element that resets a floating diffusion potential VFD of the floating diffusion region FD and a floating capacitor potential VFC of the floating capacitor.
In particular, an active reset signal RST in combination with an active floating diffusion gate signal FDG sets the floating diffusion potential VFD equal to the positive supply voltage VDD, and an active reset signal RST in combination with an active floating capacitor gate signal FCG sets the floating capacitor potential VFC equal to the positive supply voltage VDD.
The floating diffusion region FD is connected to the gate of the amplification transistor 103 serving as an amplification element. The floating diffusion region FD functions as the input node of the amplification transistor 103.
The amplification transistor 103 and the selection transistor 109 are connected in series between the power supply line for the positive supply voltage VDD and the data signal line VSL. Thus, the amplification transistor 103 is connected to the data signal line VSL through the selection transistor 109. A select signal SEL is supplied to the gate of the selection transistor 109 through a select control line. The select signal SEL has an active signal level and an inactive signal level.
An active select signal SEL turns on the selection transistor 109. When the selection transistor 109 is turned on, the amplification transistor 103 amplifies the floating diffusion potential VFD of the floating diffusion region FD and outputs a voltage corresponding to the floating diffusion potential VFD to the data signal line VSL. The data signal line VSL passes the pixel output signal Vout from the pixel circuit 100 to the column signal processing unit 14. The charge accumulated on the floating capacitor may be transferred to the floating diffusion region FD for the read out. In particular, the first and second photoelectric conversion elements SP1, SP2 are read out successively.
Since the respective gates of the first transfer transistor 101, the second transfer transistor 106, the reset transistor 102, the first gate transistor 106, the second gate transistor 105, and the selection transistor 109 are connected in units of pixel rows, these operations may be simultaneously performed for each of the pixel circuits 100 of one pixel row.
The data signal line VSL is further connected to a constant current circuit 21. The constant current circuit 21 may include a constant current source or a switched capacitor current source supplying at least temporarily a constant current to the data signal line VSL, by way of example.
The amplifier transistor 103 of the pixel circuit 100 and the constant current circuit 21 complement to a source follower circuit passing the pixel output signal Vout derived from the floating diffusion potential VFD to the column signal processing unit 14 and the ADCs 20. The ADCs 20 transform each received pixel output signal Vout into a digital pixel value and pass digital pixel data DPXS including the digital pixel values to the signal processing unit 80.
The ADC 20 is includes a voltage ramp generator 200, a comparator 23 and a counter circuit 24. The voltage ramp generator 200 generates a voltage ramp. The comparator 23 compares the pixel output voltage VOUT with the voltage ramp and outputs an active comparator signal when the voltage ramp exceeds or falls below the pixel output voltage VOUT. The counter circuit 24 counts events that occur at regular intervals between the start of the voltage ramp and the start of the active comparator signal. The count value at the end of the count period gives the result of the analog-to-digital conversion and defines the digital pixel value for the pixel output voltage on the data signal line VSL.
The voltage ramp generator 200 includes a resistor network 210, a switch arrangement 220, and a ramp control circuit 240 configured to selectively connect different circuit nodes of the resistor network 210 to one of the inputs of the comparator 23. By sequentially connecting different circuit nodes of the resistor network 210 to the comparator input, the voltage ramp generator 200 outputs a voltage ramp. The voltage ramp generator 200 further includes one or more reference voltage circuits 230, wherein each reference voltage circuit 230 impresses a reference voltage on a circuit node of the resistor network 210. In addition, the voltage ramp generator 200 may include an output buffer circuit 250, which may be controllable. The reference voltage circuits 230 allow the voltage ramp to be divided into sections with different slope angles.
The sensor controller 15 may control at least one of the ramp control circuit 240, the output buffer circuit 250, the reference voltage circuit 230, and the counter circuit 24.
In particular, the resistor network 210 may include a number of resistor elements 211 one lower, equal to or at least one greater than a number of resolution steps of the ADC 20. For example, for an ADC 20 encoding digital values with 12 bits, the number of resistor elements 211 may be equal to 4096 or greater. All resistor elements 211 may have the same electrical resistance R.
The first and second supply nodes VDD, VSS may be electrically connected to a voltage source that may supply a temperature compensated regulated constant reference supply voltage between the first and second supply nodes VDD, VSS. Because of the regulated constant reference supply voltage between the first and second supply nodes VDD and VSS and the total number n or resistor elements 211 with electrical resistance R, the current which is flowing through the resistor network 210 is (VDD−VSS)/(n×R). Alternatively, the first and second supply nodes VDD, VSS may be electrically connected to a constant current source that may supply a temperature compensated constant reference current through the resistor network 210. Each pair of neighboring resistor elements 211 is connected through a circuit node 219.
Each electronic switch 221 may include an nFET (n channel FET), a pFET (p channel FET) or a transfer gate including FETs of different channel type with the load paths electrically connected in parallel. Each electronic switch 211 is electrically connected between one of the circuit nodes 219 and the switch arrangement output 229. The electronic switches 221 form a switch arrangement 220. The number of electronic switches 221 may be equal to the number of resolution steps of the ADC 20. For example, for an ADC 20 that encodes digital values with 12 bits, the number of electronic switches 221 may be equal to 212 (4096).
An output or the reference voltage circuit 230 is electrically connected to one of the circuit nodes 219 of the resistor network 210 and supplies a reference voltage to the circuit node 219. The reference voltage deviates from the voltage that would be reached at the circuit node 219 in the absence of the reference voltage circuit 230 by virtue of the voltage divider formed by the resistor elements 211 connected in series between the concerned circuit node 219 and the second supply node VSS. The reference voltage may be higher or lower than the voltage that would be reached at the same circuit node 219 in the absence of the reference voltage circuit 230.
The voltage ramp generator 200 based on the resistor network 210, the switch arrangement 220 and the reference voltage circuit 230 enables multi-part voltage ramps with sections having different slope angles. The number of sections with different slope angles is typically one greater than the number of circuit nodes 219 connected to the output of a reference voltage circuit 230.
Compared to digital-to-analog converters that use a current mirror and control the current using a plurality of switches electrically connected in parallel, the voltage ramp generator 200 shown in
Each further resistor element 212 and the last resistor element 211 of the resistor network closest to the low supply potential may have an electrical resistance of 2R. The further resistor elements 211 of the resistor network may have the same electrical resistance of R.
Each electronic switch 221 switches a further resistive element 212 between a fixed potential and the switch arrangement output 229. In the illustrated embodiment, the fixed potential is the low supply potential VSS. Alternatively, the fixed potential may be the high supply potential VDD. According to a further embodiment, at least one of the electronic switches 221 may switch a further resistive element 212 between one of two fixed potentials and the switch arrangement output 229 such that each electronic switch 221, some of the electronic switches 221 or at least one of them can alternatively select one of the high supply potential VDD or the low supply potential VSS to control the current amplitude through the resistor network 210.
The resistor network 210 resembles a 2-2R DAC. More than one of the electronic switches 221 can be in the on-state at the same time. The number of circuit nodes 219 and electronic switches 221 corresponds to the number of bits of the DAC. For example, the number of electronic switches is equal 12 for a 12-bit DAC. One single reference voltage circuit 230 divides the voltage ramp in a plurality of sections with two different slope angles.
In
In particular, a low-resistive ohmic path electrically connects each of the electronic switches 221 with one of the circuit nodes 219. An electric resistance of the ohmic path between the electronic switch 221 and the circuit node 219 is significantly lower than the electric resistance R of the resistor elements 211. For example, the electric resistance of the ohmic path between the electronic switch 221 and the circuit node 219 is at most 10% or at most 1% of the electric resistance R of the resistor elements 211.
The resistor network 210 is a resistor string. At most one single of the electronic switches 221 is in the on-state at each time. The number of circuit nodes 219 and electronic switches 221 corresponds to 2n, with n representing the number of bits of the DA conversion. For example, the number of electronic switches is equal 212 for a 12-bit DA conversion.
Each reference voltage circuit 230 connected to a circuit node 219 increases by one the number of voltage ramp sections of different slope angles.
In particular, the ramp control circuit 240 controls the electronic switches 221 of the switch arrangement 220 in an order such that the voltage at the switch arrangement output 229 monotonically increases or monotonically decreases.
For example, if the resistor network 210 uses binary coding as it is the case when the resistor network 210 resembles that of an R-2R based DAC, the ramp control circuit 240 may address the electronic switches 221 in a binary code, wherein the LSB (least significant bit) of the binary code addresses the circuit node 219 closest to the low supply potential VSS and the MSB (most significant bit) of the binary code addresses the circuit node 219 closest to the high supply potential VDD, or vice versa, and wherein the binary code monotonically increases by one or monotonically decreases by one with each switching. For binary-coded resistor networks 210 as illustrated in
If the resistor network 210 includes a single resistor string as illustrated in
The ramp control circuit 240 may include a shift register for addressing linear resistor networks 210 as illustrated in
That is, before an electronic switch 221 is closed, the previously closed electronic switch 221 is opened so that at any given time at most one of the electronic switches 221 is closed. In particular,
The ramp control circuit 240 may be configured to control the electronic switches at different switching rates.
In particular, the switching rates may change at the slope transition points and may be constant between neighboring slope transition points. The switching rates may be fixed or may be controllable, wherein a switching rate between two neighboring slope transition points may be changed in response to an internal event or in response to a signal supplied from a controller circuit, e.g. the sensor controller 15 of the solid-state imaging device of
In
The output buffer circuit 250 outputs a voltage ramp signal VRMP and may be effective as impedance converter to decouple circuits receiving the voltage ramp signal VRMP from the resistor network 210 and vice versa. In particular, the output buffer circuit 250 decouples voltages at the circuit nodes 219 from the impedance of the circuits receiving the voltage ramp signal VRMP. The output buffer circuit 250 may also drive the voltage ramp signal VRMP.
The output buffer circuit 250 may include an OpAmp (operational amplifier) 251 that may be in a unity gain amplifier configuration. The OpAmp 251 may be combined with a low pass circuit for smoothing the stepped voltage signal at the switch arrangement output 229.
In
In the illustrated example, the programmable gain amplifier is of the non-inverting type. In particular, the programmable gain amplifier includes an OpAmp 251, wherein the non-inverting OpAmp input is electrically connected with the switch arrangement output 229. A feedback impedance network includes a first impedance Z1 between the OpAmp output and the inverting OpAmp input and a second impedance Z2 between the inverting OpAmp input and a negative reference potential.
According to another example, the programmable gain amplifier is of the inverting type, wherein the non-inverting OpAmp input is electrically connected to a reference potential. A feedback impedance network includes a first impedance Z1 between the OpAmp output and the inverting OpAmp input and a second impedance Z2 between the inverting OpAmp input and the switch arrangement output 229.
At least one of the first impedance Z1 and the second impedance Z2 may be programmable, i.e. reconfigurable during operation of the voltage ramp generator.
According to the example shown in
A control circuit, e.g. the sensor controller 15 of the solid-state imaging device 90 as shown in
In
According to the embodiment shown in
In combination with a resistor network 210 configured as linear resistor string, each additional reference voltage circuit 230 increases by one the number of voltage ramp sections with different slope angle.
In particular,
In a solid-state imaging device as illustrated in
The noise signal corresponds to the voltage of the floating diffusion immediately after an active reset signal turns on the reset transistor 120 and connects the floating diffusion FD to the positive power supply voltage VDD.
For the AD conversion of the noise signal, the comparator of the AD converter compares the voltage ramp signal with the noise signal in a P (preset) phase. For the AD conversion of the data signal, the comparator compares the voltage ramp signal with the data signal in a D (data) phase.
According to a CDS (correlated double sampling) read-out method of a high dynamic range pixel, the P phase precedes the D phase. In a DDS (double data sampling) read-out method, the D phase precedes the P phase. For example, the CDS readout may be applied to the first photoelectric conversion element SP1, which has higher sensitivity, and the DDS readout may be applied to the second photoelectric conversion element SP2, which has lower sensitivity.
If the DDS readout is applied to the lower sensitive second photoelectric conversion element SP2, for small values at the right hand side of the voltage ramp, the relative intensity resolution is lowest.
The voltage ramp includes six sections with different slope angles, wherein the slope angle strictly monotonically decreases with time. The decreasing slope angle provides a non-constant absolute resolution but decreases the relative intensity resolution for smaller voltage values of the voltage ramp, as it is required for many applications of solid-state imaging devices with wide dynamic range, in particular in the field of computer vision, e.g. surveillance cameras and automotive cameras.
The at least one reference voltage circuit 230 may include a voltage generation circuit 231 adapted to generate a reference voltage and a buffer circuit 239 adapted to buffer the generated reference voltage. In particular, the buffer circuit 239 may decouple the voltage generation circuit 231 from the resistor network 210.
The resistance elements 233 may have different electrical resistance values. For example, the electrical resistance values of the resistance elements 233 may be integer multiples of a unit resistance R0 to provide a target reference voltage at the respective reference circuit nodes 234-1, 234-2. Alternatively, all resistance elements 233 may have the same electrical resistance value. The number of resistance elements 233 in the resistor string 232 is significantly smaller than the number n of resistor elements 211 in the resistor network 210 of
The first and second auxiliary supply nodes VDDA, VSSA may be electrically connected to a voltage source that may supply a temperature compensated regulated constant reference supply voltage between the first and second auxiliary supply nodes VDDA, VSSA. Alternatively, the first auxiliary supply node VDDA may be electrically connected with the first supply node VDD and the second auxiliary supply node VSSA may be electrically connected with the second supply node VSS. Alternatively, the first and second auxiliary supply nodes VDDA, VSSA may be electrically connected to a constant current source that may supply a temperature compensated constant reference current through the resistor string 232. Each pair of neighboring resistance elements 233 is connected through a reference circuit node 234.
Each reference voltage switch 236 may include an nFET (n channel FET), a pFET (p channel FET) or a transfer gate including FETs of different channel type with the load paths electrically connected in parallel. Each reference voltage switch 236 is electrically connected between one of the reference circuit nodes 234 and the input of the buffer circuit 239. The reference voltage switches 236 form a reference voltage switch arrangement 235. The number k of reference voltage switches 236 in the reference voltage switch arrangement 235 is significantly smaller than the number n of resistor elements 211 in the resistor network 210 of
The reference voltage generation circuit 231 may further include a voltage reference control circuit 237 that controls the reference voltage switches 236 of the reference voltage switch arrangement 235, wherein the voltage reference control circuit 237 closes no more than one of the electronic switches 236 of the reference voltage switch arrangement 235 at a time.
That is, before any of the reference voltage switches 236 is closed, each previously closed reference voltage switch 236 is opened so that at any given time at most one of the reference voltage switches 236 is closed.
A control circuit, e.g. the sensor controller 15 of a solid-state imaging device 90 as shown in
The reference voltage circuit 230 may include a bandgap reference circuit 238 configured to supply an auxiliary reference voltage VBGR to one of the reference circuit nodes 234.
In particular, the bandgap reference circuit 238 may be electrically connected to one of the reference circuit nodes 234. The bandgap reference circuit 238 generates and drives a constant voltage regardless of power supply variations, temperature changes, or circuit loading. The bandgap reference circuit 238 may include a bandgap voltage diode with or without output buffer or a Brokaw bandgap reference circuit, by way of example. The auxiliary reference voltage VBGR may be around 1.25 V.
In particular, the different reference voltage circuits 230 of the voltage ramp generator 200 of
The controllable voltage range of the reference voltage circuit 230 depends on which of the reference circuit nodes 234-1, 234-2, . . . , 234-k the bandgap reference circuit 238 is connected to.
In response to an internal or external event, the voltage reference control circuit 237 may control the reference voltage switches 236 such that only the first reference circuit node 234-1 is closed. The reference voltage circuit 230 supplies a raised first reference voltage V1↑ to the resistor network circuit node 219 to which the topmost reference voltage circuit 230 is connected. The voltage ramp signal 290 is raised on both sides of the first slope transition point at t=t1 as indicated by reference sign 293.
In response to another internal or external event, the voltage reference control circuit 237 may control the reference voltage switches 236 such that only the k-th reference circuit node 234-k is closed. The reference voltage circuit 230 supplies a lowered first reference voltage V1↓ to the resistor network circuit node 219 to which the topmost reference voltage circuit 230 is connected. The voltage ramp signal 290 is lowered on both sides of the first slope transition point at t=t1 as indicated by reference sign 294.
In particular, the analog-to-digital converter 20 includes a voltage ramp generator 200 with a resistor network 210 that includes resistor elements 211 electrically connected in series between a first supply node VDD and a second supply node VSS, wherein circuit nodes 219 are formed between neighboring resistor elements 211. The voltage ramp generator 200 further includes electronic switches 221, wherein each electronic switch 221 is operable to connect one of the circuit nodes 219 with a switch arrangement output 229, and a reference voltage circuit 230 that supplies a reference voltage VREF to one of the circuit nodes 219. The analog-to-digital converter 20 further includes a comparator circuit 23 that compares two comparator input signals and that receives a voltage ramp signal from the switch arrangement output 229 as one of the comparator input signals.
The voltage ramp signal includes slope transition points at which the slope of the voltage ramp signal changes. The voltage of each slope transition is marked by one of the reference voltages supplied from the reference voltage circuits 230 and the point of time at which the circuit node 219 to which the respective reference voltage is applied, is connected to the reference input of the comparator 23.
The reference voltage circuit 230 may include a resistor string 232 and reference voltage switches 236. The resistor string 232 includes resistance elements 233 electrically connected in series between a first auxiliary supply node VDDA and a second auxiliary supply node VSSA. Reference circuit nodes 234 are formed between electrically neighboring resistance elements 233. Each reference voltage switch 236 is operable to signal-connect one of the reference circuit nodes 234 to a circuit node 219 of the resistor network 210, either directly or through a buffer circuit 239.
The reference voltage circuit 230 may further include a voltage reference control circuit 237 that controls the reference voltage switches 236 of the reference voltage switch arrangement 235, wherein the voltage reference control circuit 237 closes no more than one of the electronic switches 236 of the reference voltage switch arrangement 235 at a time.
A control circuit, e.g. the sensor controller 15 of the solid-state imaging device 90 as shown in
In addition, the control circuit, e.g. the sensor controller 15 of the solid-state imaging device 90 as shown in
The analog-to-digital converter 20 of the solid-state imaging device 90 in
In
For the voltage ramp 295 the switching rate between the start of the voltage ramp and the first slope transition point is lower than for the voltage ramp 292. The slope of the voltage ramp 295 is less steep and the voltage ramp 295 reaches the first reference voltage V1 at t=t1→after t1. In the illustrated embodiment, the switching rate between the first slope transition point and the second slope transition point is higher than for the voltage ramp 292. Since the slope of the voltage ramp 296 is steeper the voltage ramp 296 can reach the second reference voltage V2 at the same time t=t2 as the voltage ramp 292. Basically, the switching rate between the other slope transition points remains unaffected from a change of the switching rate between two slope transition points.
For the voltage ramp 296 the switching rate between the start of the voltage ramp and the first slope transition point is higher than for the voltage ramp 292. The slope of the voltage ramp 296 is steeper and the voltage ramp 296 reaches the first reference voltage V1 at t=←t1 prior to t1. In the illustrated embodiment, the switching rate between the first slope transition point and the second slope transition point is lower than for the voltage ramp 292. Since the slope of the voltage ramp 296 is less steep between the first slope transition point and the second slope transition point, the voltage ramp 296 can reach the second reference voltage V2 at the same time t=t2 as the voltage ramp 292. Basically, the switching rate between the other slope transition points is not necessarily affected by the change of the switching rate between two slope transition points.
The solid-state imaging device 23020 has the laminated structure of a first chip (upper chip) 910 and a second chip (lower chip) 920. The laminated first and second chips 910, 920 may be electrically connected to each other through TC(S)Vs (Through Contact (Silicon) Vias) formed in the first chip 910. The solid-state imaging device 23020 may be formed to have the laminated structure in such a manner that the first and second chips 910 and 920 are bonded together at wafer level and cut out by dicing.
In the laminated structure of the upper and lower two chips, the first chip 910 may be an analog chip (sensor chip) including at least one analog component of each pixel circuit, e.g., the photoelectric conversion elements arranged in array form.
For example, the first chip 910 may include only the photoelectric conversion elements of the pixel circuits as described above with reference to the preceding FIGS. Alternatively, the first chip 910 may include further elements of each pixel circuit. For example, the first chip 910 may include, in addition to the photoelectric conversion elements, at least the transfer transistor, the reset transistor, the amplifier transistor, and/or the selection transistor of the pixel circuits. Alternatively, the first chip 910 may include each element of the pixel circuit.
The second chip 920 may be mainly a logic chip (digital chip) that includes the elements complementing the elements on the first chip 910 to complete pixel circuits and current control circuits. The second chip 920 may also include analog circuits, for example circuits that quantize analog signals transferred from the first chip 910 through the TCVs. For example, the second chip 920 may include all or at least some of the components of the row driver assembly.
The second chip 920 may have one or more bonding pads BPD and the first chip 910 may have openings OPN for use in wire-bonding to the second chip 920. The solid-state imaging device 23020 with the laminated structure of the two chips 910, 920 may have the following characteristic configuration:
The electrical connection between the first chip 910 and the second chip 920 is performed through, for example, the TCVs. The TCVs may be arranged at chip ends or between a pad region and a circuit region. The TCVs for transmitting control signals and supplying power may be mainly concentrated at, for example, the four corners of the solid-state imaging device 23020, by which a signal wiring area of the first chip 910 can be reduced.
The technology according to the present disclosure may be realized in a light receiving device mounted in a mobile body of any type such as automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, or robot.
The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example depicted in
The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.
The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.
The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 imaging an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.
The imaging section 12031 may be or may include an image sensor that includes an ADC with a voltage ramp generator according to the embodiments of the present disclosure. The light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.
The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle and may be or may include a solid-state imaging device with a raw driver assembly according to the embodiments of the present disclosure. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that includes the solid-state imaging device and that is focused on the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.
The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.
In addition, the microcomputer 12051 can perform cooperative control intended for automatic driving, which makes the vehicle to travel autonomously without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.
In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.
The sound/image output section 12052 transmits an output signal of at least one of a sound or an image to an output device capable of visually or audible notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of
The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, side-view mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the side view mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.
Incidentally,
At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, imaging element having pixels for phase difference detection or may include a ToF module including a high dynamic range image sensor that includes an ADC with a voltage ramp generator according to the present disclosure.
For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km/hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automatic driving that makes the vehicle travel autonomously without depending on the operation of the driver or the like.
For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.
At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound/image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound/image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.
The example of the vehicle control system to which the technology according to an embodiment of the present disclosure is applicable has been described above. By applying an image sensor that includes an ADC with a voltage ramp generator according to the present disclosure, the results of image recognition can be more reliable. For example, recognition of pedestrians can be performed on more reliable pixel information. A faulty image sensor can be reliably detected and reported to a higher instance.
Additionally, embodiments of the present technology are not limited to the above-described embodiments, but various changes can be made within the scope of the present technology without departing from the gist of the present technology.
A solid-state imaging device including an image sensor that includes an ADC with a voltage ramp generator circuit according to the present disclosure may be any device used for analyzing and/or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, the solid-state imaging device may be any electronic device in the field of traffic, the field of home appliances, the field of medical and healthcare, the field of security, the field of beauty, the field of sports, the field of agriculture, the field of image reproduction or the like.
Specifically, in the field of image reproduction, the solid-state imaging device may be a device for capturing an image to be provided for appreciation, such as a digital camera, a smart phone, or a mobile phone device having a camera function. In the field of traffic, for example, the solid-state imaging device may be integrated in an in-vehicle sensor that captures the front, rear, peripheries, an interior of the vehicle, etc. for safe driving such as automatic stop, recognition of a state of a driver, or the like, in a monitoring camera that monitors traveling vehicles and roads, or in a distance measuring sensor that measures a distance between vehicles or the like.
In the field of home appliances, the solid-state imaging device may be integrated in any type of sensor that can be used in devices provided for home appliances such as TV receivers, refrigerators, and air conditioners to capture gestures of users and perform device operations according to the gestures. Accordingly the solid-state imaging device may be integrated in home appliances such as TV receivers, refrigerators, and air conditioners and/or in devices controlling the home appliances. Furthermore, in the field of medical and healthcare, the solid-state imaging device may be integrated in any type of sensor, e.g. a solid-state image device, provided for use in medical and healthcare, such as an endoscope or a device that performs angiography by receiving infrared light.
In the field of security, the solid-state imaging device can be integrated in a device provided for use in security, such as a monitoring camera for crime prevention or a camera for person authentication use. Furthermore, in the field of beauty, the solid-state imaging device can be used in a device provided for use in beauty, such as a skin measuring instrument that captures skin or a microscope that captures a probe. In the field of sports, the solid-state imaging device can be integrated in a device provided for use in sports, such as an action camera or a wearable camera for sport use or the like. Furthermore, in the field of agriculture, the solid-state imaging device can be used in a device provided for use in agriculture, such as a camera for monitoring the condition of fields and crops.
The present technology can also be configured as described below:
| Number | Date | Country | Kind |
|---|---|---|---|
| 21210202.4 | Nov 2021 | EP | regional |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2022/081992 | 11/15/2022 | WO |
