VOLTAGE REFERENCE CIRCUIT AND CURRENT REFERENCE CIRCUIT USING VERTICAL BIPOLAR JUNCTION TRANSISTOR IMPLEMENTED BY DEEP N-WELL CMOS PROCESS

Information

  • Patent Application
  • 20070182478
  • Publication Number
    20070182478
  • Date Filed
    December 08, 2006
    17 years ago
  • Date Published
    August 09, 2007
    16 years ago
Abstract
A voltage reference circuit and a current reference circuit using a vertical bipolar junction transistor (BJT) implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process, wherein the voltage reference circuit generates a constant reference voltage regardless of temperature and includes an amplifier element having a positive input terminal and a negative input terminal, a first transistor, and a second transistor. The first transistor is electrically connected to the positive input terminal and the second transistor is electrically connected to the negative input terminal. Each of the first and second transistors is a vertical BJT implemented by a deep N-well CMOS process, and the reference voltage is calculated by adding a base-emitter voltage of one of the first and second transistors to a value obtained by multiplying a thermal voltage by a predetermined factor. Accordingly, circuits having better reproducibility, uniformity, and device matching than circuits that use a lateral NPN/PNP device or substrate NPN/PNP device manufactured using a CMOS process are provided.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be understood in more detail from the following descriptions taken in conjunction with the attached drawings in which;



FIGS. 1A through 2 illustrate examples of a conventional bipolar junction transistor (BJT) device implemented by a complementary metal-oxide semiconductor (CMOS) process.



FIG. 3 is a cross-sectional view of a vertical NPN BJT implemented by a deep N-well CMOS process, according to an exemplary embodiment of the present invention;



FIG. 4 is a cross-sectional view of a vertical NPN BJT implemented by a deep N-well CMOS process, according to an exemplary embodiment of the present invention;



FIG. 5 is a diagram of a bandgap voltage reference circuit according to an exemplary embodiment of the present invention;



FIG. 6 is a diagram of a bandgap voltage reference circuit according to an exemplary embodiment of the present invention; and



FIG. 7 is a diagram of a current reference circuit according to an exemplary embodiment of the present invention.


Claims
  • 1. A voltage reference circuit for generating a constant reference voltage comprising: an amplifier element having a positive input terminal and a negative input terminal;a first transistor electrically connected to the positive input terminal; anda second transistor electrically connected to the negative input terminal,wherein each of the first and second transistors is a vertical bipolar junction transistor implemented by a deep N-welt complementary metal-oxide semiconductor (CMOS) process, and the reference voltage is calculated by adding a base-emitter voltage of one of the first and second transistors to a value obtained by multiplying a thermal voltage by a predetermined factor.
  • 2. The voltage reference circuit of claim 1, further comprising: a first resistor element connected between the positive input terminal and an output node of the amplifier element: anda second resistor element connected between the negative input terminal and the output node of the amplifier element.
  • 3. The voltage reference circuit of claim 2, wherein the first transistor has a base and a collector connected to each other, and the second transistor has a base and a collector connected to each other and connected to the negative input terminal through a third resistor element.
  • 4. The voltage reference circuit of claim 3 wherein the predetermined factor is a function of a resistance value of the second resistor element, a resistance value of the third resistor element and a ratio of an emitter size of the second transistor to an emitter size of the first transistor.
  • 5. The voltage reference circuit of claim 1, wherein bases of the respective first and second transistors are commonly connected to an output node of the amplifier element, and the second transistor is connected to a node having a predetermined voltage through a first resistor element.
  • 6. The voltage reference circuit of claim 1, wherein the deep N-well CMOS process comprises a P-base process.
  • 7. A current reference circuit for generating a reference current proportional to temperature, the current reference circuit comprising: an amplifier element having a positive input terminal and a negative input terminal;a first transistor connected between a first node and one of the positive input terminal and the negative input terminal;a second transistor connected between a second node and the other of the positive input terminal and the negative input terminals; andan output unit outputting the reference current in response to an output voltage of the amplifier element,wherein each of the first and second transistors is a vertical bipolar junction transistor implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process, and the reference current is calculated by multiplying a thermal voltage by a predetermined factor.
  • 8. The current reference circuit of claim 7, wherein the output unit comprises: a third transistor having a first terminal connected to an output node of the amplifier element, a second terminal connected to the positive input terminal, and a third terminal connected to a common node,a fourth transistor having a first terminal connected to the output node of the amplifier element, a second terminal connected to the negative input terminal, and a third terminal connected to the common node; anda fifth transistor having a first terminal connected to the output node of the amplifier element and a second terminal connected to the common node to output the reference current.
  • 9. The current reference circuit of claim 7, wherein the deep N-well CMOS process comprises a P-base process.
Priority Claims (1)
Number Date Country Kind
10-2006-0011310 Feb 2006 KR national