Patent Application
20150323950
The present disclosure relates to a method and apparatus for generating a voltage reference. More particularly the present disclosure relates to a methodology and circuitry configured to provide an output signal that combines a proportional to absolute temperature component with a complimentary to absolute temperature component to generate a stable output which is not temperature dependent.
It is well known that temperature affects the performance of electrical circuitry and it is important to provide circuitry which provides an output which is not dependent on temperature fluctuations, i.e. a voltage reference. It will be appreciated that a voltage reference can be converted to current reference and for the sake of the following explanation the present teaching will be described with reference to the provision of a voltage reference at the output of the circuit but it will be understood that the present teaching should be construed as limited to such a voltage reference.
In the context of providing voltage references, it is known to use a band-gap type voltage reference which is based on a summation of two voltage components having opposite and balanced Temperature Coefficients (TCs). Usually, the first voltage component is related to a base-emitter voltage of a bipolar transistor which inherently has a form which is Complementary To Absolute Temperature, denoted as a CTAT voltage. The second voltage component is obtained from the base-emitter voltage difference, ΔVBE, of two bipolar transistors operating at different collector current densities. This voltage is Proportional To Absolute Temperature and it is denoted a PTAT voltage. Very often the base-emitter voltage difference is reflected over a resistor generating a corresponding PTAT current. With a second resistor of the same type (same TC) the base-emitter voltage difference is gained to the desired level to balance the CTAT voltage component.
A real voltage reference is affected by many errors such as temperature drift or temperature coefficient (TC). Such a variation in response with respect to operating temperature may be considered a first order variation but it is also possible for resultant errors to have a contribution from higher order error components. Such higher order errors can be very well approximated by a parabolic or second order form versus absolute temperature. To compensate for these errors there is always a need for a trimming circuit and a method to guarantee the target specifications independent of how the circuit is designed or its architecture.
In summary, there is a continuous need for circuits that can provide an accurate reference circuit.
These and other problems are addressed by a voltage reference circuit provided in accordance with the present teaching. By judiciously combining circuit elements it is possible to generate a voltage or a current at an output node of the circuit that is temperature independent. The circuit elements include a first set of components that are configured relative to one another to provide an output of the form proportional to absolute temperature, PTAT. Desirably this first set of components comprises bipolar transistors and the components are configured to generate a signal that is proportional to a differential in base emitter voltages of two bipolar transistors, ΔVBE.
A second set of components are coupled to this first set of components. The second set of components operably provides an output that is complimentary to absolute temperature, CTAT, in form.
The present teaching provides for a coupling of the first and second set of components in a manner whereby a trimming of the second set of components at a single temperature can be used to compensate for errors introduced by process parameters and mismatch. As the first set of circuit components generates an output that is self-referencing, the PTAT is generated by a ratio of internal circuit components, this single trimming step is sufficient to provide a voltage reference at the output of the circuit that is, to a first order, temperature insensitive.
Embodiments which are provided to assist with an understanding of the present teaching will now be described, by way of example, with reference to the accompanying drawings, in which:
a is a schematic showing components of an illustrative circuit provided in accordance with the present teaching;
b is a schematic showing components of an illustrative circuit provided in accordance with the present teaching;
c is a schematic showing components of an illustrative circuit provided in accordance with the present teaching;
a is a schematic showing detail of circuit components configured to generate a PTAT output in accordance with the present teaching;
b is a schematic showing detail of circuit components configured to generate a PTAT output in accordance with the present teaching;
a and
The present teaching provides a reference circuit that combines the output from a first set of circuit elements with the output from a second set of circuit elements. The first set of circuit elements provides at least one proportional to absolute temperature, PTAT, cell which is configured to generate a voltage that is temperature dependent and specifically will increase with increased ambient temperature. The second set of circuit elements provides at least one complimentary to absolute temperature, CTAT, cell which is configured to generate a voltage that is temperature dependent and specifically will decrease with increased ambient temperature. By combining the PTAT and CTAT voltages from the first and second set of circuit elements the overall output of the circuit may be provided having no temperature sensitivities, i.e. it neither increases nor decreases with changes in ambient temperature. In this way the circuit provides a voltage reference.
The present teaching will now be described with reference to exemplary arrangements. The exact implementation of a circuit per the present teaching may vary but the variances share a common architecture whereby, when making adjustments which are necessary as part of a trimming or calibration regime, the set of circuit elements that provide the PTAT component of the circuit are not altered. A basic block structure of an architecture that may be employed within the context of the present teaching is shown in each of
The circuit of
As was mentioned above, a circuit provided in accordance with the present teaching couples a PTAT component with a CTAT component in order to generate a temperature independent voltage, Vref. As will be described in more detail below, the circuit is configured such that the PTAT component is provided by a first set of circuit components configured to generate a proportional to absolute temperature, PTAT, signal that is dependent on a base emitter voltage difference between first and second bipolar transistors operating at different current densities. This PTAT signal could be a voltage or a current signal. The CTAT component is provided by a second set of circuit components configured to generate a complimentary to absolute temperature, CTAT, signal which again could be a CTAT current or voltage. By arranging the PTAT component with the CTAT component it is possible to couple the CTAT signal component to the PTAT signal to provide at an output of the circuit an output voltage that is first order temperature insensitive. This coupling is typically provided by arranging the PTAT and CTAT components in a bridge configuration. Within the context of the present teaching the term “bridge configuration” is intended to define first and second legs of a circuit that are arranged relative to a shared tapping point such that changes in either of the two legs affects the signal at the shared tapping point. The PTAT component defines a first leg and the CTAT component defines a second leg, the shared tapping point being Vref, the output of the circuit.
By providing the PTAT and CTAT components in a bridge configuration the PTAT component can provide an internal reference for the circuit. Furthermore, use of the CTAT component alone can be sufficient to provide a calibration of the circuit. This calibration can be done by judiciously selecting the values of the circuit components that are used in the CTAT leg a priori to circuit manufacture. In this way, the value of the CTAT component is hard coded or hard wired into the circuit. In another configuration it is possible to trim or otherwise tune the value provided by circuit components of the CTAT component to vary its contribution to the overall sensed signal at the shared tapping point.
If the circuit is designed such that the PTAT component will not be varied as part of a trimming exercise to provide the desired voltage reference then the only circuit elements that may be varied are those that provide the second voltage component, VCTAT. As the two voltage components, VPTAT and VCTAT, have opposite temperature variations, i.e. different slopes vs. temperature, the two resistors, RPTAT and RCTAT can be arranged such that, at the common node Vref, the voltage is first order temperature independent. In other arrangements, the value of the RPTAT and RCTAT resistors can be chosen carefully based on anticipated operating conditions of the circuit. In this way the adjustment can be performed directly on the CTAT component of the circuit which will mostly vary the temperature coefficient of the output voltage. In the event that the absolute value of the output voltage needs to be changed or the trimming range of the CTAT component needs to be adjusted, then the tapping point which provides the output voltage of the circuit and is located between the RPTAT and RCTAT resistors can be moved.
In a similar fashion a temperature independent voltage can be generated based on the block schematics of
Similarly, a CTAT voltage can be combined with a PTAT current. Such a circuit is shown in
Per the present teaching, the PTAT cell is used as an internal reference with the result being that other circuit elements of the circuit are referenced relative to the PTAT cell. In this way adjustments to the circuit output are achieved by varying other circuit elements of the circuit—be that the CTAT voltage reference cell or the resistors.
A CTAT cell typically provides an output that is based on the base emitter voltage of a bipolar transistor and can therefore be considered a voltage that is very much process dependent and also sensitive to mismatches. It also has a quite significant non-linear variation vs. temperature, very often of the form of T log T, where T denotes absolute temperature. By focusing on a trimming or other modification of the circuit elements that form this CTAT cell it is possible to compensate for these variances. At the same time the circuit elements that are used to provide the PTAT voltage cell can be selected based on their precision and independence to variance.
a shows an example of such a precise and process independent PTAT voltage generator which can be usefully employed as a PTAT cell within the context of the voltage reference of the present teaching. The architecture of this PTAT cell is similar in form to that described in U.S. Pat. Nos. 8,228,052 and 8,531,169, the content of each of with is incorporated by way of reference.
In the circuit of
where
b shows another circuit that could be used in the context of the present teaching to provide the PTAT leg. The difference between the two structures consists of the method of providing the base current for the top pair of bipolar transistors, will and qn21. Transistor mn4 is used to generate the base currents of will and qn21. A transistor connected in this configuration is usually called a “beta-helper”. The other two NMOS transistors mn3 and mn5 are used to balance the base-collector voltages of will and qn21, thus minimizing the effect of the so called direct Early voltage. The Early effect generates a second order error in the base-emitter voltage. The trade-off between the structures presented in
Based on headroom limitation, a corresponding number of the cells according to
An exemplary schematic of circuit elements that could be provided in a curvature correction cell, Vcv, in accordance with the present teaching is shown in
The overall correction to the curvature is based on an understanding that the nonlinearity of the base-emitter voltage versus temperature is dependent of the slope of the bias current as can be seen in Eq. 2:
where
If the high collector current density arm of the correction circuit is biased with PTAT current and the low collector current density arm is biased with constant current from each pair of bipolar transistors, the expression of the base-emitter voltage presented in equation (1) has an additional term:
By trimming the ratio of PTAT to CTAT in the combined current source, I02, the second term in equation (3) is adjusted, such that the nonlinear term of the base-emitter voltage in equation (2) is cancelled and the compound VCTAT voltage has only linear variation versus temperature. It will be appreciated that where employed such logarithmic temperature coefficient or curvature correction is typically done prior to determination of the optimum settings for temperature coefficient correction.
The output voltage of the circuit in
The ratio RPTAT/RCTAT can be trimmed by choosing an adjustable tapping point on the resistor string implementing RPTAT+RCTAT where the output voltage is collected.
It will be apparent that the circuits presented in
Using circuits provided per the teaching of
The VCTAT component generator was implemented using a topology similar to that described above with reference to
A circuit per the implementation of
Using circuits per the present teaching it is possible to provide for trimming at a single temperature. It is also possible to provide for trimming at two or more temperatures which may be advantageously employed for more accurate applications. Using an architecture such as that provided in accordance with the present teaching it is possible to provide flexibility in trading performance for manufacturing cost—it will be appreciated that trimming at multiple temperatures will require additional calibration as additional temperature passes are required. It will be understood that dual temperature trim will be better in the form of accuracy, but the differences between dual and single temperature trims is by far not as large as in traditional architectures.
Using a dual temperature process, as a first step the device under test, DUT, is forced to temperature T1 and evaluated. The DUT is then forced to a second temperature T2 and evaluated again. Using the results from these two evaluations it is then possible to determine the value of the output voltage at which the temperature coefficient is a minimum.
By trimming at two different temperatures the accuracy of the circuit output can be improved. The maximum observed temperature coefficient of VOUT was 3.7 ppm/° C. in the −40→125° C. temperature range.
From the above it will be appreciated that the present teaching provides a number of variations on a technique which combines a PTAT and a CTAT cell to provide a voltage reference at an output of the circuit. The circuit uses the PTAT cell to provide an internal voltage reference whose accuracy is provided by the fact that the PTAT component is generated by a differential between two components or elements of the cell which inherently compensate for variations in each other. The output PTAT voltage from the PTAT cell, which is of a form of a proportional to absolute temperature voltage, is very consistent with reduced variability due to process changes and mismatch. If provided in a stack arrangement individual base emitter differentials from each of the cells may be stacked to increase the overall value of the contributing PTAT component without increasing the error. This stacked larger output voltage can then be combined with a CTAT component to remove any temperature dependent effects and provide a voltage reference having, to at least a first order, temperature insensitivities.
Any trimming that is required to the output is effected using the elements that do not contribute to the PTAT cell. The output of the circuit can be modified using trimming techniques that may be implemented in the simplest form by trimming a first set, or indeed multiple sets, of components at a first temperature. By providing trimming at multiple temperatures it is possible to improve the accuracy of the circuit.
It will be appreciated that circuits provided in accordance with the present teaching provide a number of advantages including:
High precision in both absolute value and temperature coefficient;
low noise;
operates in low headroom environment;
operates in low power environments; and
can be implemented using less silicon than required for conventional or known arrangements; and
depending on the required precision, the circuit might be trimmed at one or two temperatures.
It is however not intended to limit the present teaching to any one set of advantages or features as modifications can be made without departing from the spirit and or scope of the present teaching.
The systems, apparatus, and methods of providing a temperature independent voltage output are described above with reference to certain embodiments. By judiciously combining circuit elements into two or more cells it is possible to use a PTAT component as an internal reference for the overall circuit and modify the output by providing a trimming of a CTAT component. In this way the inherent accurate form of the PTAT component is maintained and the CTAT component is trimmed.
A skilled artisan will, however, appreciate that the principles and advantages of the embodiments can be used for any other systems, apparatus, or methods with a need for a temperature sensitive output.
For example while described with reference to a voltage output, the present teaching may equally be considered suitable for providing a current reference. Using known methodologies it will be appreciated that a PTAT voltage can be changed to a PTAT current should the need arise. For example, a PTAT current can be generated by replicating across a resistor a base-emitter voltage difference of two bipolar transistors operating at different collector current densities. When low current in a small silicon area is to be generated, a MOS transistor operating in its triode region can be used. It will be appreciated that the “on” resistance of a MOS transistor operating in triode region is not well controlled such that if accuracy is required then a use of resistors is preferred.
Additionally, while the base-emitter voltages have been described with reference to the use of specific types of bipolar transistors any other suitable transistor or transistors capable of providing base-emitter voltages could equally be used within the context of the present teaching. It is envisaged that each single described transistor may be implemented as a plurality of transistors the base-emitters of which would be connected in parallel. It will be further appreciated that transistors described herein have all 3 terminals available and as modern CMOS processes have deep N-well capabilities it is possible to use these processes fabricate low quality, but functional vertical npn bipolar transistors.
Such systems, apparatus, and/or methods can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, wireless communications infrastructure, etc. Examples of the electronic devices can also include circuits of optical networks or other communication networks, and disk driver circuits. The consumer electronic products can include, but are not limited to, measurement instruments, medical devices, wireless devices, a mobile phone (for example, a smart phone), cellular base stations, a telephone, a television, a computer monitor, a computer, a hand-held computer, a tablet computer, a personal digital assistant (PDA), a microwave, a refrigerator, a stereo system, a cassette recorder or player, a DVD player, a CD player, a digital video recorder (DVR), a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi-functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device can include unfinished products.
Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The words “coupled” or “connected”, as generally used herein, refer to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words using the singular or plural number may also include the plural or singular number, respectively. The words “or” in reference to a list of two or more items, is intended to cover all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. All numerical values provided herein are intended to include similar values within a measurement error.
The teachings of the inventions provided herein can be applied to other systems, not necessarily the circuits described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. The act of the methods discussed herein can be performed in any order as appropriate. Moreover, the acts of the methods discussed herein can be performed serially or in parallel, as appropriate.
While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and circuits described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and circuits described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. Accordingly, the scope of the present inventions is defined by reference to the claims.
