Patent Application
20200310482
Voltage references are key building blocks for most analog and digital circuits and systems. They are used extensively in voltage regulators, analog-to-digital converters and bias circuitry. Cutting edge complementary metal oxide semiconductor (CMOS) technology has paved the way for a new era of low power applications and opportunities (e.g., internet-of-things (IoT), sensor networks and interfaces, energy harvesting, wireless charging, brain-machine interface, low power actuators, etc.).
Most modern CMOS processes use a supply voltage of ˜1V or lower owing to device geometries. Consequently, conventional bandgap references require separate supply voltage domains due to reduced voltage headroom. In contrast, threshold voltage has not scaled much with feature size reduction. Hence, there is a growing demand for ultra-low power voltage references capable of providing an output comparable to the threshold voltage that can be powered with sub-1V supply voltages.
Traditional approaches to designing voltage references involve bipolar junction transistors (BJT), where two linearly temperature variant voltages and/or currents are generated. The positive and the negative temperature dependent slopes cancel out when combined to generate a temperature independent voltage reference. However, most BJT based approaches are power hungry (>1 μW) and they also require higher supply voltages as the devices operate in forward active region. Another popular approach is to use feedback amplifiers and large resistors for error correction, which limits the minimum supply voltage and minimum power consumption, as each device requires voltage headroom to be in saturation.
Recent trends in designing voltage references use metal oxide semiconductor (MOS) devices in the sub-threshold region. This facilitates device operation with very low voltage headroom. Moreover, it helps to reduce power consumption by 4 to 5 orders of magnitude. Recent works have reported sub-nanowatt power consumption with excellent temperature coefficients (TC) and line sensitivities (LS) with the ability to operate below 1V. Two-transistor (2T) based voltage references offer excellent performance but the output reference voltage (175.3 mV) is often too low compared to the threshold voltage of the devices in modern CMOS. A cascaded 4T reference boosts the output voltage (343 mV) but it does not offer a good temperature-coefficient (33 ppm/° C.). In addition, the minimum supply voltage that can be used is 0.5 V because the devices require a 3˜4VT voltage headroom in order to minimize non-linear temperature dependency.
There is a growing demand for ultra-low power voltage references with good TC and LS that generates output voltages that can be fed to external circuitry without level shifting. It is also desirable to push the supply voltage as low as possible so that it can be powered by wireless power transfer or energy scavenging (e.g., RF, TEG, solar, etc.).
Typically, power amplifiers are used to increase the output voltage (VREF) of voltage references. In one or more embodiments, instead of using a power amplifier, a voltage reference circuit (e.g., a main stage) is coupled to a bulk feedback circuit to increase the output voltage and to reduce the temperature coefficient (e.g., reduce the temperature dependence of VREF).
In one or more embodiments, the bulk-feedback circuit includes two auxiliary stages (M3-M4 and M5-M6). The bulk-feedback circuit may boost the output voltage of VREF without using typical cascode topology. Including two stages may improve temperature performance.
The temperature gradient in the voltage reference circuit from low voltage operation may be compensated with replica paths. Depending on the complementary-to-absolute-temperature (CTAT) or proportional-to-absolute temperature circuit (PTAT) nature of temperature gradient of the main stage, the feedback circuit can be designed to control the bulk voltage of the main stage using a replica stage that may be optimized to provide an opposing operation. If the main stage has a PTAT (CTAT) response, the feedback (e.g., auxiliary) stages may be designed to provide PTAT (CTAT) responses. This is because increasing (decreasing) the bulk voltage increases (decreases) the threshold voltage, which may compensate for temperature dependent reduction in the output reference voltage. In short, the concept is to use a temperature dependent voltage source (CTAT/PTAT) to control the threshold voltage to compensate for the temperature dependency of the reference.
In some embodiments, transistors may be metal-oxide-semiconductor field-effect transistors (MOSFETs). In some embodiments, M2 and M4 may be deep N-well MOSFETs. In some embodiments, transistors may be 65 nm CMOS transistors. In some embodiments, the voltage reference circuit, including both the voltage reference and feedback portions, may operate in the sub-threshold range of one or all of the transistors.
Transistors in the main stage may be selected to have the same width-to-length (W/L) ratio. The length may be increased to reduce power consumption or decreased to reduce layout area. The width may be optimized to reduce temperature sensitivity.
After the main stage has been designed, the characteristic equation for the feedback circuit may be found by sweeping the voltage (Vbulk) across the main stage, where Vbulk=VOS−cT. VOS is the offset voltage, T=temperature, and c=performance coefficient.
The W/L ratios of transistors of a first auxiliary stage of the feedback circuit may be selected to generate a value of c that provides a temperature dependency that counteracts the temperature dependency of the voltage reference circuit. That is, as discussed above, the feedback circuit is designed to act as either a CTAT or a PTAT, depending on the behavior of the voltage reference circuit so that the temperature dependencies cancel out. Once the W/L ratios are determined to find the desired c, the size of each transistor may be scaled by the same factor to optimize VOS. For example, in some embodiments, VOS may be optimized such that VREF is close to the drain supply voltage (VDD). The second auxiliary stage may be selected in a similar manner to the first auxiliary stage.
The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure or its applications or uses. In the following detailed description of embodiments of the present apparatuses, systems and methods, reference is made to the accompanying drawings which form a part hereof, and which are shown by way of illustration specific embodiments in which the described apparatuses, systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the disclosure. Moreover, for the purpose of clarity, detailed descriptions of certain features will not be discussed when they would be apparent to those with skill in the art so as not to obscure the description of embodiments of the disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the disclosure is defined only by the appended claims.
According to examples of the present disclosure, an ultra-low-power voltage reference which works on the principle of cancellation of temperature dependency on sub-threshold current is disclosed. The feedback control which is based on bulk-voltage compensation, may not only suppresses the second order temperature dependency but may also enable it to achieve a much higher output voltage using supply voltages as low as 0.35 V. The closed-loop control may provide reliable performance over all process corners in sub-threshold operation. A disclosed example design achieves a line sensitivity of 0.004%/V at 200 C and power supply rejection ratio (PSRR) of −45 dB with total power consumption of 12.9 pW. The temperature coefficient is 8.3 ppm/0 C over a temperature range of −10-1100 C and a supply range of 0.35-2.5V. Disclosed herein is a complete feedback-controlled pico-watt voltage reference which may have a stable temperature coefficient and line sensitivity while having an output voltage (293.5 mV) comparable to the supply voltage even if it is operated with a supply voltage as low as 350 mV.
The main (e.g., first) stage 102 may include a first MOSFET device M1 and a second MOSFET device M2 coupled in series. The gate of M1 may be coupled to a common voltage (e.g., ground). The drain of M1 may be coupled to a voltage source VDD (e.g., supply voltage). The source of M1 may be coupled to the drain and the gate of M2. The source of M2 may be coupled to the common voltage. A reference voltage VREF may be provided at a node between the source of M1 and the gate and drain of M2. In some examples, M1 may be a native 2.5V device with a low threshold voltage (Vth). In some examples, M2 may be a 2.5V I/O device with a higher Vth than M1. In some examples, the devices M1 and M2 may be N-channel MOSFETS.
The current through each device, ID, may be dictated by the sub-threshold current equation of MOSFET devices as shown below
Where k′ is the mobility of the device, f is the work function, VT is the thermal voltage, VGS is the gate-to-source voltage, Vth is the threshold voltage, VBS is the substrate (e.g., bulk)-to-source voltage, VSB is the source-to-substrate voltage, VDB is the drain-to-substrate voltage, VDS is the drain-to-source voltage, and VA is the early voltage. Equation (1) can be simplified in some examples by assuming that the bulk and source are at the same potential:
In some examples, it can be assumed that VDS is large enough so that
can be neglected. In some examples, both devices (M1 and M2) may carry equal current, in these examples, the reference voltage VREF can be simplified by equating both current equations as follows:
Where f1 is the work function for M1, f2 is the work function for M2, k′1 is the mobility of M1, k′2 is the mobility of M2, and ΔVth is the threshold voltage difference between M1 and M2. Equation (2) shows that properly sized devices having k1=k2 can lead to a fixed reference voltage:
V
REF∝(Vth1−Vth2)−C01+C1T−C02+C2T=ΔC0+TΔC. (4)
Where Vth1 is the threshold voltage of M1, Vth2 is the threshold voltage of M2, T is temperature, C01 and C02 are the combined temperature independent factors whereas C1 and C2 are the summation of all temperature dependent factors up to the first order in the threshold voltage. Both devices may have identical TCs (C1 and C2), which may provide a constant reference voltage output.
Equation (3) describes the performance of voltage reference if the desired performance is not too stringent (e.g., TC<20 ppm/° C.). However, some approximations and simplifications may cause deviation from the theoretical calculations in some applications.
In some examples, it may be assumed that VDS>>VT. Hence, the exponential term within the parenthesis in Equation (2) is reduced, but the linear term may cause a deviation. Moreover, increasing VDS may mean increasing the minimum supply voltage of the circuit in some applications. In some examples, the device M1 may suffer from the body effect while the device M2 may not if both the devices have their bulk (e.g., substrate) connected to ground. In some examples, it may be assumed that both the devices M1 and M2 may have significant Vth difference, but may have equal temperature coefficients. All these factors may contribute to either CTAT or PTAT like nature with small non-linear temperature dependency especially if the desired reference voltage is comparable to the supply voltage.
Feedback circuits using amplifiers are power hungry and require large voltage headroom to retain the devices in the saturation region. Moreover, they require another stable reference voltage.
An energy efficient feedback mechanism is to control the body voltage of the main stage 102 with one or more auxiliary PTAT or CTAT stages in the bulk feedback network 108. Returning to
Optionally, a second auxiliary stage 106 including devices M5 and M6 coupled in series may be included to compensate for the temperature dependency of the main stage (M1-M2). In some applications, adding a second auxiliary stage 106 may further reduce temperature sensitive of the reference voltage. However, in some examples, the second auxiliary stage 106 may be omitted, which may save power and/or die area. Second auxiliary stage 106 may include MOSFET devices M5 and M6. The gates of M5 and M6 may be coupled to the substrate of M4. The source of M5 and the drain of M6 may also be coupled to the substrate of M4. The drain of M5 may be coupled to the voltage source VDD and the substrate of M5 may be coupled to the common voltage. The substrate and source of M6 may be coupled to the common voltage. In some examples, M5 and M6 may be N-channel devices. In some examples, M5 and M6 may be standard I/O devices.
In some examples, deep N-well devices may be used for M2 and M4 which are available in most modern CMOS processes. M3 and M4 the second stage 104 (e.g., first auxiliary stage) may create a negative feedback for the main stage 102. M5 and M6 of the third stage 106 (e.g., second auxiliary stage) may be included to reduce temperature sensitivity of the first auxiliary stage 104. As a result, a TC as low as 8.3 ppm/° C. can be achieved for an output voltage of 293.5 mV. In some examples, the maximum supply may be determined by the device break-down rating which may be 2.5V for the I/O devices in the used process.
To design a voltage reference circuit according to the present disclosure, such as voltage reference circuit 100, the main stage 102 (M1-M2) may be sized with low VDS so that it can be operated with very low VDD. Designing the main stage 102 with low VDS may increase its temperature dependence. This may be compensated for by the bulk feedback network (e.g., the two auxiliary stages 104, 106).
In some examples, M1 and M2 may have the same W/L ratio which may achieve low temperature dependency. In an example implementation, the length of both the devices were chosen as 80 μm which may reduce power consumption. In other examples, shorter lengths may be chosen to reduce size, but may come at the expense of increased power consumption. The widths of the devices M1 and M2 may be optimized using a plot of TV versus widths of the devices M1 and M2. In the example plot 200 shown in
Once the main stage 102 is designed, the feedback network 108 including auxiliary stages 104 and 106 may be optimized to reduce the TC of the main stage 102 by controlling the bulk proportional to the output voltage. The main stage 102 in the example implementation has a slightly negative TC (−20 ppm/° C.); hence the feedback network may be designed so that it has an overall negative TC.
As illustrated in
The voltage reference circuit 100 may be implemented in a 65 nm CMOS process. The gate lengths of the devices may be chosen to be large to reduce power consumption. However, the same output voltage performance can be achieved with smaller length devices at the expense of higher power consumption. Hence, there may be a trade-off between area and power consumption.
The example implementation of voltage reference circuit 100 having chip layout 500 was simulated over supply voltages from 0.35-2.5V and over temperature from −20° C.-130° C.
The example implementation of the voltage reference circuit was designed in 65 nm CMOS; hence it may have a much higher leakage current compared to wider line CMOS devices or more advanced technology nodes using high-K gate dielectrics or FinFETs. Thick gate-oxide, high-voltage (2.5 V) devices may be used to increase the supply voltage range.
An ultra-low power voltage reference circuit has been disclosed herein which in some examples may exhibit an output voltage of 293 mV even after being supplied by voltage as low as 350 mV. Instead of using conventional amplifiers, in some examples, properly sized CTAT or PTAT stage may be used as feedback to the main stage. This may facilitates operations at lower VDD with ultra-low power consumption. The voltage reference circuit described herein may achieve a temperature coefficient of 7.3 ppm/° C. with line sensitivity of 0.004%/V with a total power consumption of 13.6 pW without any trimming in some examples.
Of course, it is to be appreciated that any one of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and/or processes or be separated and/or performed amongst separate devices or device portions in accordance with the present systems, devices and methods.
Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.
This application claims priority to U.S. Provisional Application No. 62/825,127 filed on Mar. 28, 2019, the contents of which are incorporated herein by reference for any purpose.
| Number | Date | Country | |
|---|---|---|---|
| 62825127 | Mar 2019 | US |
