Voltage regulating circuit for keeping voltage headroom

Abstract

A voltage regulating circuit includes a low-dropout regulator, configured to provide a driving voltage to drive a loading circuit and receive a first detection voltage from a first feedback terminal; and a reference voltage generating circuit, coupled to the low-dropout regulator, configured to receive a second detection voltage from a second feedback terminal. A voltage difference between the first feedback terminal and the second feedback terminal is clamped according to the first detection voltage and the second detection voltage.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a voltage regulating circuit, and more particularly, to a voltage regulating circuit capable of maintaining an operation voltage period of a loading by keeping enough headroom.

2. Description of the Prior Art

With the growth of the data transmission volume of mobile devices, demands for power consumption are increased. In addition, batteries with higher capacities cannot be utilized in the mobile devices for advanced processes with trends of slim-type mobile devices. However, with evolutions of the process, a core voltage of a digital logic circuit of an integrated chip (IC) is lowered. When an operating period of the digital logic circuit is decreased with a voltage drop, which is caused by a path impedance of the IC, the core voltage during the operation period is narrowed down, and causes logic abnormality in circuitry.

FIG. 1 is a schematic diagram of a conventional voltage regulating circuit 10 with a reference circuit 102 and a low-dropout regulator 104 for a loading circuit LC. In FIG. 1, a power path impedance R_{APR_PWR} and a ground path impedance R_{APR_GND} exit between the conventional voltage regulating circuit 10 and the loading circuit LC. Ideally, since a current I_APR of the digital logic circuit DLC flows through the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} the current I_APR is equal to a current I_PWR or I_GND, if R_{APR_PWR} and R_{APR_GND} are small enough, then the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} can be ideally neglected.

However, the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} between the conventional voltage regulating circuit 10 and the loading circuit LC cannot be neglected practically. As such, a voltage difference between two terminals of the digital logic circuit DLC is affected because of an IR drop of the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND}. And IR drop is proportional to the path impedances, which narrows down the voltage operation range of the loading circuit LC.

Therefore, improvements are necessary to the conventional techniques.

SUMMARY OF THE INVENTION

In light of this, the present invention provides a voltage regulating circuit, which compensates a raised voltage and a dropped voltage generated by path impedances between the voltage regulating circuit and a loading circuit to keep enough headroom for operating the loading.

An embodiment of the present invention discloses a voltage regulating circuit comprises a low-dropout regulator, configured to provide a driving voltage to drive a loading circuit and receive a first detection voltage from a first feedback terminal; and a reference voltage generating circuit, coupled to the low-dropout regulator, configured to receive a second detection voltage from a second feedback terminal; wherein a voltage difference between the first feedback terminal and the second feedback terminal is clamped according to the first detection voltage and the second detection voltage.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a conventional voltage regulating circuit with a reference circuit and a low-dropout regulator for a loading circuit.

FIG. 2 is a schematic diagram of a voltage regulating circuit according to an embodiment of the present invention.

FIG. 3, FIG. 5, FIG. 7, FIG. 9 are schematic diagrams of a voltage regulating circuit according to an embodiment of the present invention.

FIG. 4, FIG. 6, FIG. 8, FIG. 10 are schematic diagrams of waveforms of the voltage regulating circuit and a digital logic circuit in the configuration of FIG. 3, FIG. 5, FIG. 7 and FIG. 9 according to an embodiment of the present invention.

FIG. 11, FIG. 12 are schematic diagrams of a voltage regulating circuit according to another embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2, which is a schematic diagram of a voltage regulating circuit 20 according to an embodiment of the present invention. The voltage regulating circuit 20 includes a low-dropout regulator 202 and a reference voltage generating circuit 204, wherein the voltage regulating circuit 20 is configured to provide a stable output for a loading circuit LC. The low-dropout regulator 202 is configured to provide a driving voltage VDD_REG to drive the loading circuit LC through a power path impedance R_{APR_PWR}, and receive a first detection voltage VDD_DET from a first feedback terminal VDD_APR. The reference voltage generating circuit 204 is configured to receive a second detection voltage VSS_DET from a second feedback terminal VSS_APR of the loading circuit LC. The reference voltage generating circuit 204 is coupled to the low-dropout regulator 202, wherein a voltage difference between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR is clamped by the driving voltage VDD_REG determined according to the first detection voltage VDD_DET and the second detection voltage VSS_DET. A power detecting terminal V_FB of the low-dropout regulator 202 is configured to receive the first detection voltage VDD_DET and a ground detecting terminal V_SEN of the reference voltage generating circuit 204 is configured to receive the second detection voltage VSS_DET.

In detail, please refer to FIG. 3 and FIG. 4. FIG. 3 is a schematic diagram of a voltage regulating circuit 30 according to an embodiment of the present invention. FIG. 4 is a schematic diagram of waveforms of the voltage regulating circuit 30 and a loading circuit LC in the configuration of FIG. 3 according to an embodiment of the present invention.

The voltage regulating circuit 30 includes a low-dropout regulator 302 and a reference voltage generating circuit 304. The voltage regulating circuit 30 is configured to provide a stable output for the loading circuit LC. The low-dropout regulator 302 is configured to determine the driving voltage VDD_REG to drive a loading circuit LC through a power path impedance R_{APR_PWR}, and receive a first detection voltage VDD_DET from a first feedback terminal VDD_APR. The driving voltage VDD_REG is determined according to the received voltage of a power detecting terminal V_FB and a reference voltage V_{REF_VDD}, wherein the received voltage is the first detection voltage VDD_DET. The reference voltage generating circuit 304 includes a first resistor module RM_1, a second resistor module RM_2, a current mirror CM, and a multiplexer MUX. The current mirror CM is configured to reflect the current of the first resistor module RM_1 to the second resistor module RM_2 according to a first input voltage V_REF, wherein the first resistor module RM_1 and the second resistor module RM_2 may respectively be a resister series up to mega ohm, and its current is microampere. The multiplexer MUX is configured to generate the reference voltage V_{REF_VDD} to the low-dropout regulator 302 according to the received voltage from the second feedback terminal VSS_APR.

The voltage regulating circuit 30 further includes a plurality of switches S1-S4, which are selectively conducted to operate the voltage regulating circuit 30 in the following configurations:

• • a) The switches S1, S2 are configured to turn on or turn off a function of feedback of the first feedback terminal VDD_APR of a digital logic circuit DLC of the loading circuit LC;
  • when the switch S1 is conducted and the switch S2 is turned off, the voltage feedback of the first feedback terminal VDD_APR is activated; when the switch S1 is turned off and the switch S2 is conducted, the driving voltage VDD_REG is fed back to the low-dropout regulator 302.
  • b) The switches S3, S4 are configured to turn on or turn off a function of detecting the second feedback terminal VSS_APR of a digital logic circuit DLC of the loading circuit LC;
  • when the switch S3 is conducted and the switch S4 is turned off, the function of detecting the second feedback terminal VSS_APR is activated; when the switch S3 is turned off and the switch S4 is conducted, the reference voltage generating circuit 304 detects the second voltage VSS_REG of the low-dropout regulator 302.

As illustrated in FIG. 3, since a power path impedance R_{APR_PWR} and a ground path impedance R_{APR_GND} cannot be neglected between the low-dropout regulator 302 and the loading circuit LC, an IR drop at the digital logic circuit DLC is generated. In an embodiment, the current I_APR is around a hundred of milliampere (mA), while the currents of a power feedback path impedance R_{DET_PWR} and a ground detect path impedance R_{DET_GND} are around tens of microampere (μA). Comparing to the loading condition of the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND}, the current loading of the power feedback path impedance R_{DET_PWR} and the ground detect path impedance R_{DET_GND} usually can be negligible.

In this condition, a power feedback path is conducted via the switch S1, and a ground detecting path is conducted via the switch S3 to compensate the IR drop of the digital logic circuit DLC. The reference voltage generating circuit 304 is configured to generate a first input voltage V_REF on the first resistor module RM_1 according to the first input voltage V_REF and a unit gain buffer. The current mirror CM reflects the current of the first resistor module RM_1 to the second resistor module RM_2 according to the first input voltage V_REF and then establishes the reference voltage V_{REF_VDD} according to the multiplexer MUX.

In addition, since the switch S3 is conducted and the switch S4 is turned off, a ground detecting terminal V_SEN of the second resistor module RM_2 is connected to the second feedback terminal VSS_APR. Assume I_GND≈I_APR, a raised voltage ΔV₁=I_GND*R_{APR_GND}≈I_APR*R_{APR_GND} is generated by the ground path impedance R_{APR_GND}. In such a condition, the raised voltage ΔV₁ is sensed at the ground detecting terminal V_SEN and is compensated on the reference voltage V_{REF_VDD} of the reference voltage generating circuit 304, and the raised voltage ΔV₁ is provided to the low-dropout regulator 302 for compensating the raised ground voltage of the digital logic circuit DLC.

In addition, since the switch S1 is conducted and the switch S2 is turned off, the power detecting terminal V_FB is connected to the first feedback terminal VDD_APR to ensure that the first feedback terminal VDD_APR of the digital logic circuit DLC may be locked on the reference voltage V_{REF_VDD}, which is not varied with the digital logic circuit DLC and the power path impedance R_{APR_PWR} to compensate a dropped voltage ΔV₂=I_PWR*R_{APR_PWR}≈I_APR*R_{APR_PWR} (I_PWR≈I_APR), wherein the dropped voltage ΔV₂ is generated when the current I_APR flows through the power path impedance R_{APR_PWR}.

By detecting the first feedback terminal VDD_APR and the second feedback terminal VSS_APR of the digital logic circuit DLC, the dropped voltage ΔV₂ and the raised voltage ΔV₁ through the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} may be compensated to ensure that a voltage difference VDD_{DIFF_MAX} is maintained between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR. Therefore, the digital logic circuit DLC may be operated with enough margin with either light loading or heavy loading.

As shown in FIG. 4, in a period T0, the current I_APR is around 0 mA when the digital logic circuit DLC is operated without loading, and the voltage difference VDD_{DIFF_MAX} between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR is clamped without interference of the power path impedance and the ground path impedance.

In a period T1, when the digital logic circuit DLC starts to draw the current from the voltage regulating circuit 30, the raised voltage ΔV₁=I_GND*R_{APR_GND}≈I_APR*R_{APR_GND} (I_GND≈I_APR) is generated by the ground path impedance R_{APR_GND}. The raised voltage ΔV₁ is sensed at the ground detecting terminal V_SEN and is compensated for the reference voltage V_{REF_VDD} of the reference voltage generating circuit 304. The raised voltage ΔV₁ is then provided to the low-dropout regulator 302 for compensating the raised voltage ΔV₁ of the digital logic circuit DLC. At the same time, the voltage of the first feedback terminal VDD_APR is fed back to the power detecting terminal V_FB, such that the low-dropout regulator 302 may maintain the voltage difference VDD_{DIFF_MAX} between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR to compensate a dropped voltage ΔV₂=I_PWR*R_{APR_PWR}≈I_APR*R_{APR_PWR} (I_PWR≈I_APR), which is generated when the current I_APR flows through the power path impedance R_{APR_PWR}. Therefore, the digital logic circuit DLC may be operated with enough margin with either light loading or heavy loading.

In another embodiment, when power path impedance R_{APR_PWR} can be neglected and the ground path impedance R_{APR_GND} cannot be neglected between the low-dropout regulator 302 and the reference voltage generating circuit 304, only the ground path impedance R_{APR_GND} should be considered for the compensation of the raised voltage ΔV₁≈I_APR*R_{APR_GND} and the power path impedance R_{APR_PWR} can be neglected in this case.

In order to compensate the IR drop of the ground path impedance R_{APR_GND} the function of detecting the second feedback terminal VSS_APR is activated, and the switch S3 is conducted and the switch S4 is turned off, as shown in FIGS. 5 and 6.

In FIG. 5, the switch S1 is turned off and the switch S2 is conducted. That is, the feedback function of the first feedback terminal VDD_APR is not activated. In addition, the switch S3 is conducted and the switch S4 is turned off to activate the function of detecting the second detection voltage VSS_DET from the second feedback terminal VSS_APR. The reference voltage generating circuit 304 is configured to generate the first input voltage V_REF on the first resistor module RM_1 according to the first input voltage V_REF and a unit gain buffer. The current mirror CM reflects currents of the first resistor module RM_1 to the second resistor module RM_2 according to the first input voltage V_REF and then establishes the reference voltage V_{REF_VDD} according to the multiplexer MUX. Since the switch S3 is conducted and the switch S4 is turned off, the ground detecting terminal V_SEN of the second resistor module RM_2 is connected to the second feedback terminal VSS_APR to detect the second detection voltage VSS_DET. The raised voltage ΔV₁=I_GND*R_{APR_GND}≈I_APR*R_{APR_GND} is generated by the ground path impedance R_{APR_GND}. In such condition, the raised voltage ΔV₁ is sensed at the ground detecting terminal V_SEN and is compensated on the reference voltage V_{REF_VDD} of the reference voltage generating circuit 304. The raised voltage ΔV₁ is provided to the low-dropout regulator 302 for compensating the raised ground voltage of the digital logic circuit DLC.

Since the switch S1 is turned off and the switch S2 is conducted, the power detecting terminal V_FB is connected to the driving voltage VDD_REG to keep up with a variation of the reference voltage V_{REF_VDD}. In addition, since the power path impedance R_{APR_PWR} can be neglected, i.e. ΔV₂=I_PWR*R_{APR_PWR}≈I_APR*R_{APR_PWR}≈0, the driving voltage VDD_REG of the low-dropout regulator 302 would be close to the first feedback terminal VDD_APR, which ensures that the first feedback terminal VDD_APR of the digital logic circuit DLC would not be affected by the current I_APR.

Therefore, by detecting the second feedback terminal VSS_APR of the digital logic circuit DLC, the raised voltage ΔV₁ generated by the current I_APR flowing through the ground path impedance R_{APR_GND} may be compensated to ensure that the clamped voltage between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR is fixed with either light loading or heavy loading of the digital logic circuit DLC.

FIG. 6 is a schematic diagram of waveforms of the voltage regulating circuit 30 and the digital logic circuit DLC in the configuration of FIG. 5 according to an embodiment of the present invention. In the period T0, the current I_APR is around 0 mA when the digital logic circuit DLC is operated without loading, and the voltage difference between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR of the digital logic circuit DLC is clamped without interference of the power path impedance and the ground path impedance, such that the digital logic circuit DLC may be operated within the voltage difference VDD_{DIFF_MAX}.

In the period T1 of FIG. 6, when the digital logic circuit DLC starts to draw the current I_APR from the voltage regulating circuit 30, and the raised voltage ΔV₁≈I_APR*R_{APR_GND} is generated by the current I_APR flowing through the ground path impedance R_{APR_GND}. The raised voltage ΔV₁ is sensed at the ground detecting terminal V_SEN and the reference voltage V_{REF_VDD} of the reference voltage generating circuit 304 is raised by the raised voltage ΔV₁, which is provided to the low-dropout regulator 302. The driving voltage VDD_REG is fed back to a power detecting terminal V_FB, such that the driving voltage VDD_REG may follow the variation of the reference voltage V_{REF_VDD}.

Since the power path impedance R_{APR_PWR} can be neglected (i.e. ΔV₂≈I_APR*R_{APR_PWR}≈0), the voltage drop by the current I_APR flowing through the power path impedance R_{APR_PWR} can be neglected, i.e. a voltage of the first feedback terminal VDD_APR is nearly equal to the driving voltage VDD_REG. Therefore, by detecting the second detection voltage VSS_DET from the second feedback terminal VSS_APR of the digital logic circuit DLC, the raised voltage ΔV₁ generated by the current I_APR flowing through the ground path impedance R_{APR_GND} may be compensated to ensure that the clamped voltage between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR is fixed with either light loading or heavy loading of the digital logic circuit DLC.

In another embodiment, when power path impedance R_{APR_PWR} cannot be neglected and the ground path impedance R_{APR_GND} can be neglected, only the power path impedance R_{APR_PWR} should be considered for the compensation of the IR drop, and the ground path impedance R_{APR_GND} can be neglected in this case.

In order to compensate the IR drop of the power path impedance R_{APR_PWR}, the function of feedback of the first feedback terminal VDD_APR to the reference voltage V_{REF_VDD} is activated, and thus the switch S1 is conducted, the switch S2 is turned off; the switch S3 is turned off, the switch S4 is conducted, as shown in FIG. 7 and FIG. 8.

The reference voltage generating circuit 304 is configured to generate the first input voltage V_REF on the first resistor module RM_1 according to the first input voltage V_REF and a unit gain buffer. The current mirror CM reflects the current of the first resistor module RM_1 to the second resistor module RM_2 according to the first input voltage V_REF and then establishes the reference voltage V_{REF_VDD} according to the multiplexer MUX. Since the switch S3 is turned off and the switch S4 is conducted, the ground detecting terminal V_SEN of the second resistor module RM_2 is connected to the second voltage VSS_REG and the ground path impedance R_{APR_GND} can be neglected.

Moreover, since the switch S1 is conducted and the switch S2 is turned off, the power detecting terminal V_FB of the low-dropout regulator 302 is connected to the first feedback terminal VDD_APR to ensure that the first feedback terminal VDD_APR of the digital logic circuit DLC may be locked on the reference voltage V_{REF_VDD}, which is not varied with the digital logic circuit DLC and the power path impedance R_{APR_PWR}, to compensate a dropped voltage ΔV₂=I_PWR*R_{APR_PWR}≈I_APR*R_{APR_PWR} (I_PWR≈I_APR), which is generated when the current I_APR flows through the power path impedance R_{APR_PWR}.

As shown in FIG. 8, in the period T0, the current I_APR is around 0 mA when the digital logic circuit DLC is operated without loading, and the voltage difference VDD_{DIFF_MAX} between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR is clamped without interference of the power path impedance and the ground path impedance.

In the period T1, when the digital logic circuit DLC starts to draw the current I_APR from the voltage regulating circuit 30, since the ground path impedance R_{APR_GND} can be neglected, the raised voltage ΔV₁ of the current I_APR flows through the ground path impedance R_{APR_GND} can be neglected.

Since the ground detecting terminal V_SEN of the second resistor module RM_2 detects that the second voltage VSS_REG is nearly equal to the voltage of the second feedback terminal VSS_APR, the ground path impedance R_{APR_GND} can be neglected and the raised voltage ΔV₁ on the reference voltage V_{REF_VDD} can be neglected.

The low-dropout regulator 302 may adjust the first feedback terminal VDD_APR by detecting the first detection voltage VDD_DET of the power detecting terminal V_FB to compensate the dropped voltage ΔV₂ of the current I_APR flowing through the power path impedance R_{APR_PWR} to ensure that a voltage difference VDD_{DIFF_MAX} is maintained between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR.

In another embodiment, when both of power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} can be neglected, the driving voltage VDD_REG is fed back to the power detecting terminal V_FB and the second voltage VSS_REG is detected for ensuring the clamped voltage of the digital logic circuit DLC, i.e. the voltage difference VDD_{DIFF_MAX}, is maintained.

As shown in FIG. 9, the switch S1 turned off and the switch S2 is conducted, the power detecting terminal V_FB is connected to the driving voltage VDD_REG to keep up with a variation of the reference voltage V_{REF_VDD}; the switch S3 is turned off and the switch S4 is conducted to turn off the function of detecting the second feedback terminal VSS_APR.

The current mirror CM reflects the current of the first resistor module RM_1 to the second resistor module RM_2 according to the first input voltage V_REF and then establishes the reference voltage V_{REF_VDD} according to the multiplexer MUX. Since the switch S3 is turned off and the switch S4 is conducted, the ground detecting terminal V_SEN of the second resistor module RM_2 is connected to the second voltage VSS_REG and the ground path impedance R_{APR_GND} can be neglected, the raised voltage ΔV₁=I_GND*R_{APR_GND}≈I_APR*R_{APR_GND}≈0, wherein I_GND≈I_APR, is generated when the current I_APR flows through the ground path impedance R_{APR_GND}.

Since the switch S1 is turned off and the switch S2 is conducted, the power detecting terminal V_FB is configured to receive the driving voltage VDD_REG to keep up with a variation of the reference voltage V_{REF_VDD}. In addition, the power path impedance R_{APR_PWR} can be neglected, i.e. ΔV₂=I_PWR*R_{APR_PWR}≈I_APR*R_{APR_PWR}≈0, wherein I_PWR≈I_APR, the driving voltage VDD_REG of the low-dropout regulator 302 is close to the first feedback terminal VDD_APR, which ensures that the first feedback terminal VDD_APR of the digital logic circuit DLC would not be affected by the current I_APR.

As shown in FIG. 10, in the period T0, the current I_APR is around 0 mA when the digital logic circuit DLC is operated without loading, and the voltage difference VDD_{DIFF_MAX} between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR is clamped without interference of the power path impedance and the ground path impedance.

In the period T1, when the digital logic circuit DLC starts to draw the current I_APR from the voltage regulating circuit 30, since the ground path impedance R_{APR_GND} can be neglected, the raised voltage ΔV₁ of the current I_APR flows through the ground path impedance R_{APR_GND} can be neglected, and the second feedback terminal VSS_APR varies with the second voltage VSS_REG.

Since the ground detecting terminal V_SEN of the second resistor module RM_2 detects that the second voltage VSS_REG is nearly equal to the voltage of the second feedback terminal VSS_APR, and then the reference voltage V_{REF_VDD} is output to the low-dropout regulator 302. The driving voltage VDD_REG is fed back to the power detecting terminal V_FB which ensures that the driving voltage VDD_REG keeps up with the reference voltage V_{REF_VDD}.

In addition, since the power path impedance R_{APR_PWR} can be neglected, the dropped voltage ΔV₂ generated by the current I_APR flowing through the power path impedance R_{APR_PWR} can be neglected, and the voltage of the first feedback terminal VDD_APR can vary with the driving voltage VDD_REG.

By detecting the driving voltage VDD_REG and the second voltage VSS_REG, the voltage difference VDD_{DIFF_MAX} between the first feedback terminal VDD_APR and the second feedback terminal VSS_APR may be clamped when both of the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} can be neglected to ensure with either light loading or heavy loading of the digital logic circuit DLC.

Please refer to FIG. 11, which is a schematic diagram of a voltage regulating circuit 1100 according to an embodiment of the present invention. The voltage regulating circuit 1100 includes a low-dropout regulator 1102 and a reference voltage generating circuit 1104. Since FIG. 11 is an embodiment of FIG. 3, element symbols are inherited in FIG. 11. Different from FIG. 3, the reference voltage generating circuit 1104 includes a first resistor module RM and a multiplexer MUX. The multiplexer MUX is configured to generate a reference voltage V_{REF_VDD} to the low-dropout regulator 1102.

When a power path impedance R_{APR_PWR} and a ground path impedance R_{APR_GND} cannot be neglected, an IR drop at a digital logic circuit DLC is generated. In order to compensate the voltage drops caused by the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} the feedback function of the first feedback terminal VDD_APR and the detecting function of the second feedback terminal VSS_APR are activated.

As shown in FIG. 11, when the switch S1 is conducted and the switch S2 is turned off, the function of feedback of the first feedback terminal VDD_APR to the reference voltage V_{REF_VDD} is activated; when the switch S3 is conducted and the switch S4 is turned off the function of detecting the second feedback terminal VSS_APR is activated.

The voltage regulating circuit 1100 is configured to determine the reference voltage V_{REF_VDD} according to a selection of the multiplexer MUX. Since the switch S3 is conducted and the switch S4 is turned off, a ground terminal V_{REF_VSS} of a ground detecting terminal V_SEN is connected to the second feedback terminal VSS_APR to receive a second detection voltage VSS_DET. A raised voltage ΔV₁=I_GND*R_{APR_GND} I_APR*R_{APR_GND}, wherein I_GND≈I_APR, is generated when a current I_APR flow through a ground path impedance R_{APR_GND}, and the raised voltage ΔV₁ is provided to the low-dropout regulator 1102 for compensating the raised ground voltage of the digital logic circuit DLC.

An output voltage VDD_REG of the low-dropout regulator 1102 is [V_{REF_VDD}*(R₂/(R₁+R₂))+V_{REF_VSS}*(R₁/(R₁+R₂))]*(1+R₄/R₃)=V_{REF_VDD}+ΔV₁, wherein R₁=R₂=R₃=R₄=R and V_{REF_VSS}=ΔV₁, which can be a compensation for the IR drop of the ground path impedance R_{APR_GND}.

In addition, since the switch S1 is conducted and the switch S2 is turned off, the power detecting terminal V_FB is connected to the first feedback terminal VDD_APR to receive the first detection voltage VDD_DET from the first feedback terminal VDD_APR, and a dropped voltage ΔV₂=I_PWR*R_{APR_PWR}≈I_APR*R_{APR_PWR} (wherein I_PWR≈I_APR) is generated when the current I_APR flows through the power path impedance R_{APR_PWR}.

By detecting the first detection voltage VDD_DET from the first feedback terminal VDD_APR and the second detection voltage VSS_DET from the second feedback terminal VSS_APR, the raised voltage ΔV₁ and the dropped voltage ΔV₂ generated when the current I_APR flows through the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} may be compensated to ensure that the digital logic circuit DLC may be operated with enough margin with either light loading or heavy loading.

Regarding the waveforms of the voltage regulating circuit 1100 and the digital logic circuit DLC, please refer to FIG. 4 when the power path impedance R_{APR_PWR} and a ground path impedance R_{APR_GND} cannot be neglected. Alternatively, other configurations of the voltage regulating circuit 1100 and corresponding waveforms may be referred to above embodiments of FIG. 3.

Please refer to FIG. 12, which is a schematic diagram of a voltage regulating circuit 1200 according to an embodiment of the present invention. The voltage regulating circuit 1200 includes a low-dropout regulator 1202 and a reference voltage generating circuit 1204. Since FIG. 12 is an embodiment of FIG. 3, element symbols are inherited in FIG. 12. Different from FIG. 3, the reference voltage generating circuit 1204 includes a first resistor module RM, wherein the first resistor module RM includes a resistor R₁ and a resistor R2 in series. The reference voltage generating circuit 1204 is configured to generate an input voltage V_N for the low-dropout regulator 1202 according to a reference voltage V_REF and a ground detecting terminal V_SEN.

When a power path impedance R_{APR_PWR} and a ground path impedance R_{APR_GND} cannot be neglected, an IR drop at a digital logic circuit DLC is generated. In order to compensate the voltage drops caused by the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND}, the feedback function of the first feedback terminal VDD_APR and the detecting function of the second feedback terminal VSS_APR are activated.

As shown in FIG. 12, when the switch S1 is conducted and the switch S2 is turned off, the function of feedback of the first feedback terminal VDD_APR to a reference voltage V_{REF_VDD} is activated; when the switch S3 is conducted and the switch S4 is turned off, the function of detecting the second feedback terminal VSS_APR is activated.

The voltage regulating circuit 1200 is configured to generate the reference voltage V_{REF_VDD} according to a unit gain buffer, the reference voltage V_{REF_VDD} is connected to a terminal of the resistor R₁ of the first resistor module RM, and another terminal of the resistor R₁ is coupled to a ground terminal V_{REF_VSS} via the resistor R2. The input voltage V_N is generated according to a voltage division of the resistors R₁ and R₂ and then transmitted to the low-dropout regulator 1202.

When the switch S3 is conducted and the switch S4 is turned off, the ground terminal V_{REF_VSS} is connected to the second feedback terminal VSS_APR to receive a second detection voltage VSS_DET. A raised voltage ΔV₁=I_GND*R_{APR_GND}≈I_APR*R_{APR_GND} (I_GND≈I_APR) is generated when a current I_APR flows through the ground path impedance R_{APR_GND}. The second feedback terminal VSS_APR is connected to a ground terminal V_{REF_VSS} of the first resistor module RM. Thus, the input voltage V_N=V_{REF_VDD}*(R₂/(R₁+R₂))+V_{REF_VSS}*(R₁/(R₁+R₂))] is provided to the low-dropout regulator 1202 for compensating the raised voltage. An effective output voltage of the low-dropout regulator 1202 is VDD_REG=[V_{REF_VDD}*(R₂/(R₁+R₂)+V_{REF_VSS}*(R₁/(R₁+R₂)]*(1+R₄/R₃=V_{REF_VD}+ΔV₁, wherein R₁=R₂=R₃=R₄=R, V_{REF_VSS}=ΔV₁).

Since the switch S1 is conducted and the switch S2 is turned off, the power voltage terminal V_FB of the low-dropout regulator 1202 is connected to the first feedback terminal VDD_APR to receive the first detection voltage VDD_DET from the first feedback terminal VDD_APR, a dropped voltage ΔV₂≈I_PWR*R_{APR_PWR}≈I_APR*R_{APR_PWR} (I_PWR≈I_APR) generated when the current I_APR flows through the power path impedance R_{APR_PWR}.

By detecting the first detection voltage VDD_DET from the first feedback terminal VDD_APR and the second detection voltage VSS_DET from the second feedback terminal VSS_APR, the raised voltage ΔV₁ and the dropped voltage ΔV₂ generated when the current I_APR flows through the power path impedance R_{APR_PWR} and the ground path impedance R_{APR_GND} may be compensated to ensure that the digital logic circuit DLC may be operated with enough margin with either light loading or heavy loading.

Regarding the waveforms of the voltage regulating circuit 1200 and the digital logic circuit DLC, please refer to FIG. 4 when the power path impedance R_{APR_PWR} and a ground path impedance R_{APR_GND} cannot be neglected. Alternatively, other configurations of the voltage regulating circuit 1200 and corresponding waveforms may be referred to above embodiments of FIG. 3.

In summary, the present invention provides a voltage regulating circuit, which compensates a raised voltage and a dropped voltage generated by path impedances between the voltage regulating circuit and a loading circuit to keep enough headroom for operating the loading.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A voltage regulating circuit, comprising: a low-dropout regulator, configured to provide a driving voltage to drive a loading circuit and receive a first detection voltage from a first feedback terminal; anda reference voltage generating circuit, coupled to the low-dropout regulator, configured to receive a second detection voltage from a second feedback terminal;wherein a voltage difference between the first feedback terminal and the second feedback terminal is clamped according to the first detection voltage and the second detection voltage.

2. The voltage regulating circuit of claim 1, wherein the reference voltage generating circuit comprises: a first resistor module and a second resistor module;a current mirror, coupled to the first resistor module and the second resistor module, configured to reflect the current of the first resistor module to the second resistor module according to a first input voltage; anda multiplexer, coupled to the second resistor module, configured to generate a reference voltage to the low-dropout regulator according to the second detection voltage.

3. The voltage regulating circuit of claim 2, wherein the low-dropout regulator is configured to determine the driving voltage to drive the loading circuit according to a power detecting terminal and the reference voltage.

4. The voltage regulating circuit of claim 1, wherein a voltage of a power detecting terminal is determined according to a power path impedance between the low-dropout regulator and the first feedback terminal.

5. The voltage regulating circuit of claim 4, wherein a power feedback path is conducted to compensate a voltage drop of the power path impedance between the low-dropout regulator and the first feedback terminal.

6. The voltage regulating circuit of claim 1, wherein a voltage of a ground detecting terminal is determined according to a ground path impedance between the reference voltage generating circuit and the second feedback terminal.

7. The voltage regulating circuit of claim 6, wherein a ground detecting path is conducted to compensate a raised voltage of the ground path impedance between the reference voltage generating circuit and the second feedback terminal.

8. The voltage regulating circuit of claim 1, wherein the reference voltage generating circuit comprises: a first resistor module; anda multiplexer, coupled to the first resistor module, configured to generate a reference voltage to the low-dropout regulator.

9. The voltage regulating circuit of claim 8, wherein the low-dropout regulator is configured to determine the driving voltage to drive the loading circuit and to receive the first detection voltage from the first feedback terminal according to a power detecting terminal and a second input voltage, wherein the second input voltage is determined according to an output of the reference voltage and a ground detecting terminal of the low-dropout regulator.

10. The voltage regulating circuit of claim 9, wherein the second input voltage is between an output of the reference voltage and a voltage of the ground detecting terminal.

11. The voltage regulating circuit of claim 9, wherein a power feedback path between the low-dropout regulator and the first feedback terminal is conducted to compensate a voltage drop of a power path impedance between the low-dropout regulator and the first feedback terminal.

12. The voltage regulating circuit of claim 9, wherein the ground detecting terminal is determined according to a ground path impedance between the reference voltage generating circuit and the second feedback terminal.

13. The voltage regulating circuit of claim 12, wherein a ground detecting path is conducted to compensate a raised voltage of the ground path impedance between the reference voltage generating circuit and the second feedback terminal.

14. The voltage regulating circuit of claim 1, wherein the reference voltage generating circuit comprises: a first resistor module, coupled to the second feedback terminal and configured to generate an input voltage for the low-dropout regulator according to the reference voltage and a voltage of a ground detecting terminal.

15. The voltage regulating circuit of claim 14, wherein the low-dropout regulator is configured to determine the driving voltage to drive the loading circuit and receive the first detection voltage from the first feedback terminal according to a power detecting terminal and the input voltage.

16. The voltage regulating circuit of claim 14, wherein a power feedback path between the low-dropout regulator and the first feedback terminal is conducted to compensate a voltage drop of a power path impedance between the low-dropout regulator and the first feedback terminal.

17. The voltage regulating circuit of claim 14, wherein the ground detecting terminal is determined according to a ground path impedance between the reference voltage generating circuit and the second feedback terminal.

18. The voltage regulating circuit of claim 17, wherein a ground detecting path is conducted to compensate a raised voltage of the ground path impedance between the reference voltage generating circuit and the second feedback terminal.