Patent Application
20240329674
The description relates to a voltage regulation circuit receiving as input voltage, in particular a DC (direct current) voltage supply, and outputting a regulated voltage.
In recent years, the rise of GaN (gallium nitride) High Electron Mobility Transistor technologies have attracted interest by the power electronics designers. Nowadays, the goal is to develop fully integrated power converters with both power devices, able to maintain high voltages, and low voltage driving devices, to create a suitable driver. This may lead to several improvements in the direction to obtain lower area, lower cost, improved reliability and reduced parasitic components, due to the fewer interconnections between the driver and the power stage. This allows the exploit of all the advantages of a GaN based technology like higher breakdown voltage, operative frequency and lower on-resistance, compared to usual Power MOS devices.
To implement for instance a monolithic gate driver, several circuit blocks are utilized with a stable voltage bias, provided by voltage regulators.
To obtain a stable supply voltage, used by other parts of the circuit, voltage regulators should have a voltage reference generator which provides a low drift voltage.
Most of known architectures use the p-n junction to obtain a voltage reference and exploit all the devices based on it, from diodes to bipolar transistors. In particular, a so-called bandgap voltage reference operates on the basis of the principle of balancing in a circuit the negative temperature coefficient of a p-n junction, usually the voltage VBE on the base-emitter junction of a bipolar transistor, with the positive temperature coefficient of the thermal voltage VT, where VT=kT/q.
In GaN technology, where transistors are based on the Two-Dimensional Electron Gas (2DEG), these classic design methods cannot be applied.
In
At the state of the art, most architectures for providing a voltage reference in circuit where p-n junctions cannot be exploited can be categorized as:
Also, most of the internal references use another circuit block to create a regulated voltage, available for other circuit blocks as voltage bias. This implies higher current consumption and a more complex circuit.
Also, there are several challenges in designing such circuit block, i.e., voltage regulator with voltage reference, such as:
Various embodiments disclosed herein provide a voltage regulation circuit with a voltage reference which solves the drawbacks of the prior art.
According to one or more embodiments, this can be achieved by means of a voltage regulation circuit having the features set forth in the discussion that follows.
The present disclosure describes solutions regarding a voltage regulation circuit receiving an input voltage, in particular a DC voltage supply, and outputting a regulated voltage,
In variant embodiments, in said output stage coupled between said voltage to regulate and an output node on which said regulated voltage is taken said second MOSFET transistor is coupled to the gate of the first depletion MOSFET transistor,
In variant embodiments, said enhancement MOS transistor is cascoded with a second enhancement MOSFET transistor, the gate of said first enhancement MOSFET transistor being coupled to ground by a first resistor of the voltage divider, the gate of the second enhancement MOSFET transistor being coupled to said first resistor by a second resistor and to the output node by a third resistor.
In variant embodiments, said first depletion MOSFET transistor has its gate coupled to its source through a resistor and coupled to the drain of the first enhancement MOSFET transistor, through said second enhancement MOSFET transistor.
In variant embodiments, said first depletion MOS transistor and second MOSFET transistor are cascoded by respective third and fourth depletion transistors, in particular said third depletion transistor being interposed between the voltage to regulate and the first depletion MOS transistor with its gate coupled to the source of the first depletion MOSFET transistor, and the fourth depletion transistor being coupled between the voltage to regulate and the second MOSFET transistor with its gate coupled to the source of the second MOSFET transistor.
In variant embodiments, said gates of the first depletion MOSFET transistor and second transistor are coupled to ground by a capacitor.
In variant embodiments, said negative feedback loop comprises a differential amplifier which inputs are coupled to said divider output node and to said control node, said first enhancement MOSFET transistor having its gate coupled to its drain, the output of said differential amplifier being coupled to the gate of said second transistor.
In variant embodiments, said depletion n-type MOSFET transistors and enhancement n-type MOSFET transistor are obtained by Gallium Nitride technology, in particular are GaN High Electron Mobility Transistor.
In embodiments said second MOSFET transistor is a second depletion MOSFET transistor.
In embodiments the solution here described regards also a voltage regulation circuit receiving an input voltage, in particular a DC voltage supply, and outputting a regulated voltage,
One or more embodiments will now be described, by way of example, with reference to the annexed figures wherein:
In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.
Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.
The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.
In
Such voltage regulator circuit 20 receives as input voltage, a DC voltage supply VCC, and supplies at an output node REG a regulated voltage VREG, which is regulated to take in account variation determined by a load coupled to the output node REG and also for possible variations of the input voltage VCC. The regulated voltage VREG may in embodiments correspond to an analog voltage supply VREG, for instance of a gate driver in GaN technology.
As shown such voltage regulation circuit 20 comprises, indicated as a whole with 50, a voltage reference circuit configured to supply a reference voltage VREF, which is independent, in particular with respect to temperature variations. In particular the voltage reference circuit 50 here described is configured to behave in a manner similar in some respects to a bandgap reference circuit, in particular in that provides components with negative temperature coefficient and components with positive temperature coefficient.
Then, the voltage regulation circuit 20 comprises a current generator circuit 31 and an output stage 33. The current generator circuit 31 is coupled at its input to the input voltage VCC. The divider circuit 40 is coupled by a divider output node A of the divider circuit 40, i.e., the node on which the divided voltage is taken, in particular in the example between resistors R3 and resistor R4, to the voltage reference circuit 50, which is also coupled by a control node C to such current generator circuit 31. The voltage regulation circuit 20 comprises a first circuit branch B1 and a second circuit branch B2 in parallel, each coupled between said input voltage VCC and ground GND.
On the first branch B1 is arranged, coupled to the input voltage VCC, such current generator circuit 31 comprising a first depletion n-type, i.e., with n channel operating in depletion mode, MOSFET QD2, which drain is coupled to the input voltage VCC and which source is coupled to a source resistor R1. Thus, a current ID2 equal to (−VGS(QD2))/R1, where VGS(QD2) is the gate source voltage of the first depletion n-type MOSFET QD2, flows into the first branch B1, specifically into an enhancement MOSFET QE2 and in particular, into a resistor R5.
The voltage reference circuit 50 indeed comprises, on the first branch B1 a first enhancement n-type, i.e., n channel operating in enhancement mode, MOSFET transistor QE2, which is coupled to ground GND by its source through a source resistor R5 and it is coupled by its drain to a control node C.
The second circuit branch B2, comprises a second depletion n-type MOSFET transistor QD4, which is coupled at its drain to the input voltage VCC, while on its source, the output node REG, outputs the regulated voltage VREG. The second depletion n-type MOSFET transistor QD4 and the first depletion n-type MOSFET QD2 have their gates coupled together and coupled to the control node C. The second depletion n-type MOSFET transistor QD4 can be also defined as a pass transistor. Such gate electrodes are coupled to ground GND through a compensation capacitor CC. As mentioned, in variant embodiments, the second depletion n-type MOSFET transistor QD4 may be substituted by an enhancement n-type MOSFET transistor.
The second depletion n-type MOSFET transistor QD4 represents the output stage 33, with its gate operating as the control input coupled to the control node C and the output on the source, corresponding to output node REG. The output of the current generator 31 thus may be considered as corresponding to the drain of enhancement MOSFET transistor QE1, i.e., node C, which represents the input of the output stage 33, which output, the output node REG, outputs the regulated voltage VREG.
A voltage divider circuit 40 is then provided on the second branch B2 between the source of the second depletion n-type MOSFET transistor QD4, i.e., the regulated output node REG, and ground GND. The voltage divider 40 comprises three resistors in series, R2, R3, R4. The resistor R2 is coupled to the regulated output node REG on which the regulated voltage VREG is taken. The resistor R4 is coupled to ground GND. The node in common between resistor R3 and resistor R4 is coupled to the divider output node A on which the reference voltage VREF is obtained.
Thus, the proposed architecture embeds the voltage reference and the voltage regulator in one circuit, using the voltage reference circuit 50 as part of a feedback network to regulate the output voltage VREG.
As indicated, in the circuit of
Thus, a current ID2 equal to (−VGS(QD2))/R1 flows into the first circuit branch B1, creating a PTAT voltage drop VP on resistor R5 equal to ID2*R5=−VGS(QD2)*R5/R1, since its proportionality with the gate-source voltage of the first depletion n-type MOSFET transistor QD2. The value of resistance of the resistor R1 on the source of the first depletion n-type MOSFET transistor QD2 is selected to obtain a desired valued of bias current. The reference voltage VREF is obtained at the gate of MOSFET QE2 coupled to the divider output node A, as sum of the voltage drop VP across such resistor R5 and the gate source voltage on first enhancement n-type MOSFET QE2, VGS(QE2), which is CTAT, as said. Thus, the voltage reference circuit 50 substantially comprises the first enhancement n-type MOSFET QE2 supplying a CTAT contribution by its gate source voltage VGS(QE2) and the voltage drop VP on the resistor R5, which is originated by the current of the generator 31 comprising the PTAT first depletion n-type MOSFET transistor QD2. The reference voltage VREF is also a fixed potential in the voltage divider 40. So, the regulated voltage VREG is obtained as:
VREG=((R2+R3+R4)/R4)*VREF=((R2+R3+R4)/R4)*(VGS(QE2)+(−VGS(QD2)·R5/R1)
Thus the CTAT contribution and the PTAT contribution originated by the current ID2 of the current generator 31 compensate one with the other. The ratio of resistor R5 to resistor R1 may be set to nullify any temperature dependence.
In the second branch B2, QD4 represents the output transistor of the regulator, generating the regulated voltage VREG, while as said R2, R3 and R4 act as a voltage divider 40 and negative feedback network, biasing the gate voltages of the enhancement MOSFET QE2. In particular, variations, e.g., of current drawn by the load at the output node REG on the second branch B2 are by this arrangement brought back on the first branch B1 by controlling, through the divider 40, the biasing of the gate of the enhancement MOSFET QE2, which varies the current flowing in the first branch B1, and thus the voltage of the control node C, which also is coupled, in particular directly in the embodiment shown, to the gate of the output MOSFET QD4, controlling thus its output, the regulated voltage VREG. In other words, if the regulated voltage VREG decreases, due to an increasing of the load current, the gate voltage of the enhancement MOSFET QE2 is pulled down through the resistor divider, reducing the conduction of MOSFET QE2 itself, then, the voltage of the control node C is pulled up as well as the gate voltage of the output MOSFET QD4, which consequently increases the regulated voltage VREG, restoring the regime condition. The reference voltage VREF may undergo a transient variation during the adjustment of the regulated voltage VREG, but in any case returns to its value at regime.
In
On the first branch B1 such current generator circuit 31 is arranged, coupled to the input voltage VCC, and comprising the first depletion n-type, MOSFET QD2, which drain is coupled to the input voltage VCC and which source is coupled to a source resistor R1. In the embodiment shown, where the cascode 32 is interposed, the drain of the MOSFET is coupled to the input voltage VCC by being coupled to the source of the MOSFET QD1 which drain in its turn is coupled to the input voltage VCC.
In the second circuit branch B2, the second depletion n-type MOSFET transistor QD4 is coupled at its drain to the input voltage VCC through the protection cascode circuit 32, while on its source, the output node REG, outputs the regulated voltage VREG. The second depletion n-type MOSFET transistor QD4 and the first depletion n-type MOSFET QD2 have their gates coupled together and coupled to the control node C. Such gate electrodes are coupled to ground GND through a compensation capacitor CC. Thus, the drains of the two gate coupled depletion n-type MOSFETS QD2 and QD4 are coupled to the input voltage VCC through a protective cascode, i.e., a depletion n-type MOSFET QD1 with the gate coupled to the source of first depletion n-type MOSFET transistor QD2, the source coupled to the drain of the first depletion n-type MOSFET transistor QD2 and the drain coupled to the supply voltage VCC, and a depletion n-type MOSFET QD3, with the gate coupled to the source of the depletion n-type MOSFET transistor QD4, the source coupled to the drain of the second depletion n-type MOSFET transistor QD4 and the drain coupled to the regulated voltage VCC.
Depletion MOSFET transistors QD1 and QD3 are thus used as cascode configuration with the respective transistors QD2 and QD4 to improve the power supply rejection and, therefore, extend the supply voltage range.
Also, an enhancement MOSFET QE1 is used as cascode to decrease the voltage tracking of the reference voltage VREF. To this regard, the voltage reference circuit 50 therefore comprises, on the first branch B1 the first enhancement n-type MOSFET transistor QE2, which is coupled to ground GND by its source through a source resistor R5 and in
In the voltage regulator circuit 20′, in the second branch B2, MOSFET QD4 still represents the output transistor of the regulator, generating the regulated voltage VREG, while as said R2, R3 and R4 act as a voltage divider 40 and negative feedback network, biasing the gate voltages of the enhancement MOSFETS QE1 and QE2. In particular, the second depletion n-type MOSFET transistor QD4 still represents the output stage 33, with its gate operating as the control input coupled to node C and the output on the source, corresponding to output node REG. The output of the current generator 31 thus may be considered as corresponding to the drain of enhanced MOSFET transistor QE1, i.e., node C, which represents the input of the output stage 33, which output, the output node REG, outputs the regulated voltage VREG.
The compensation capacitor CC guarantees the closed loop stability.
The exemplary voltage regulator circuits 20 or 20′ provide an average 6 V voltage, with low line sensitivity and low temperature spread.
The voltage regulator circuits 20 and 20′ are more suitable for small oscillations of the voltage to be regulated.
In
The first branch B1 is substantially similar to the one of embodiments 20, 20′ in that comprises a current generator circuit 71 comprising the first depletion n-type, i.e., with n channel operating in depletion mode, MOSFET QD2, which drain is coupled to the input voltage VCC and which source is coupled to a source resistor R1. The other end of the resistor is coupled to the control node C.
The voltage regulator circuit 60 comprises a voltage reference circuit 90, which analogously to the voltage reference circuit 50 indeed comprises, on the first branch B1 the first enhancement n-type, i.e., n channel operating in enhancement mode, MOSFET transistor QE2, which is coupled to ground GND by its source through the source resistor R5 and it is coupled by its drain to the control node C.
However, in this case the control node C, i.e., the drain of the MOSFET transistor QE2, is short-circuited to its gate, so that the reference voltage VREF forming on such gate it is also present on its drain, i.e., on the control node C.
Also in this case the second depletion n-type MOSFET transistor QD4 represents the output stage 33, with its gate operating as the control input. However, as shown in
Thus, here the reference voltage VREF is generated in the same way, i.e., by circuit 90 on the gate of QE2, however this reference voltage VREF is not coupled to the divider node A, but it is coupled to the control node C which is one of the two inputs of the differential amplifier, the other one receiving the voltage on the divider node A, i.e., VREG*R4/(R3+R4). Therefore the second depletion n-type MOSFET transistor QD4 is driven by the difference, or error, between the reference voltage VREF and the regulated voltage VREG, in particular divided by the ratio value of the divider 80, e.g., R4/(R3+R4). The regulated voltage VREG is the same as described for the other embodiments, or course minus the R2 resistance:
The regulated voltage obtained is proportional to the divided ratio multiplied by the reference voltage, which is set by the difference of the gate source voltage of the enhancement MOSFET on branch B1 to the gate source voltage of the depletion MOSFET, divided by the ratio of the resistance of their source resistor, e.g., R5 and R1.
In
The use of the differential amplifier receiving the reference voltage VREF and a voltage proportional to the regulated voltage VREG allows to handle higher oscillations, e.g., when higher loads are coupled to the regulated voltage node REG.
Also in this case therefore the regulated voltage is fed back by a divider while the reference voltage is set by an enhancement MOSFET QE2, which gate-source voltage are CTAT (Complementary To Absolute Temperature), the input circuit 71 on the same branch, B1, comprising a CTAT depletion MOSFET, QD2.
Also in this case, the gate electrode of the second depletion n-type MOSFET transistor QD4 is coupled to ground GND through a compensation capacitor CC. Also in this case in variant embodiments the MOSFET QD4 can be an enhancement MOSFET instead of a depletion MOSFET:
Thus, in general the voltage regulation circuit here described comprising:
For process variable is intended the variable in a negative feedback loop which is the current measured value of a particular part of a process which is being monitored or controlled.
In the embodiments of
Thus, in the voltage regulator, 20, 20′, of
In other words, with more detail of the couplings of the components, in
In the embodiment of
From the description here above are clear the advantages of the solution here described.
The voltage regulator according to the solution here described, using the described circuital arrangement exploiting depletion and enhancement n-channel MOSFETs, obtains a regulation with a voltage reference which has low line sensitivity and low temperature spread.
The circuit described obtains also advantages in the terms of power consumption, area consumption, cost saving, with respect to the known solution.
Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example, without departing from the scope of protection.
The depletion n-type MOSFET transistors and enhancement n-type MOSFET transistor are obtained by Gallium Nitride technology, in particular are GaN High Electron Mobility Transistor, although it may be used with transistor using other hetero-junctions, for example GaAs and AlGaAs, or also with other compatible transistor technologies.
A voltage regulation circuit (20;20′;60) receiving as input an input voltage (VCC), in particular a DC voltage supply, and outputting a regulated voltage (VREG), may include a voltage reference circuit (50;90) configured to supply a reference voltage (VREF) which is independent, in particular with respect to temperature variations, said voltage regulation circuit (20;20′;60) comprising a first circuit branch (B1) and a second circuit branch (B2) in parallel coupled between said input voltage (VCC) and ground (GND), said first branch (B1) comprising a current generator (31; 71) comprising a first depletion MOSFET transistor (QD2), which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between said input voltage (VCC) and the voltage reference circuit (50;90), said voltage reference circuit (50;90) comprising a first enhancement MOSFET transistor (QE2), which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground (GND) by its source through a source resistor (R5), on which a reference voltage (VREF), sum of the PTAT voltage drop (VP) on the source resistor (R5) and of the gate source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2) being formed, said first enhancement MOSFET transistor (QE2) being arranged on said first branch (B1) and coupled by the drain to said first depletion MOSFET transistor (QD2) in a control node (C), said control node (C) being coupled to the gate of said first enhancement MOSFET transistor (QE2), said first depletion MOSFET transistor (QD2) injecting a PTAT current (ID2) in said first branch (B1) determining a PTAT voltage drop (VP) on said source resistor (R5), said second branch (B2) comprising an output stage (33; 73) coupled between said voltage to regulate (VCC) and an output node (REG) on which said regulated voltage (VREG) is taken, said output stage (33) comprising a second MOSFET transistor (QD4), in part on which output is taken said output node (REG), a resistive voltage divider (40; 80) being coupled to said output node (REG), outputting on a respective divider output node (A) a divided output regulated voltage (VREG) which is inputted as the process variable of a negative feedback loop (QE2; 75) which is also coupled to said reference voltage (VREF), the output of said negative feedback loop (QE2; 75) controlling the gate of said second MOSFET transistor (QD4).
The output stage (33) may be coupled between said voltage to regulate (VCC) and an output node on which said regulated voltage (VREG) is taken said second MOSFET transistor (QD4) is coupled to the gate of the first depletion MOSFET transistor (QD2), said negative feedback loop (QE2; 75) comprising a coupling of said divider output node (A) of said resistive voltage divider (40) to a gate of said first enhancement MOSFET transistor (QE2) on which a reference voltage (VREF), sum of the PTAT voltage drop (VP) on the source resistor (R5) and of the gate source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2), is formed.
The enhancement MOS transistor (QE2) may be cascoded with a second enhancement MOSFET transistor (QE1), the gate of said enhancement MOSFET transistor (QE2) being coupled to ground by a first resistor (R4) of said voltage divider (40), the gate of the second enhancement MOSFET transistor (QE1) being coupled to said first resistor (R4) by a second resistor (R3) and to the output node by a third resistor (R2).
The first depletion MOSFET transistor (QD2) may have its gate coupled to its source through a resistor (R1) and coupled to the drain of the first enhancement MOSFET transistor (QE2), in particular through said second enhancement MOSFET transistor (QE1).
The first depletion MOS transistor (QD2) and second MOSFET transistor (QD4) may be cascaded by respective third (QD1) and fourth depletion transistors (QD3), in particular said third depletion transistor being interposed between the voltage to regulate (VCC) and the first depletion MOS transistor with its gate coupled to the drain of the first depletion MOSFET transistor (QD2), and the fourth depletion transistor (QD3) being coupled between the voltage to regulate (VCC) and the second MOSFET transistor (QD4), with its gate coupled to the source of the second MOSFET transistor (QD4).
The gates of the first depletion MOSFET transistor (QD2) and second transistor (QD4) may be coupled to ground by a compensation capacitor (CC).
The negative feedback loop may include a differential amplifier (75) which inputs are coupled to said divider output node (A) and to said control node (C), said first enhancement MOSFET transistor (QE2) having its gate coupled to its drain, the output of said differential amplifier (75) being coupled to the gate of said second depletion transistor (QD4).
The depletion n-type MOSFET transistors and enhancement n-type MOSFET transistor may be obtained by Gallium Nitride technology, in particular are GaN High Electron Mobility Transistor.
The second MOSFET transistor (QD4) may be a second depletion MOSFET transistor.
A voltage regulation circuit (20; 20′) receiving as input an input voltage (VCC), in particular a DC voltage supply, and outputting a regulated voltage (VREG), may include a voltage reference circuit (50) configured to supply a reference voltage (VREF) which is independent, in particular with respect to temperature variations said voltage regulation circuit (20; 20′) comprising a first circuit branch (B1) and a second circuit branch (B2) in parallel coupled between said input voltage (VCC) and ground (GND), comprising said first branch (B1) comprising a current generator (31) comprising a first depletion MOSFET transistor (QD2), which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between said input voltage (VCC) and the voltage reference circuit (50) said voltage reference circuit (50) comprising a first enhancement MOSFET transistor (QE2), which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground (GND) by its source through a source resistor (R5), said first depletion MOSFET transistor (QD2) injecting a PTAT current (ID2) in said first branch (B1) determining a PTAT voltage drop (VP) on said source resistor (R5), said second branch (B2) comprising an output stage (33) coupled between said voltage to regulate (VCC) and an output node on which said regulated voltage (VREG) is taken, said output stage comprising a second MOSFET transistor (QD4), in particular a depletion MOSFET, coupled to the gate of the first depletion MOSFET transistor (QD2), said output node (REG) being coupled through a resistive voltage divider (40) to a gate (A) of said first enhancement MOSFET transistor (QE2) on which a reference voltage (VREF), sum of the PTAT voltage drop (VP) on the source resistor (R5) and of the gate source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2) is formed.
The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102023000006477 | Apr 2023 | IT | national |
