Patent Grant
9798341
This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2014-007147 filed on Jan. 17, 2014, the entire content of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a protection circuit for an output transistor of a voltage regulator.
2. Description of the Related Art
A related-art voltage regulator is now described.
The related-art voltage regulator includes an error amplifier circuit 104, a reference voltage circuit 103, an NMOS transistor 602, resistors 105 and 106, a diode 601, a ground terminal 100, an output terminal 102, and a power supply terminal 101.
The resistors 105 and 106 are connected in series between the output terminal 102 and the ground terminal 100, and divide an output voltage Vout generated at the output terminal 102. A voltage generated at a connection point of the resistors 105 and 106 is represented by Vfb. The error amplifier circuit 104 controls a gate voltage of the NMOS transistor 602 so that the voltage Vfb may approach a voltage Vref of the reference voltage circuit 103, to thereby control the NMOS transistor 602 to output an output voltage Vout from the output terminal 102. The diode 601 clamps the gate voltage of the NMOS transistor 602 so that the gate of the NMOS transistor is protected from a breakdown even if a voltage exceeding a withstand voltage of the gate of the NMOS transistor is input from the power supply terminal 101 (for example, see Japanese Patent Application Laid-open No. 2002-343874).
However, the related-art voltage regulator has a problem in that, because the gate of the NMOS transistor 602 is clamped by only the diode, a drivability of the NMOS transistor 602 is limited.
The present invention has been made in view of the above-mentioned problem, and provides a voltage regulator including a protection circuit for a gate of an output transistor, which does not limit a drivability of the output transistor.
In order to solve the related-art problem, a voltage regulator according to one embodiment of the present invention has the following configuration.
The voltage regulator includes: a power supply terminal configured to input a power supply voltage; a reference voltage circuit configured to output a reference voltage; an output transistor; an error amplifier circuit configured to amplify and output a difference between a divided voltage and the reference voltage, the divided voltage being obtained by dividing an output voltage output from the output transistor, to thereby control a gate of the output transistor; a clamp circuit connected between the gate of the output transistor and the power supply terminal; and a level shift circuit including an input terminal connected to the gate of the output transistor and an output terminal connected to an input terminal of the clamp circuit.
The clamp circuit of the voltage regulator according to one embodiment of the present invention is configured so that the clamp circuit operates when the output voltage of the error amplifier circuit decreases below a predetermined voltage, and hence the gate of the output transistor can be protected without limiting the drivability of the output transistor.
In the following, embodiments of the present invention are described with reference to the drawings.
The voltage regulator according to the first embodiment includes an error amplifier circuit 104, a reference voltage circuit 103, an output transistor 110, PMOS transistors 112 and 113, resistors 105 and 106, a constant current circuit 111, a ground terminal 100, an output terminal 102, and a power supply terminal 101. The constant current circuit 111 and the PMOS transistor 112 form a level shift circuit 121. The PMOS transistor 113 is a clamp circuit for a gate of the output transistor 110.
Next, connections in the voltage regulator according to the first embodiment are described.
The resistor 105 and the resistor 106 are connected in series between the output terminal 102 and the ground terminal 100. The error amplifier circuit 104 has an inverting input terminal connected to a positive electrode of the reference voltage circuit 103 and a non-inverting input terminal connected to a connection point of the resistor 106 and the resistor 105. The output transistor 110 has a gate connected to an output terminal of the error amplifier circuit 104, a source connected to the power supply terminal 101, and a drain connected to the output terminal 102. The PMOS transistor 112 has a gate connected to the output terminal of the error amplifier circuit 104, a source connected to a gate of the PMOS transistor 113, and a drain connected to the ground terminal 100. The PMOS transistor 113 has a drain connected to the output terminal of the error amplifier circuit 104 and a source connected to the power supply terminal 101. The constant current circuit 111 has one terminal connected to the power supply terminal 101 and the other terminal connected to the gate of the PMOS transistor 113.
Next, an operation of the voltage regulator according to the first embodiment is described.
When a power supply voltage VDD is input to the power supply terminal 101, the voltage regulator outputs an output voltage Vout from the output terminal 102. The resistors 106 and 105 divide the output voltage Vout and output a divided voltage Vfb. The reference voltage circuit 103 outputs a reference voltage Vref. The error amplifier circuit 104 controls a gate voltage of the output transistor 110 so that the reference voltage Vref and the divided voltage Vfb have the same value, that is, the output voltage Vout is constant.
When the output voltage Vout is higher than a predetermined voltage, the divided voltage Vfb is higher than the reference voltage Vref. Hence, an output signal of the error amplifier circuit 104 (the gate voltage of the output transistor 110) is increased, and the output transistor 110 is turned off to reduce the output voltage Vout. In addition, when the output voltage Vout is lower than the predetermined voltage, operations opposite to the above-mentioned operations are performed to increase the output voltage Vout. In this way, the voltage regulator operates so that the output voltage Vout is constant.
It is assumed here that a threshold value of the PMOS transistor 113 is represented by Vth, a difference between an input voltage and an output voltage of the level shift circuit 121 is represented by VLS, the gate voltage of the output transistor 110 is represented by VDRVG, and a gate voltage of the PMOS transistor 113 is represented by VDRVG_H. A condition under which the level shift circuit 121 operates is expressed as follows.
VDD−VDRVGH_H>|Vth| (1)
Further, the voltage VDRVG_H is expressed as follows.
VDRVG_H=VDRVG+VLS (2)
The following holds based on Expressions (1) and (2).
VDRVG<VDD−|Vth|−VLS (3)
Based on the above-mentioned expressions, the PMOS transistor 113 starts to cause a current to flow when the voltage VDRVG decreases from the power supply voltage VDD to be smaller than VDD−|Vth|−VLS, thereby starting a clamping operation. A voltage VDRVG at which the PMOS transistor 113 starts the clamping operation is referred to as a clamp level. By setting the clamp level to a voltage around a withstand voltage of the gate of the output transistor 110, a gate-source voltage of the output transistor 110 can be increased while a breakdown of the gate is prevented, which enables the operation in a high drivability region. In this manner, the drivability is increased, and hence a dropout voltage of the output voltage Vout can be made small even when an output current is increased.
Further, when the voltage VDRVG_H exceeds the threshold value of the PMOS transistor 113, the PMOS transistor 113 can steeply increase a current. Therefore, the PMOS transistor 113 can control the voltage VDRVG to be a desired clamp level even when a boost circuit is provided, which causes a larger current than normal to flow to the gate of the output transistor 110 to perform the control.
When a threshold value of the PMOS transistor 112 is set to the threshold value Vth of the PMOS transistor 113, VLS=|Vth| holds and Expression (3) is then expressed as follows.
VDRVG<VDD−2×|Vth| (4)
Based on Expression (4), the PMOS transistor 113 starts to cause a current to flow when the voltage VDRVG decreases from the power supply voltage VDD to be smaller than VDD−2×|Vth|, thereby starting the clamping operation. By increasing the clamp level to a voltage around the withstand voltage of the gate of the output transistor 110, the gate-source voltage of the output transistor 110 can be increased while the breakdown of the gate is prevented, which enables the operation in the high drivability region. In this manner, the drivability is increased, and hence the dropout voltage of the output voltage Vout can be made small even when the output current is increased.
Note that, when the same type of transistor is used for the PMOS transistor 113 and the output transistor 110, the transistors are less affected by variation in threshold value and a drivability of the output transistor 110 thus hardly varies. Further, the PMOS transistor 112 and the PMOS transistor 113 have the same threshold value in the above description, but the present invention is not limited to this configuration and may use transistors having different threshold values. In addition, the use in the voltage regulator is described above as an example, but the present invention can be used in any circuit configuration without limiting to the voltage regulator as long as the circuit configuration uses an output transistor such as an operational amplifier circuit.
As described above, the voltage regulator according to the first embodiment can protect the gate by controlling the clamp circuit by the output of the level shift circuit 121 without limiting the drivability of the output transistor 110.
An operation of the voltage regulator according to the second embodiment is described. A normal operation is the same as that in the first embodiment.
When a threshold value of the diode-connected PMOS transistor is represented by Vth similarly to the threshold value of the PMOS transistor 112, VLS=|Vth|+n×|Vth|=(n+1)×|Vth| holds, and Expression (3) is then expressed as follows.
VDRVG<VDD−n+2)×|Vth| (5)
Based on Expression (5), the PMOS transistor 113 starts to cause a current to flow when the voltage VDRVG decreases from the power supply voltage VDD to be smaller than VDD−(n+2)×|Vth|, thereby starting the clamping operation.
When the level shift circuit 121 is configured in this manner, the clamp level can be easily adjusted by changing the number of the diode-connected PMOS transistors.
As described above, the voltage regulator according to the second embodiment can protect the gate by controlling the clamp circuit by the output of the level shift circuit 121 without limiting the drivability of the output transistor 110. Further, the clamp level can be easily adjusted by changing the number of the diode-connected PMOS transistors 201 to 20n.
An operation of the voltage regulator according to the third embodiment is described. A normal operation is the same as that in the first embodiment.
When a resistance value of the resistor 301 is represented by R1 and a current of the constant current circuit 111 is represented by I1, Expression (3) is then expressed as follows.
VDRVG<VDD−2×|Vth|−I1×R1 (6)
Based on Expression (6), the PMOS transistor 113 starts to cause a current to flow when the voltage VDRVG decreases from the power supply voltage VDD to be smaller than VDD−2×|Vth|−I1×R1, thereby starting the clamping operation.
With this configuration, the clamp level can be easily adjusted by changing the resistance value R1 of the resistor 301.
As described above, the voltage regulator according to the third embodiment can protect the gate to prevent the breakdown of the gate by controlling the clamp circuit by the output of the level shift circuit 121 without limiting the drivability of the output transistor 110. Further, the clamp level can be easily adjusted by changing the resistance value of the resistor 301.
An operation of the voltage regulator according to the fourth embodiment is described. A normal operation is the same as that in the first embodiment.
When a threshold value of each of the PMOS transistors 401 to 40n is represented by Vth similarly to the threshold value of the PMOS transistor 112, VLS=|Vth|+n×|Vth|=(n+1)×|Vth| holds and Expression (3) is then expressed as follows.
VDRVG<VDD−(n+2)×|Vth| (7)
Based on Expression (7), the PMOS transistor 113 starts to cause a current to flow when the voltage VDRVG decreases from the power supply voltage VDD to be smaller than VDD−(n+2)×|Vth|, thereby starting the clamping operation. With this configuration, the clamp level can be easily adjusted by changing the number of the PMOS transistors 401 to 40n.
Note that, the PMOS transistor 112 and the PMOS transistors 401 to 40n have the same threshold value in the above description, but the present invention is not limited to this configuration and may use transistors having different threshold values. In addition, the use in the voltage regulator is described above as an example, but the present invention can be used in any circuit configuration without limiting to the voltage regulator as long as the circuit configuration uses an output transistor such as an operational amplifier circuit.
As described above, the voltage regulator according to the fourth embodiment can protect the gate to prevent the breakdown of the gate by controlling the clamp circuit by the output of the level shift circuit 121 without limiting the drivability of the output transistor 110. Further, the clamp level can be easily adjusted by changing the number of the PMOS transistors 401 to 40n.
Connections in the voltage regulator according to the fifth embodiment are described. The PMOS transistors 501 to 50n each having a gate and a drain connected to each other are connected in series. The PMOS transistor 501 has the gate and the drain connected to the gate of the output transistor 110 and a source connected to the gate and the drain of the PMOS transistor 502. The n-th PMOS transistor 50n connected in series has the gate and the drain connected to the gate of the PMOS transistor 113 and a source connected to the power supply terminal 101. The rest is the same as in
An operation of the voltage regulator according to the fifth embodiment is described. A normal operation is the same as that in the first embodiment.
When a threshold value of each of the PMOS transistors 501 to 50n is represented by Vth similarly to the threshold value of the PMOS transistor 113, VLS=(n−1)×|Vth| holds and Expression (3) is then expressed as follows.
VDRVG<VDD−n×|Vth| (8)
Based on Expression (8), the PMOS transistor 113 starts to cause a current to flow when the voltage VDRVG decreases from the power supply voltage VDD to be smaller than VDD−n×|Vth|, thereby starting the clamping operation. With this configuration, the clamp level can be easily adjusted by changing the number of the PMOS transistors 501 to 50n.
Note that, the PMOS transistor 113 and the PMOS transistors 501 to 50n have the same threshold value in the above description, but the present invention is not limited to this configuration and may use transistors having different threshold values. In addition, the use in the voltage regulator is described above as an example, but the present invention can be used in any circuit configuration without limiting to the voltage regulator as long as the circuit configuration uses an output transistor such as an operational amplifier circuit.
As described above, the voltage regulator according to the fifth embodiment can protect the gate to prevent the breakdown of the gate by controlling the clamp circuit by the output of the level shift circuit 121 without limiting the drivability of the output transistor 110. Further, the clamp level can be easily adjusted by changing the number of the PMOS transistors 501 to 50n.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-007147 | Jan 2014 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20030011952 | Fukui | Jan 2003 | A1 |
| 20030090251 | Nakashimo | May 2003 | A1 |
| 20050068266 | Sano | Mar 2005 | A1 |
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| 20090273237 | Inoue | Nov 2009 | A1 |
| 20100090665 | Jian | Apr 2010 | A1 |
| Number | Date | Country |
|---|---|---|
| 2002-343874 | Nov 2002 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20150205313 A1 | Jul 2015 | US |
