Patent Grant
11036247
This application is related to U.S. patent application Ser. No. 16/699,076, entitled “DISTRIBUTED LOW-DROPOUT VOLTAGE REGULATOR (LDO) WITH UNIFORM POWER DELIVERY,” filed concurrently, the content of which is incorporated by reference herein.
Voltage regulators, in particular linear voltage regulators, are devices that are used to maintain a steady voltage. A low-dropout or LDO regulator is a DC linear voltage regulator that can regulate the output voltage even when the supply voltage is very close to the output voltage. Such voltage regulators have broad applicability. For example, voltage regulators may be utilized with analog-to-digital converters (ADC), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and other high performance/high power products. The voltage regulators may provide clean (e.g., steady) output voltage to one or more components of these high performance/high power products even in instances where input voltage into the voltage regulator is close to the output voltage.
A parameter for measuring the performance of linear regulators is PSRR (Power Supply Rejection Ratio, Power Supply Ripple Rejection, or Power supply ripple rejection ratio). PSRR describes the capability of the linear regulator to avoid undesired supply noise/interference from coupling to LDO output. High PSRR over a wide frequency range is difficult to achieve for LDO with reasonable power consumption. In a linear regulator having a high PSRR, power supply noise and interferences will not be coupled to the sensitive output, to provide quiet power supply to the circuit.
As described above, high PSRR is desirable in linear regulators, including LDO voltage regulators. Conventional approaches to maintain PSRR often involve wide bandwidth and high gain. However, these approaches need large devices and high power consumption. In embodiments of the present invention, using a compensation capacitance inserted in a proper location as described herein, substantial improvement in PSRR can be achieved without large device size and high power consumption.
According to some embodiments of the present invention, a linear voltage regulator circuit includes a power supply terminal and a ground terminal, and a differential amplifier coupled between the power supply terminal and the ground terminal. The differential amplifier is configured to amplify a differential between a reference voltage and a regulated output voltage. The differential amplifier includes a pair of input transistors, a pair of bias transistors, and a pair of current mirror transistors coupled between the power supply terminal and the ground terminal. The differential amplifier also includes a bias voltage coupled to a gate node of each of the pair of bias transistors, and a virtual ground node at a source node of one of the pair of bias transistors. The linear voltage regulator also includes an output transistor, which includes a gate node coupled to the differential amplifier, a source node coupled to the power supply terminal, and a drain node providing the regulated output voltage. The linear voltage regulator further includes a compensation capacitor coupled between the power supply terminal and the virtual ground node in the differential amplifier to provide a current between the power supply terminal and the gate node of the output transistor to reduce effects of capacitances coupled to the gate node that degrade PSRR of the voltage regulator.
In some embodiments of the above voltage regulator, the pair of input transistors includes a first transistor for receiving a sample of the regulated output voltage and a second transistor for receiving a reference voltage. The pair of bias transistors includes a third transistor and a fourth transistor coupled between the pair of input transistors and the pair of current mirror transistors. A bias voltage is coupled to respective gate nodes of the third and fourth transistors. The pair of current mirror transistors includes a fifth transistor and a sixth transistor having their respective gate nodes coupled together and coupled to a drain node of the fifth transistor. The virtual ground node is at a source node of the third or the fourth transistor.
In some embodiments, the first, second, third, and fourth transistors are N-channel transistors, and the fifth and sixth transistors are P-channel transistors
In some embodiments, the output transistor is an P-channel transistor, and the regulated output voltage is provided at a drain node of the output transistor.
In some embodiments, the output transistor is an N-channel transistor, and the regulated output voltage is provided a source node of the output transistor.
According to some embodiments of the present invention, a voltage regulator circuit includes a power supply terminal and a ground terminal, and a differential amplifier coupled between the power supply terminal and the ground terminal. The voltage regulator circuit also includes an output transistor, which includes a gate node coupled to an output node of the differential amplifier to receive a gate voltage and to provide a regulated output voltage at an output node of the output transistor. The differential amplifier is configured to provide the gate voltage based on a differential between a reference voltage and the regulated output voltage. The voltage regulator also includes a compensation capacitance coupled between a virtual ground node and either the power supply terminal or the ground terminal and a virtual ground node in the differential amplifier.
In some embodiments of the above voltage regulator, the compensation capacitance is configured to reduce effects of capacitances that degrade PSRR (Power Supply Rejection Ratio).
In some embodiments the differential amplifier includes a pair of input transistors, a pair of bias transistors, and a pair of current mirror transistors coupled between the power supply terminal and the ground terminal. A bias voltage is coupled to a gate node of each of the pair of bias transistors, and the virtual ground node is at a source node of one of the pair of bias transistors.
In some embodiments, the pair of input transistors includes a first transistor for receiving a sample of the regulated output voltage and a second transistor for receiving a reference voltage. The pair of bias transistors includes a third transistor and a fourth transistor coupled between the pair of input transistors and the pair of current mirror transistors. A bias voltage is coupled to respective gate nodes of the third and fourth transistors. The pair of current mirror transistors includes a fifth transistor and a sixth transistor having their respective gate nodes coupled together and coupled to a drain node of the fifth transistor. The virtual ground node is located at a source node of the third or the fourth transistor.
In some embodiments, the compensation capacitance is coupled between a power supply terminal and the virtual ground node. In some embodiments, the first, second, third, and fourth transistors are N-channel transistors; and the fifth and sixth transistors are P-channel transistors.
In some embodiments, the output transistor is an P-channel transistor, and the output node is a drain node of the output transistor.
In some embodiments, the output transistor is an N-channel transistor, and the output node is a source node of the output transistor.
In some embodiments, the output transistor is an N-channel transistor, and the output node is a drain node of the N-channel transistor.
In some embodiments, the compensation capacitance is coupled between a ground terminal and the virtual ground node. In some embodiments, the first, second, third, and fourth transistors are P-channel transistors, and the fifth and sixth transistors are N-channel transistors.
According to some embodiments of the present invention, a method includes providing a voltage regulator having a differential amplifier coupled to a gate node of an output transistor, and providing a virtual ground node in the voltage regulator. The method also includes determining an optimal capacitance value for a compensation capacitor between a power terminal and the virtual ground node for improving PSRR (Power Supply Rejection Ratio) of the voltage regulator. The method further includes coupling a compensation capacitor having the optimal capacitance value between the power terminal and the virtual ground node in the differential amplifier.
In some embodiments, the method further includes performing voltage regulation using the voltage regulator with the compensation capacitor.
In some embodiments, the differential amplifier includes a pair of input transistors, a pair of bias transistors, and a pair of current mirror transistors coupled between a power supply terminal and a ground terminal. A bias voltage is coupled to a gate node of each of the pair of bias transistors, and the virtual ground node is located at a source node of one of the pair of bias transistors.
In some embodiments, determining a capacitance value includes using circuit simulation technique to determine an optimal capacitance value.
A further understanding of the nature and advantages of the present invention may be realized by reference to the following drawings. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description can be applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
In the following description, for the purposes of explanation, specific details are set forth in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent that various embodiments may be practiced without these specific details. The figures and description are not intended to be restrictive. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
Although this disclosure may reference MOSFET based LDOs it is within the scope of this disclosure to apply the techniques herein to voltage regulators of different configurations, including, Bipolar Junction Transistor (BJT) LDOs, BJT switch transistors, and the like.
The low-dropout voltage regulator (LDO) illustrated in
LDO 100 in
These capacitances can increase the input capacitance of output transistor 120 and degrade the PSRR of the circuit. In the mid to high frequency range, especially at frequencies higher than the unity gain bandwidth of the feedback loop, the PSRR degradation can be due to the undesired capacitive coupling from the power transistor gate Vg to other low impedance nodes. For example, when Vdd rises or drops, the gate voltage Vg cannot follow exactly Vdd due to current drawn from capacitance Cc. Therefore, an AC current (which is equal to transconductance gm multiplied by gate-source voltage Vgs) is injected to Vout and degrades the PSRR performance. In this example, Cc is just an example of undesired capacitive coupling. Other undesired capacitive coupling includes those coupled to a bias voltage or the ground, etc., which can also degrade PSRR.
One difference between LDO 300 in
The virtual ground node 312 is a circuit node with a very low impedance that allows a current to the gate node 321 to vary, while maintaining a substantially constant voltage. As an example, a virtual ground node can be located at a source node of an MOS transistor having a constant gate bias voltage. The drain node of the MOS transistor is coupled to a constant current source and the gate node 321 of the output transistor 320. In some embodiments, the constant current source can be provided by a current mirror in the differential amplifier, as described in more detail in connection to
As shown in
As shown in
Differential amplifier 410 includes a first input 411 at a gate node of a first transistor M1 for receiving a sample of the LDO output voltage Vout at output node 424 through a voltage divider made up of resistors R1 and R2. Differential amplifier 410 also includes a second input 412 at a gate node of a second transistor M2 for receiving a reference voltage, Vref, which can be provided, e. g., by a band-gap reference circuit (not shown). The first and second transistors M1 and M2 are coupled to the ground GND at power terminal 402 through a current sink that provides a current I0. Differential amplifier 410 also includes a current mirror made up of two transistors M5 and M6. Current mirror M5 and M6 are coupled to Vdd at the power terminal 401. As shown in
In the example of
As shown in
In the example of
In
In embodiments of the invention, a compensation capacitance is introduced to reduce the capacitances that degrade the PSRR of LDO 400. As shown in
In some embodiments, the capacitance value of compensation capacitance can be determined by circuit simulation or hand calculation. For example, the PSRR can be determined by circuit simulation or hand calculation for different capacitance values of the compensation capacitance at different frequencies. A capacitance value of the compensation capacitance can be selected that, at a desirable frequency, provides the most PSRR improvement.
In order to confirm the effectiveness of the compensation capacitance, a circuit simulation study is carried out. At an optimal compensation capacitance value of about 3 nF at about 10 MHz, an improvement of about 25 db in PSRR can be achieved. In circuit implementation, component mismatch can prevent realization of the optical value. However, even with a compensation capacitance value that is about 25% off the optimal capacitance, an improvement of 12 db in PSRR can still be achieved.
As shown in
In the example of
As shown in
In the example of
In
In embodiments of the invention, a compensation capacitance is introduced to reduce the capacitances that degrade the PSRR of LDO 500. As shown in
In some embodiments, the capacitance value of compensation capacitance can be determined by circuit simulation or hand calculation. For example, the PSRR can be determined by circuit simulation or hand calculation for different capacitance values of the compensation capacitance at different frequencies. A capacitance value of the compensation capacitance can be selected that, at a desirable frequency, provides the most PSRR improvement.
As shown in
In the example of
As shown in
In the example of
In
In embodiments of the invention, a compensation capacitance is introduced to reduce the capacitances that degrade the PSRR of LDO 600. As shown in
In some embodiments, the capacitance value of compensation capacitance can be determined by circuit simulation or hand calculation. For example, the PSRR can be determined by circuit simulation or hand calculation for different capacitance values of the compensation capacitance at different frequencies. A capacitance value of the compensation capacitance can be selected that, at a desirable frequency, provides the most PSRR improvement.
As shown in
In the example of
As shown in
In the example of
In
In embodiments of the invention, a compensation capacitance is introduced to reduce the capacitances that degrade the PSRR of voltage regulator 700. As shown in
In some embodiments, the capacitance value of compensation capacitance can be determined by circuit simulation or hand calculation. For example, the PSRR can be determined by circuit simulation or hand calculation for different capacitance values of the compensation capacitance at different frequencies. A capacitance value of the compensation capacitance can be selected that, at a desirable frequency, provides the most PSRR improvement.
In some embodiment, the voltage regulator circuits described above in connection with
At 810, the method includes providing a linear voltage regulator having a differential amplifier coupled to an output transistor. Examples of the linear voltage regulator are described above in connection with
At 820, the method includes providing a virtual ground node in the differential amplifier. Examples of the virtual ground in various linear voltage regulators are described above in connection with
At 830, the method includes determining an optimal capacitance value for a compensation capacitor between a gate node of the output transistor and the virtual ground node in the differential amplifier for improving the PSRR of the voltage regulator. As described above, the optimal capacitance value can be determined using circuit simulation techniques. In some cases, the capacitance value can be determined by hand calculation.
At 840, the method includes coupling a compensation capacitor having the optimal capacitance value between the gate node of the output transistor and the virtual ground node in the differential amplifier.
At 850, the method includes performing voltage regulation using the linear voltage regulator with the compensation capacitance. Examples of various linear voltage regulators including the compensation capacitance are described above in connection with
Numerous specific details are set forth herein to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter may be practiced without these specific details. In other instances, methods, apparatuses, or systems that would be known by one of ordinary skill have not been described in detail so as not to obscure claimed subject matter.
While the present subject matter has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing may readily produce alterations to, variations of, and equivalents to such embodiments. Accordingly, it should be understood that the present disclosure has been presented for purposes of example rather than limitation, and does not preclude inclusion of such modifications, variations, and/or additions to the present subject matter as would be readily apparent to one of ordinary skill in the art. Indeed, the methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure.
Conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain examples include, while other examples do not include, certain features, elements, and/or steps. Thus, such conditional language is not generally intended to imply that features, elements and/or steps are in any way required for one or more examples or that one or more examples necessarily include logic for deciding, with or without author input or prompting, whether these features, elements and/or steps are included or are to be performed in any particular example.
The terms “comprising,” “including,” “having,” and the like are synonymous and are used inclusively, in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense (and not in its exclusive sense) so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list. The use of “adapted to” or “configured to” herein is meant as open and inclusive language that does not foreclose devices adapted to or configured to perform additional tasks or steps. Additionally, the use of “based on” is meant to be open and inclusive, in that a process, step, calculation, or other action “based on” one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited. Similarly, the use of “based at least in part on” is meant to be open and inclusive, in that a process, step, calculation, or other action “based at least in part on” one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited. Headings, lists, and numbering included herein are for ease of explanation only and are not meant to be limiting.
The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of the present disclosure. In addition, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described blocks or states may be performed in any order other than that specifically disclosed, or multiple blocks or states may be combined in a single block or state. The example blocks or states may be performed in serial, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed examples. Similarly, the example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed examples.
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