Voltage regulator compensation circuit and method

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of voltage regulators, and particularly to methods of improving a voltage regulator's response to a load transient.

2. Description of the Related Art

The purpose of a voltage regulator is to provide a nearly constant output voltage to a load, despite being powered by an unregulated input voltage and having to meet the demands of a varying load current.

In some applications, a regulator is required to maintain a nearly constant output voltage for a step change in load current; i.e., a sudden large increase or decrease in the load current demanded by the load. For example, a microprocessor may have a “power-saving mode” in which unused circuit sections are turned off to reduce current consumption to near zero; when needed, these sections are turned on, requiring the load current to increase to a high value—typically within a few hundred nanoseconds.

When there is a change in load current, some deviation in the regulator's output voltage is practically unavoidable. The magnitude of the deviation is affected by both the capacitane C

e

and the equivalent series resistance (ESR) R

e

of the output capacitor. The output capacitor may comprise one or more capacitors, generally of the same kind, which, when connected into a series, parallel, or series/parallel combination, provide capacitance C

e

and ESR R

e

. A smaller capacitance or a larger ESR increase the deviation. For example, for a switching voltage regulator (which delivers output current via an output inductor and which includes an output capacitor connected in parallel across the load), a change in load current ΔI

load

results in a change in the regulator's output voltage unless 1)the current delivered to the load instantaneously increases by ΔI

load

, or 2)the capacitance of the output capacitor is so large and its ESR is so small that the output voltage deviation would be negligible. The first option is impossible because the current in the output inductor cannot change instantaneously. The time required to accommodate the change in load current can be reduced by reducing the inductance of the output inductor, but that eventually requires increasing the regulator's switching frequency, which is limited by the finite switching speed and the resulting dissipation in the switching transistors. The second option is possible, but requires a very large output capacitor which is likely to occupy too much space on a printed circuit board, cost too much, or both.

For applications requiring the regulator's output voltage to meet a narrow load transient response specification, i.e., a specification which narrowly limits the allowable output voltage deviation for a bidirectional step change in load current, this inevitable deviation may be unacceptably large. As used herein, “ΔV

out

” refers to a regulator's output voltage deviation specification, as well as to peak-to-peak output voltage deviations shown in graphs. The most obvious solution for improving load transient response is to increase the output capacitance and/or reduce the ESR of the output capacitor. However, as noted above, a larger output capacitor (which provides both more capacitance and lower ESR) requires more volume and more PC board area, and thereby more cost.

One approach to improving load transient response is shown in

FIG. 1. A

switching voltage regulator

10

includes a push-pull switch

12

connected between a supply voltage V

in

and ground, typically implemented with two synchronously switched power MOSFETs

14

and

16

. A driver circuit

18

is connected to alternately switch on one or the other of MOSFETs

14

and

16

. A duty ratio modulator circuit

20

controls the driver circuit; circuit

20

includes a voltage comparator

22

that compares a sawtooth clock signal received from a clock circuit

24

and an error voltage received from an error signal generating circuit

26

. Circuit

26

typically includes a high-gain operational amplifier

28

that receives a reference voltage V

ref

at one input and a voltage representative of the output voltage V

out

at a second input, and produces an error voltage that varies with the difference between V

out

and the desired output voltage. The regulator also includes an output inductor L connected to the junction between MOSFETs

14

and

16

, an output capacitor

30

, shown represented as a capacitance C

e

in series with an ESR R

e

, and a resistor R, connected between the output inductor and the output capacitor. A load

32

is connected across the output capacitor.

In operation, MOSFETs

14

and

16

are driven to alternately connect inductor L to V

in

and ground, with a duty ratio determined by duty ratio modulator circuit

20

; the duty ratio varies in accordance with the error voltage produced by error amplifier

28

. The current in inductor L flows into the parallel combination of output capacitor

30

and load

32

. The impedance of capacitor

30

is much smaller at the switching frequency than that of load

32

, so that the capacitor filters out most of the AC components of the inductor current and virtually all of the direct current is delivered to load

32

.

Without series resistor R

s

, the voltage fed back to circuit

26

is equal to V

out

, and the regulator's response to a step change in load current is that of a typical switching regulator; a regulator's output voltage V

out

is shown in

FIG. 2

a

for a step change in load current I

load

shown in

FIG. 2

b

. Because the current in L cannot change instantaneously, a sudden increase in I

load

causes V

out

to deviate downward; the control loop eventually forces V

out

back to a nominal output voltage V

nom

. Similarly, when I

load

later steps down, V

out

deviates upward before returning to V

nom

. The total deviation in output voltage ΔV

out

for a step change in load current is determined by the difference between the two voltage deviations. If the regulator is subject to a narrow load transient response specification, the total deviation may exceed the tolerance allowed.

Connecting resistor R

s

in series with inductor L (at an output terminal

34

) can reduce ΔV

out

; one possible response with R

s

included is shown in

FIG. 3

a

for a step change in load current shown in

FIG. 3

b

. With R

s

in place, the control loop no longer causes V

out

to recover to V

nom

; rather, V

out

recovers to a voltage given by the voltage at terminal

34

minus the product of ΔI

load

and R

s

. That is, the steady-state value of V

out

for a light load will be higher than it is for a heavy load, by ΔI

load

*R

s

. Making R

s

approximately equal to the ESR of the output capacitor can provide a somewhat narrower ΔV

out

than can be achieved without the use of R

s

.

One disadvantage of the circuit of

FIG. 1

is illustrated in

FIGS. 4

a

and

4

b

. In this case, the load current (

FIG. 4

b

) steps back down before V

out

(

FIG. 4

a

) has settled to a steady-state value. With V

out

higher than it was in

FIG. 3

a

at the instant I

load

begins to fall, the peak of the upward V

out

deviation is also higher, making the overall deviation ΔV

out

greater than it would otherwise be. This larger deviation means that to satisfy a particular narrow output voltage deviation specification, regulator

10

must use an output capacitor with larger capacitance or smaller ESR. This can be achieved either by using more individual capacitors of a given type, or by using a different type of capacitor. Either solution (and because the cost of a capacitor is approximately inversely proportional to its ESR) has an associated cost, which may make meeting the voltage deviation. specification prohibitively expensive.

Another disadvantage of the

FIG. 1

circuit is the considerable power dissipation required of series resistor R

s

. For example, assuming an R

s

of 5 mΩ and a maximum load current of 14.6 A, the dissipation in R

s

will be 1.07 W.

An approach to improving a regulator's load transient response using a different control principle is disclosed in D. Goder and W. R. Pelletier, “V

2

Architecture Provides Ultra-Fast Transient Response in Switch Mode Power Supplies”, HFPC Power Conversion, September 1996 Proceedings, pp. 19-23. The regulator described therein includes a push-pull switch, a driver circuit, an error amplifier, and an output inductor and capacitor similar to those shown in

FIG. 1. A

signal representing the regulator's output voltage is fed to both the error amplifier and to a voltage comparator which also receives the error amplifier's output. When the regulator's output voltage exceeds the output of the error amplifier, the comparator's output goes high and triggers a monostable multivibrator, which turns off the upper switching transistor for a predetermined time interval.

The transient response of this circuit is designed to be faster than that of the circuit in

FIG. 1. A

load current step immediately changes the voltage at the comparator, bypassing the sluggishness of the error amplifier and thereby shortening the response time. However, even with a shorter response time, the shape of the response trace still resembles that shown in

FIG. 3

a

, with little to no improvement in the magnitude of ΔV

out

.

Another switching regulator is described in L. Spaziani, “Fueling the Megaprocessor—a DC/DC Converter Design Review Featuring the UC3886 and UC3910”, Unitrode Application Note U-157, pp. 3-541 to 3-570. This regulator employs a control principle known as “average current control”, in which regulation is achieved by controlling the average value of the current in the output inductor. A resistor is connected in series with the regulator's output inductor, and a current sense amplifier (CSA) is connected across the resistor to sense the inductor current. The output of the CSA is fed to a current error amplifier along with the output of a voltage error amplifier that compares the regulator's output voltage with a reference voltage. A comparator receives the output of the current error amplifier at one input and a sawtooth clock signal at its other input; the comparator produces a pulse-width modulated output to drive a push-pull switch via a driver circuit.

In operation, an increase in load current causes an output voltage decrease, increasing the error signal from the voltage error amplifier. This increases the output from the current error amplifier, which in turn causes the duty ratio of the pulses produced by the comparator to increase. This increases the current in the output inductor to bring up the output voltage. The voltage error amplifier is configured to provide a non-integrating gain, and this, in combination with average current control, gives the regulator a finite and controllable output resistance. This permits the output voltage to be positioned, similar to the way in which series resistor R

s

affected the response of the

FIG. 1

circuit. However, as is clearly shown in

FIG. 32

of the reference, the obtainable response again resembles that of

FIG. 3

a

, with a ΔV

out

that may still exceed a narrow output voltage deviation specification.

SUMMARY OF THE INVENTION

A method and circuit are presented which overcome the problems noted above, enabling a voltage regulator to provide an optimum response to a large bidirectional load transient while using the smallest possible output capacitor.

The invention is intended for use with a voltage regulator for which output capacitor size and cost are preferably minimized, which must maintain its output voltage within specified boundaries for large bidirectional step changes in load current. These goals are achieved with a technique referred to herein as “optimal voltage positioning”, which keeps the output voltage within the specified boundaries while employing an output capacitor that has a combination of the largest possible ESR and lowest possible capacitance that ensures that the peak-to-peak voltage deviation for a bidirectional step change in load current is no greater than the maximum allowed. This output capacitor is identified herein as the “smallest possible output capacitor”.

The invention can be used with regulators subject to design requirements that specify a minimum time T

min

between load transients, and with those for which no T

min

is specified. When no T

min

is specified, optimal voltage positioning is achieved by compensating the regulator to ensure a response that is flat after the occurrence of the peak deviation—referred to herein as an “optimum response”—which enables the output voltage to remain within specified limits regardless of how quickly load transients occur. When a time T

min

is specified, the invention provides a method which enables the smallest possible output capacitor to be determined which enables the output voltage to remain within specified boundaries. The invention is applicable to both switching and linear voltage regulators.

Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1

is a schematic diagram of a prior art switching voltage regulator circuit.

FIGS. 2

a

and

2

b

are plots of output voltage and load current, respectively, for a prior art voltage regulator circuit which does not include a resistor connected between its output terminal and its output capacitor.

FIGS. 3

a

and

3

b

are plots of output voltage and load current, respectively, for a prior art voltage regulator circuit which does include a resistor connected between its output terminal and its output capacitor.

FIGS. 4

a

and

4

b

are plots of output voltage and load current, respectively, for a prior art voltage regulator circuit in which the load current steps down before the output voltage has settled in response an upward load current step

FIG. 5

a

is a plot of a step change in load current.

FIG. 5

b

is a plot of the output current injected by a voltage regulator toward the parallel combination of output capacitor and output load in response to the step change in load current shown in

FIG. 5

a.

FIG. 5

c

is a plot of a voltage regulator's output capacitor current in response to the step change in load current shown in

FIG. 5

a.

FIG. 5

d

is a plot of a voltage regulator's output voltage when the capacitance of its output capacitor C

e

is greater than a critical capacitance C

crit

.

FIG. 5

e

is a plot of a voltage regulator's output voltage when the capacitance of its output capacitor C

e

is less than a critical capacitance C

crit

.

FIGS. 6

a

and

6

b

are plots of output voltage and load current, respectively, for a voltage regulator per the present invention which employs an output capacitance C

e

that is equal to or greater than a critical capacitance C

crit

.

FIGS. 7

a

and

7

b

are plots of output voltage and load current, respectively, for a voltage regulator per the present invention which employs an output capacitance C

e

that is less than a critical capacitance C

crit

.

FIG. 8

is a block/schematic diagram of an embodiment of a voltage regulator per the present invention.

FIG. 9

is a schematic diagram of one possible implementation of the voltage regulator embodiment shown in FIG.

8

.

FIGS. 10

a

and

10

b

are simulated plots of load current and output voltage, respectively, for a voltage regulator per FIG.

9

.

FIG. 11

is a schematic diagram of an alternative implementation of the voltage error amplifier shown in FIG.

9

.

FIG. 12

is a block/schematic diagram of another embodiment of a voltage regulator per the present invention.

FIG. 13

is a schematic diagram of one possible implementation of the voltage regulator embodiment shown in FIG.

12

.

FIG. 14

is a plot of output voltage and load current, respectively, for a voltage regulator subject to a requirement which specifies a minimum time T

min

between load transients and which employs optimal voltage positioning per the present invention.

FIGS. 15

a

and

15

b

, are schematic diagrams of alternative implementations of the voltage error amplifier shown in

FIG. 9

, for use in a regulator per the present invention which is subject to a requirement which specifies a minimum time T

min

between load transients.

FIG. 16

is a schematic diagram of a possible implementation of the voltage regulator embodiment shown in

FIG. 12

, for use in a regulator per the present invention which is subject to a requirement which specifies a minimum time T

min

between load transients.

FIG. 17

are plots of output voltage and load current, respectively, which illustrate an alternative voltage positioning approach per the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides a means of determining the smallest possible capacitor that can be used on the output of a voltage regulator in applications requiring large bidirectional step-like changes in load current, which enables the regulator's output voltage to remain within specified boundaries for a given step size. A given step change in load current is identified herein as ΔI

load

, and the allowable output voltage deviation specification is identified as ΔV

out

. As used herein, the “smallest possible output capacitor” refers to the output capacitor having the smallest possible capacitance value and the largest permissible ESR value which enable the regulator to meet the ΔV

out

specification. Because the cost of a capacitor tends to be inversely proportional to its ESR and directly proportional to its capacitance, and because space is nearly always at a premium on a circuit board, the invention makes it possible for the output capacitor's cost and space requirements to be minimized.

The invention takes advantage of the realization that there is a smallest possible output capacitor that, when used with a properly configured voltage regulator, enables the regulator to meet a given ΔV

out

specification. Neglecting the effect of the output capacitor's equivalent series inductance, a step change in load current ΔI

load

causes an initial change in the output voltage of a voltage regulator that is equal to the product of the capacitor's ESR (identified herein as R

e

) and ΔI

load

; i.e., R

e

*ΔI

load

. This initial change occurs for both upward and downward load current steps. If the output capacitor's capacitance C

e

is equal to or greater than a certain “critical” value C

crit

(discussed in detail below), the output voltage deviation may not exceed the initial Re*ΔI

load

change. If C

e

is less than C

crit

, the output voltage deviation continues to increase after the initial R

e

*ΔI

load

change before beginning to recover.

Prior art regulators are typically designed to drive the output voltage back towards a nominal value after the occurrence of a load transient. Doing so, however, can result in an overall output voltage deviation ΔV

out

of up to twice R

e

*ΔI

load

: when the load current steps up, V

out

drops from the nominal voltage by Re*ΔI

load

. If the load current stays high long enough, the regulator drives V

out

back toward the nominal voltage. Now when the load current steps back down, V

out

deviates up by R

e

*ΔI

load

, resulting in a total output voltage deviation of 2(Re*ΔI

load

)

Having recognized the adverse implications of prior art regulator control methods on the magnitude of ΔV

out

, it was realized that “optimal voltage positioning”, which allows V

out

to increase to the maximum voltage allowed by the ΔV

out

specification in response to a load transient that reduces the load current, and to decrease to the minimum voltage allowed by the ΔV

out

specification in response to a load transient that increases the load current, enables the smallest possible output capacitor to be used while still meeting the regulator's ΔV

out

specification.

The method and circuits described herein explain how optimal voltage positioning is achieved for two primary cases. In the first case, the regulator is not subject to a specification that defines a minimum time between load transients. This situation calls for the generation of an “optimum load transient response”, which remains “flat” at the upper voltage deviation boundary after a downward load current step, and remains flat at the lower voltage deviation boundary after an upward load current step. In the second case, the regulator is subject to a specification that defines a minimum time T

min

between load transients. Here, the invention prescribes a method which a enables the smallest possible output capacitor to be determined which enables the output voltage to remain within the specified boundaries, without requiring the response to remain flat after a load transient. As used herein, a “flat” response refers to a response that is substantially flat, exclusive of any ripple voltage that may exist. Note that in practical switching regulators, the ripple voltage that causes a deviation from the “flat” voltage is typically much smaller than the peak deviation.

The first case, in which the regulator is not subject to a T

min

specification and a flat response is desired, is discussed first. A number of steps must be performed to achieve the goal of providing the optimum load transient response and thereby identifying the smallest possible capacitor which enables a given ΔV

out

specification to be met. A maximum ESR R

e(max)

is first determined for the output capacitor that will be employed by a voltage regulator subject to a specified voltage deviation specification ΔV

out

for a bidirectional step change in load current ΔI

load

. In accordance with Ohm's Law, R

e(max)

is given by: R

e(max)

=ΔV

out

/ΔI

load

; if the output capacitor's R

e

is any greater than R

e(max)

, the initial deviation in V

out

for a step change in load current equal to ΔI

load

is guaranteed to exceed ΔV

out

.

The next step is to determine the “critical” capacitance value C

crit

mentioned above. The critical capacitance is the amount of capacitance that, when connected in parallel across a load driven by a voltage regulator (as the regulator's output capacitor), causes the output voltage to have a zero slope—i.e., to become flat after the initial R

e

*ΔI

load

change—when the current injected by the regulator towards the parallel combination of load and output capacitor ramps up (or down) with the maximum slope allowed by the physical limitations of the regulator. The maximum slope allowed by the physical limitations of the regulator is referred to herein as the “maximum available slope”.

The critical capacitance C

crit

is given by:

C

crit

=ΔI

load

/mR

e(max)

(Eq. 1)

where ΔI

load

is the largest expected load current step, R

e(max)

is the maximum allowable output capacitor ESR (calculated above), and m is a slope value associated with the current injected toward the parallel combination of the output capacitor and output load; m and the method of determining its value are discussed below.

The slope parameter m is illustrated in

FIGS. 5

a

-

5

c

.

FIG. 5

a

depicts the load current waveform for an upward step.

FIG. 5

b

shows the current injected by the regulator toward the parallel combination of output capacitor and output load when the regulator produces output current at the maximum available slope m.

FIG. 5

c

shows the current in the output capacitor, which is equal to the difference between the load current and the injected current.

FIGS. 5

d

and

5

e

illustrate how the size of a regulator's output capacitor affects V

out

when its capacitance C

e

is greater than C

crit

(

FIG. 5

d

) and less than C

crit

(

FIG. 5

e

), and the regulator injects a current toward the parallel combination of capacitor and load with the maximum available slope. When C

e

>C

crit

, V

out

begins to recover immediately after the occurrence of the initial ΔI

load

R

e

change. However, when C

e

<C

crit

, the output voltage deviation continues to increase after the initial ΔI

load

R

e

change, before eventually recovering.

The slope value m for a given regulator depends on its configuration. In general, m is established by:

1)determining the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔI

load

,

2) determining the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔI

load

. A step decrease in load current results in an injected current which has a negative slope. For this step, then, the “minimum available slope . . . for a step decrease in load current” is equal to the most negative slope,

3) determining which of the two absolute values is smaller—this is the “worst case” maximum available slope. The smaller of the two absolute values is the value m which is to be used in the equations found herein.

In a switching regulator, the worst-case maximum available slope m is clearly defined by its input voltage V

in

, its output voltage V

out

, and the inductance L of its output inductor. For example, for a buck-type voltage regulator, m can be determined in accordance with the following: when V

out

is less than V

in

−V

out

, m is given by m=V

out

/L. When V

out

is greater than V

in

−V

out

, m is given by m=(V

in

−V

out

)/L.

For linear voltage regulators, the worst-case maximum available slope is not as clearly defined. It will depend on a number of factors, including the compensation of its voltage error amplifier, the physical characteristics of its semiconductor devices, and possibly the value of the load current as well.

The two optimum load transient responses achievable with the present invention are depicted in

FIGS. 6 and 7

.

FIG. 6

a

depicts the optimum load transient response to a bidirectional step in load current shown in

FIG. 6

b

, for a properly configured regulator when the capacitance C

e

of its output capacitor is equal to or greater than C

crit

. Because C

e

is equal to or greater than C

crit

, the maximum output voltage deviation is limited to R

e

*ΔI

load

.

FIG. 7

a

shows the optimum load transient response to a bidirectional step change in load current ΔI

load

in

FIG. 7

b

, when the capacitance of a properly configured regulator's output capacitor is less than C

crit

. After the initial step (=ΔI

load

*R

e

) caused by the capacitor's R

e

, V

out

gradually declines to a steady-state value, and then remains flat at the steady-state value until the load current steps back down. It can be shown that the peak voltage deviation ΔV

out

, in this case is given by:

ΔV

out

=ΔI

load

2

/2mC

e

+mC

e

R

e

2

/2 (Eq. 2)

where m and ΔI

load

are the same as in equation 1, and C

e

and R

e

are the capacitance and ESR, respectively, of the output capacitor employed. If a capacitor with a capacitance less than C

crit

must be used, the invention still provides a method that ensures that the peak voltage deviation given by equation 2 is not exceeded. Thus, as used herein, an “optimum response” for a regulator having an output capacitor with a capacitance greater than C

crit

is as shown in

FIG. 6

a

, in which the regulator responds to a load current step of size ΔI

load

with an initial output voltage deviation equal to ΔI

load

*R

e

, and then remaining flat until the next load current step. When the output capacitor has a capacitance less than C

crit

, an optimum response is as shown in

FIG. 7

a

, with a peak output voltage deviation given by equation 2, and then remaining flat until the next load current step.

To achieve an optimum response, first select the type of capacitor (such as Al electrolytic, ceramic, tantalum, polymer, and OS-CON (Al with an organic semiconductive electrolyte)) that will be used as the output capacitor for the voltage regulator. The selection of an output capacitor type is driven by a number of factors. For a switching regulator, one important consideration is switching frequency. Low-frequency designs (e.g., 200 kHz) tend to use Al electrolytic capacitors, medium-frequency designs (e.g., 500 kHz) tend to use OS-CON capacitors, low and medium-frequency designs for which height is restricted (as in many laptop computers) tend to use tantalum or polymer capacitors, and high-frequency designs (1 MHz and above) tend to use ceramic capacitors.

Once a capacitor type has been selected, its characteristic time constant T

c

is determined, which is given by the product of its ESR and its capacitance. Because a capacitor's ESR tends to decrease as its capacitance increases, T

c

tends to be about constant for capacitors of a given type and voltage rating. For example, a standard low-voltage (e.g., 10 V) Al electrolytic capacitor may have a characteristic time constant of, for example, 40 μs (e.g., 2 mF×20 mΩ), ceramic capacitors may have characteristic time constants of, for example, 100 ns (e.g., 10 μF×10 mΩ), and OS-CON capacitors may have characteristic time constants of, for example, 4 μs (e.g., 100 μF×40 mΩ). Note that that time constants listed here are only examples: characteristic time constants can vary widely even within a particular capacitor type. Also note that the constancy of T

c

is typically more predictable when the capacitor chosen has near the maximum available capacitance for its size and voltage rating.

With m determined as described above, next determine a critical time constant T

crit

in accordance with the following: T

crit

=ΔI

load

/m. Note that T

crit

is related to C

crit

as follows: T

crit

=C

crit

×R

e(max)

, where R

e(max)

=ΔV

out

/ΔI

load

.

If the characteristic time constant T

c

of the selected capacitor type is less than T

crit

(T

c

<T

crit

), determine a minimum capacitance in accordance with the following:

C

min

=[ΔI

load

2

/m+m(T

c

2

)]/2ΔV

out

(Eq. 3)

and use an output capacitor having a capacitance C

e

which fulfills the minimum output capacitance requirement in accordance with the following:

C

e

≧C

min

However, if the characteristic time constant T

c

of the selected capacitor type is greater than or equal to T

crit

(T

c

≧T

crit

) use an output capacitor having a capacitance C

e

in accordance with the following:

C

e

≧T

c

/(ΔV

out

/ΔI

load

)

Having selected the output capacitor, the voltage regulator needs to be configured such that its response will have the optimum shape shown in

FIG. 6

a

(if C

e

>C

crit

) or

FIG. 7

a

(if C

e

<C

crit

). If C

e

>C

crit

, the optimum response is achieved by configuring the voltage regulator such that its output impedance (including the impedance of the output capacitor) becomes resistive and equal to the ESR of the output capacitor. If C

e

<C

crit

, the optimum response is ensured only by forcing the regulator to inject current to the combination of the load and the output capacitor with the maximum available slope until the peak deviation is reached. For this case an optimum output impedance cannot be defined because the regulator operates in a nonlinear mode for part of the response, but the output response can still be designed to be approximately optimal.

One embodiment of a voltage regulator per the present invention is shown in

FIG. 8. A

controllable power stage

50

is characterized by a transconductance g and produces an output V

out

at an output node

52

in response to a control signal received at a control input

53

; power stage

50

drives a load

54

. An output capacitor

56

is connected in parallel across the load, here shown divided into its capacitive C

e

and ESR R

e

components. A feedback circuit

58

is connected between output node

52

and control input

53

.

Feedback circuit

58

can include, for example, a voltage error amplifier

59

connected to receive a signal representing output voltage V

out

at a first input

60

and a reference voltage at a second input, and producing an output

62

which varies with the differential voltage between its inputs. For the embodiment shown in

FIG. 8

, an optimum load transient response—i.e., per

FIG. 6

a

if capacitor

56

is equal to or greater than C

crit

and per

FIG. 7

a

if capacitor

56

is less than C

crit

—is achieved by compensating voltage error amplifier

59

such that its gain K(s) is given by:

K(s)=−(1/gR

o

)(1/(

1+sR

e

C

e

)) (Eq. 4)

where g is the transconductance of the controllable power stage

50

, C

e

and R

e

are the capacitance and ESR of output capacitor

56

, respectively, s is the complex frequency, and R

o

is a quantity given by:

R

o

=R

e

, if C

e

≧C

crit

, or (Eq. 5)

R

o

=(ΔI

load

/2mC

e

)+(mC

e

R

e

2

/2ΔI

load

), if C

e

<C

crit

(Eq. 6)

where C

e

and R

e

are the capacitance and ESR of output capacitor

56

, respectively, m is as defined above in connection with the determination of C

crit

, and ΔI

load

is the largest load current step which the regulator is designed to accommodate.

The value of R

o

defined in equations 5 and 6 is a measure of the peak voltage deviation of the regulator. When C

e

is greater than or equal to C

crit

, and the gain K(s) of voltage error amplifier

59

is as defined in equation

4

, the combined output impedance of the regulator and the output capacitor

56

will be equal to the ESR R

e

of the output capacitor. Therefore, the peak voltage deviation will be ΔI

load

*R

o

, which is equal to ΔI

load

*R

e

when C

e

>C

crit

.

When C

e

is less than C

crit

, and the gain K(s) of voltage error amplifier

59

is as defined in equation 4, the peak voltage deviation ΔV

out

will be as defined in equation 2. The system is nonlinear when C

e

is less than C

crit

, and as such the regulator cannot achieve the optimal transient response shown in

FIG. 6

a

. However, compensating voltage error amplifier

59

to yield the transfer function given by equation 4 provides a transient response that is as close to

FIG. 6

a

's ideal response as practically possible.

Controllable power stage

50

is not limited to any particular configuration. In

FIG. 8

, power stage

50

is configured to provide current-mode control; the power stage includes a current sensor

64

which has a transresistance equal to R

s

and which produces an output signal that varies with the power stage's output current, a current controller

66

which receives the output of the current sensor and the output

62

of the voltage error amplifier as inputs and produces an output

67

, and a power circuit

68

which receives output

67

from the current controller and produces output voltage V

out

in response. The invention is applicable to both linear and switching regulators: in linear regulators, power circuit

68

is a series pass transistor and current controller

66

is an amplifier. For a switching regulator, power circuit

68

can have any of a large number of topologies, containing components such as controlled switches, diodes, inductors, transformers, and capacitors. For example, a typical power circuit for a buck-type switching regulator is shown in

FIG. 1

, which includes a pair of controlled switches

14

and

16

and an output inductor L connected between the junction of the switches and the regulator's output.

The current controller

66

for a switching regulator can be of two types: instantaneous and average. Instantaneous current control has at least six different subtypes, as described, for example, in A. S. Kislovski, R. Redl, and N. O. Sokal,

Dynamic analysis of switching

-

mode DC/DC converters

, Van Nostrand Reinhold (1991), p. 102, including constant off-time peak current control, constant on-time valley current control, hysteretic control, constant frequency peak current control, constant frequency valley current control, and PWM conductance control. Instantaneous current controllers can typically change the current in the output inductor within one switching period, while changing the inductor current with average current control usually takes several periods. For this reason, instantaneous current control is preferred, but average current controllers can also be used to implement the present invention if the current-controlling loop has sufficiently fast response; however, such implementations suffer from the drawback of requiring a current error amplifier, which increases the complexity and cost of the regulator circuit.

FIG. 9

is a schematic diagram of one possible implementation of a switching voltage regulator per the present invention. In this embodiment, feedback circuit

58

includes voltage error amplifier

59

, which is made up of an operational amplifier

70

, an input resistor R

1

, a feedback resistor R

2

, and a feedback capacitor C

1

. Power circuit

68

includes a pair of switches

72

and

74

connected between V

in

. and ground, with the junction between the switches connected to an output inductor L. Current sensor

64

is implemented with a resistor

75

having a resistance R

s

, connected in series between inductor L and output node

52

.

Current controller

66

is a constant off-time peak current control type controller, which includes a voltage comparator

76

with its inputs connected to the inductor side of resistor

75

and to the output of a summing circuit

78

. Summing circuit

78

produces a voltage at its output Z that is equal to the sum of the voltages at its X and Y inputs; X is connected to receive the output

62

of voltage error amplifier

59

, and Y is connected to the output side of current sense resistor

75

. Summing circuit

78

can also include a gain stage

80

having a fixed gain k, connected between the output of voltage error amplifier

59

and its X input; the gain k should be significantly less than unity—e.g. 0.01—if the output voltage V

out

and the reference voltage V

ref

are expected to be nearly equal. The output of comparator

76

is connected to a monostable multivibrator

82

, the output of which is fed to a driving circuit

83

via a logic inverter

84

. Driving circuit

83

includes upper driver

86

and lower driver

88

, which drive switches

72

and

74

, respectively, of power circuit

68

.

The operation of the switching regulator circuit of

FIG. 9

is as follows: when the product of the current in inductor L and the resistance R

s

of resistor

75

exceeds the error voltage produced by voltage error amplifier

59

, the output of voltage comparator

76

goes high and triggers monostable multivibrator

82

. Logic inverter

84

inverts the high output of multivibrator

82

, which causes upper driver

86

to turn off upper switch

72

and lower driver

88

to turn on lower switch

74

. As a result, the current in inductor L begins to decrease. Monostable multivibrator

82

has an associated timing interval T

off

; after timing interval T

off

has expired, the states of switches

72

and

74

reverse, and the current in inductor L begins to increase. When the inductor current exceeds the threshold of comparator

76

, the cycle repeats. Output voltage regulation is achieved by changing the threshold of voltage comparator

76

with the error voltage from error amplifier

59

via summing circuit

78

.

When configured per the present invention, the switching voltage regulator of

FIG. 9

provides a nearly optimum load transient response, as illustrated in the simulated plots of load current I

load

and output voltage V

out

shown in

FIGS. 10

a

and

10

b

, respectively. In this example, the load current changes from 0.56 A to 14.56 A and back (ΔI

load

=14 A) and the allowable output voltage deviation ΔV

out

is 0.07 V. The parameter values of the switching regulator are as follows:

V

in

=5 V; V

ref

=2.8 V; L=3 μH; C

e

=10 mF; R

e

=5 mΩ; R

s

=5mΩ; k=0.01; ΔI

load

=14 A; ΔV

out

=0.07 V

Note that the output capacitor's R

e

is within the acceptable range defined by R

e(max)

=ΔV

out

/ΔI

load

, equal here to 0.07V/14A=5 mΩ.

For this example, V

out

(˜V

ref

) is greater than V

in

−V

out

, so that m is given by:

m=(V

in

−V

out

)/L=[(5-2.8)V]/3 μH=0.733 A/μs.

From equation 1, the critical capacitance C

crit

is given by:

C

crit

=14 A/[(0.733 A/μs) (5 mΩ)]=3.818 mF.

Since 10 mF is greater than 3.818 mF, C

e

is greater than C

crit

and thus R

o

(as given by equation 5) is to be made equal to R

e

. This is accomplished by compensating voltage error amplifier

59

as needed to obtain the transfer function of equation 4. When voltage error amplifier

59

is implemented as shown in

FIG. 9

, this compensation is achieved when the following two equations are satisfied:

k*(R

2

/R

1

)=1/(g*R

o

) (Eq. 7)

R

e

*C

e

=R

2

*C

1

(Eq. 8)

The value of g is determined by the transresistance of current sensor

64

and the implementation of current controller

66

. If the first stage of the current controller is a voltage comparator (as here), g is equal to the reciprocal of the transresistance of current sensor

64

. When the current sensor is implemented with a resistor, the transresistance is simply the resistor's resistance (thus, g=1/R

s

in this example). In this example, equations 7 and 8 are satisfied when the following component values are used: R

1

=1kΩ; R

2

=100 kΩ; C

1

=500 pF. As the waveform of

FIG. 10

b

shows, the output voltage response corresponds to a resistive output impedance of 5 mΩ, which is also equal to the ESR of the output capacitor.

An alternative implementation of feedback circuit

58

is shown in

FIG. 11

, in which voltage error amplifier

59

is implemented using a transconductance amplifier

90

. A transconductance amplifier is characterized by an output current that is proportional to the voltage difference between its non-inverting and inverting inputs; the proportionality factor between the output current and the input difference voltage is the amplifier's transconductance g

m

. The voltage gain of a transconductance-type voltage error amplifier is equal to the product of the impedance connected to the output of transconductance amplifier

90

and the transconductance gm.

The voltage error amplifier implementations shown in

FIGS. 9 and 11

are equivalent when the following three equations are satisfied:

g

m

[(R

3

R

4

)/(R

3

+R

4

)]=R

2

/R

1

(Eq. 9)

V

cc

[R

4

/(R

3

+R

4

)]=V

ref

(Eq. 10)

C

2

[(R

3

R

4

)/(R

3

+R

4

)]=C

1

R

2

(Eq. 11)

Thus, the transfer function defined in equation 4 is obtained for voltage error amplifier

59

shown in

FIG. 11

when each of equations 9, 10 and 11 are satisfied.

The invention is not limited to use with current-mode controlled voltage regulators that include a voltage error amplifier. One possible embodiment of the invention which uses neither current-mode control nor a voltage error amplifier is shown in FIG.

12

. In this embodiment, a controllable power stage

100

produces an output voltage V

out

in accordance with the voltage difference between a pair of inputs

102

,

104

; the power stage includes a power circuit

68

controlled by a fast voltage controller

105

which receives the inputs. In a switching voltage regulator, fast voltage controller

105

is characterized by rapidly increasing the duty ratio of the pulse train at its output when an appreciable positive voltage difference appears between inputs

102

and

104

. In a linear voltage regulator, fast voltage controller

105

would typically be implemented with a wide-band operational amplifier.

The embodiment of

FIG. 12

also includes a current sensor

106

having a transresistance R

s

connected in series between the output of the power stage

100

and output node

52

, which produces an output that varies with the regulator's output current. The current sensor's output is connected to one input of a summing circuit

108

, and a second summing circuit input is connected to output node

52

. The summing circuit produces an output voltage equal to the sum of its inputs, which is connected to input

102

of power stage

100

.

Input

104

of power stage

100

is connected to a node

110

located at the junction between a pair of impedances Z

1

and Z

2

, which are connected in series between output node

52

and a voltage reference

112

. When a regulator is configured as shown in

FIG. 12

, an optimal transient response is obtained by arranging the ratio between the two impedances Z

2

/Z

1

in accordance with the following:

Z2/Z1=[R

o

(1+sR

e

C

e

)−R

s]/R

s

(Eq. 12)

where R

o

is defined by equations 5 and 6, R

s

is the resistance of current sensor

106

, and R

e

and C

e

are the ESR and capacitance of the output capacitor

56

employed.

One implementation of the voltage regulator embodiment of

FIG. 12

is shown in FIG.

13

. Fast voltage controller

105

is implemented with a hysteretic comparator

130

, the output of which is connected to a driving circuit

132

which includes an upper driver

134

and a lower driver

136

. Power circuit

68

includes an upper switch

138

and a lower switch

140

, which are driven by drivers

134

and

136

, respectively, and an output inductor L is connected to the junction between the switches. The hysteretic comparator

130

monitors the output voltage and turns off the upper switch when the output voltage exceeds the upper threshold of the comparator. The upper switch is turned on again when the output voltage drops below the comparator's lower threshold.

Current sensor

106

and summing circuit

108

are implemented with a series resistor

142

having a resistance R

s

. Impedance Z

1

is implemented with a parallel combination of a capacitor C

4

and a resistor R

6

, and impedance Z

2

is implemented with a resistor R

7

.

For the output impedance of the switching regulator of

FIG. 13

to be equal to the resistance R

o

, the ratio of the resistances of resistors R

6

and R

7

must be given by:

R

7

/R

6

=(R

o

−R

s

)/R

s

.

and the product of the capacitance of capacitor C

4

and the resistance of resistor R

7

must be given by:

C

4

R

7

=C

e

[(R

o

R

e

)/R

s

].

As is readily apparent to those skilled in the art of voltage regulator design, the voltage regulator embodiments and implementations discussed above are merely illustrative. Many other circuit configurations could be employed to achieve the invention's goals of optimum transient response and smallest possible output capacitor, as long as the inventive method is practiced as described herein.

The second primary situation covered by the invention, in which the regulator is subject to a specification that defines a minimum time T

min

between load transients, presents a simpler case. In the first case, the need to stay within a particular ΔV

out

specification regardless of the time between load transients dictated that the response remain flat after a load transient. However, when it is known that there will be at least a minimum time T

min

between load transients, it may no longer be necessary that the response remain flat. Here, it is only necessary that, in response to a load transient, the output voltage waveform: 1)remains within the ΔV

out

specification, and 2)settles before the end of time T

min

. Optimal voltage positioning in this case is achieved with the waveform shown in

FIG. 14

, which achieves the two goals stated above with the smallest possible output capacitor.

A regulator which is subject to a T

min

specification is implemented with a design that is virtually identical to those defined above. If the regulator settles within minimum time T

min

after a load transient, then only a DC shift in output voltage is needed—to the highest allowable output voltage boundary when a maximum step decrease in load current occurs, and to the lowest allowable output voltage boundary when a maximum step increase in load current occurs. However, because a flat response is no longer required, the compensation capacitor found in the designs above can be omitted.

This illustrated in

FIG. 15

a

, which is a schematic of a feedback circuit

58

′ for use in the regulator of FIG.

9

. Feedback circuit

58

′ includes a voltage error amplifier

59

′; circuits

58

′ and

59

′ are alternative embodiments of feedback circuit

58

and voltage error amplifier

59

in the regulator of FIG.

9

. Voltage error amplifier

59

′ is identical to voltage error amplifier

59

, except for the exclusion of capacitor C

1

. As above, voltage error amplifier

59

′ must provide the transfer function given in equation 4 to enable the smallest possible output capacitor to be employed. Note that if the regulator's settling time is longer than T

min

, an optimal load transient response must be provided—which requires the presence of capacitor C

1

. A regulator's settling time is approximately given by 6*R

e

*C

e

, where R

e

and C

e

are the ESR and capacitance of the output capacitor.

Another alternative embodiment of feedback circuit

58

and voltage error amplifier circuit

59

is shown in

FIG. 15

b

, in which voltage error amplifier

59

′ is implemented with a transconductance amplifier. This embodiment, which can be employed if the regulator settles within minimum time T

min

, after a load transient, is identical to that shown in

FIG. 11

except for the exclusion of capacitor C

2

.

One more possible implementation of a regulator subject to a T

min

specification is shown in FIG.

16

. This implementation is identical to that shown in

FIG. 13

, except that capacitor C

4

has been excluded from impedance Z

1

′—which is permitted as long as the regulator settles within minimum time T

min

after a load transient. Otherwise, an optimal response must be provided as described above.

The inventive method described herein can be presented as a general design procedure, which is applicable to: 1)regulators that are subject to a T

min

specification, 2) regulators which are not subject to a T

min

specification, 3) linear voltage regulators, and 4)switching voltage regulators, and which accommodates the use of output capacitors having capacitances that are both greater than and less than the critical capacitance defined above. This design procedure can be practiced in accordance with the following steps:

1. Select a type of capacitor (such as Al electrolytic, ceramic, tantalum, polymer, and OS-CON capacitors) to be used as the output capacitor for a voltage regulator required to maintain a regulated output voltage within a specified voltage deviation specification ΔV

out

for a step change in load current ΔI

load

.

2. Determine the characteristic time constant T

c

for the selected capacitor type, which as explained above, is defined as the product of its ESR and its capacitance. 3. Determine the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔI

load

, and the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔI

load

This is the done as described above in connection with equation 1.

4. Determine which of the two absolute values is smaller. The smaller absolute value is identified as m.

5. Determine a critical time constant T

crit

in accordance with the following: T

crit

=ΔI

load

/m. Note that T

crit

is related to C

crit

as follows: T

crit

C

crit

R

e(max)

, where R

e(max)

=ΔV

out

/ΔI

load

.

6. If T

c

<T

crit

, determine a minimum capacitance in accordance with the following:

C

min

=[ΔI

load

2

/m+m(T

c

2

)]/2ΔV

out

and use an output capacitor having a capacitance C

e

which fulfills the minimum output capacitance requirement in accordance with the following:

C

e

≧C

min

7. If T

c

≧T

crit

, use an output capacitor having a capacitance C

e

in accordance with the following:

C

e

>T

c

/(ΔV

out

/ΔI

load

)

Note that though output impedance is not explicitly discussed in the design procedure above, the procedure does yield a regulator with the output impedance needed to practice optimal voltage positioning as described herein.

Note that time constant T

c

(or its constituent factors C

e

and R

e

) is not a precisely defined quantity for a particular capacitor type. A number of factors, including manufacturing tolerances, case size, temperature and voltage rating, can all affect T

c

. Thus, in a practical design, the parameter T

c

used in the calculations should be considered as an approximate value, and a number of iterations through the design procedure may be necessary.

The inventive method is restated below, specifically directed to the design of a buck-type switching voltage regulator employing current-mode control, which produces an optimum load transient response while minimizing the size of the regulator's output capacitor. This type of regulator has a pair of switches connected in series between an input voltage V

in

and ground, with the junction between the switches connected to an output inductor. The switches are driven to alternately connect the inductor to V

in

and to ground. Note that the design procedure below is applicable only for the case when C

e

>C

crit

, and as such it achieves the optimum load transient response shown in

FIG. 6

a

; a buck-type regulator employing current-mode control could also use an output capacitor having a capacitance less than C

crit

—and thereby achieve the optimum response shown in

FIG. 7

a

—by following the design procedure described above. The design procedure applicable when C

e

>C

crit

can be practiced by following the steps below:

1. Calculate a maximum ESR R

e(max)

for the regulator's output capacitor in accordance with the following: R

e

(fix) ΔV

out

/ΔI

load

.

2. Determine a minimum inductance L

min

for the regulator's output inductor in accordance with the following: L

min

=(V

out

T

off

)/I

ripple,p-p

, where T

off

is the off time of the switch which connects the output inductor to V

in

, and I

ripple,p-p

is the maximum allowable peak-to-peak output ripple current.

3. Use an output inductor with an inductance L

1

which is equal to or greater than L

min

.

4. Determine a minimum capacitance C

min

for the output capacitor in accordance with the following:

if V

out

<(V

in

−V

out

): C

min

=ΔI

load

/[R

e(max)

(V

out

/L

1

)];

if V

out

>V

in

−V

out

: C

min

=ΔI

load

/[R

e(max)

((V

in

−V

out

)/L

1

)].

5. Use an output capacitor having a capacitance C

e

about equal to C

min

and an ESR R

e

about equal to R

e(max)

6. Arrange the output impedance of the regulator to be about equal to R

e

. This step is accomplished by making the transfer function for the regulator's feedback circuit correspond with equation 4, in accordance with the methods described above.

An alternative voltage positioning approach may be considered when reduced power consumption and use of the smallest possible output capacitor are both design goals. In this instance, having the output at the highest possible voltage allowed by the ΔV

out

specification after a downward step in load current can increase the average power consumed by the device whose supply voltage is provided by the regulator.

The alternative voltage positioning approach described below reduces the average power consumption when compared with the method described above. The approach is applicable when 1)the regulator's input voltage is more than twice as large as its output voltage (an increasingly common occurrence as regulators are called upon to deliver supply voltages of around 1.5-2 V while being powered by anywhere from 5-20 V), and 2)the output capacitance is below the critical value C

crit

. Under these conditions, the size of the output voltage's downward deviation V

1

for a maximum step increase in load current will be smaller than the peak upward deviation V

2

for a maximum step decrease in load current. This asymmetry is the result of the difference in the inductor current slope. For example, if V

in

=12 V, V

out

=1.6 V, ΔI

load

=10A, L=500 nH, C

e

=100 μF, and R

e

=1 mohm, the downward deviation V

1

will be 25 mV and the upward deviation V

2

will be 156 mV (from equation 1). Assuming that the C

e

value is obtained using the design procedure described herein (and the feedback loop compensated accordingly), the difference between the output voltage at zero load and at full load will be 156 mV. Assume further that the maximum peak-to-peak output voltage deviation ΔV

out

is 156 mV and the regulator's nominal output voltage is 1.6 volts. If the 156 mV wide band is symmetrically positioned around 1.6 V, then the minimum output voltage (at 10A load) is 1.6-(0.156/2)=1.522 V, and the maximum voltage (at 0A load) is 1.6+0.156/2=1.678 V.

Per the novel voltage positioning technique described above, the regulator would be arranged to make the output voltage settle at the maximum allowable voltage after the occurrence of the maximum downward load current step. Under this alternative approach, the output voltage is made to settle at less than the maximum allowed after a downward load current step. This is illustrated in the plot shown in FIG.

17

. Assume that, for this example, the output voltage is positioned such that at full load the static output voltage is 1.522 V, and at zero load the static output voltage is 1.6-0.156/2+0.025=1.547 V. When the load current steps down to zero, the output voltage deviates upward by T

2

=156 mv to 1.678 V, but after reaching the peak it returns back to 1.547 V. When the load steps back up, the output voltage deviates downward by V

1

=25 mV, from 1.547 V to 1.522 V. Because the output voltage remains between 1.522 and 1.678, compliance with the ΔV

out

specification is maintained.

The benefit of reducing the upper static limit, optimally to the sum of the allowed minimum voltage and the peak deviation V

1

caused by the application of the full load, is that the average power consumed by the device being powered by the regulator may be reduced. Assume that the device is a microprocessor which does not always switch between zero current and full current, but rather sometimes draws a current somewhere between the two limits. At full load or at zero load there is no difference in power consumption between the two cases of static voltage positioning, but at half load the difference can be quite significant. In the above example, the difference is 328 mW, or about 4% of the total consumed power. If the regulator is powered by a battery, the 4% reduction serves to extend the life of the battery by about 4%.

Voltage positioning which satisfies the combined goals of reduced power consumption and using the smallest possible output capacitor can be achieved with the circuits shown in

FIGS. 8

or

12

. For the embodiment shown in

FIG. 8

, the gain K(s) of the voltage error amplifier

59

must be:

K(s)=−(1/gR

o1

)(1/(1+sR

e

C

e

)) (Eq. 13)

where g is the transconductance of the controllable power stage

50

, C

e

and R

e

are the capacitance and ESR of output capacitor

56

, respectively, s is the complex frequency, and R

o1

is a quantity given by:

R

o1

=(ΔI

load

/2m

1

C

e

)+(m

1

C

e

R

e

2

/2ΔI

load

) 14)

where C

e

and R

e

are the capacitance and ESR of output capacitor

56

, respectively, m

1

is the absolute value of the largest slope of the current injected toward the parallel combination of output capacitor

56

and load

54

(rather than the smaller of the two slopes, as is used in equation 6), and ΔI

load

is the largest load current step which the regulator is designed to accommodate.

Similarly, for the embodiment shown in

FIG. 12

, the ratio between the two impedances Z

2

/Z

1

must be as follows:

Z

2

/Z

1

=[R

o1

(1+sR

e

C

e

)−R

s

]/R

s

(Eq. 15)

where R

o1

is given in equation 14.

In both implementations, the output capacitor must be selected as follows: choose a capacitor type that has a characteristic time constant T

c

less than the critical time constant T

crit

. Determine the minimum capacitance C

min

in accordance with:

C

min=[ΔI

load

2

/m+m(T

c

2

)]/2ΔV

out

(Eq. 16)

(where m is as defined above in connection with the determination of C

crit

) and use an output capacitor having a capacitance C

e

which fulfills the minimum output capacitance requirement in accordance with the following:

C

e

≧C

min

After selecting the output capacitor and designing the compensation per equation 14 or 15, offset the output voltage such that at full load, the output voltage is at the minimum allowed voltage. Offsetting the output voltage can be implemented by several methods: for example, by adjusting the reference voltage, by connecting a resistor between the inverting input of the voltage error amplifier (

70

in

FIG. 9

or

90

in

FIG. 11

) and ground, or by inserting a resistive divider between the junction of L and R

s

and the inverting input

102

of the hysteretic comparator in FIG.

13

.

While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. For example, a trivial alternate embodiment of a buck-type switching regulator has the second switch replaced with a rectifier diode. Accordingly, it is intended that the invention be limited only in terms of the appended claims.

Claims

1. A method of enabling a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for bidirectional step changes in load current of a specified maximum magnitude, comprising the step of:compensating a voltage regulator which employs an output capacitor and is required to maintain a regulated output voltage within specified boundaries for bidirectional step changes in load current of a specified maximum magnitude such that, after the occurrence of a step change in load current of said specified maximum magnitude, the response of the output voltage is substantially flat after said output voltage reaches one of said specified boundaries, the output capacitor required to provide said compensation being the smallest possible output capacitor that allows the regulator's output voltage to be maintained within said specified boundaries.
2. A method of enabling a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for specified maximum bidirectional step changes in load current, with a minimum time Tmin specified between said step changes in load current, comprising the step of:compensating a voltage regulator which employs an output capacitor and is required to maintain a regulated output voltage within specified boundaries for a bidirectional step change in load current such that its output voltage substantially settles at the lowest specified output voltage boundary within a specified time Tmin in response to a specified maximum load step increase, and such that its output voltage substantially settles at the highest specified output voltage boundary within said specified time Tmin in response to a specified maximum load step decrease.
3. A method of minimizing the size of a voltage regulator's output capacitor which enables the regulator's output voltage to be maintained within a voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, comprising the steps of:selecting a type of capacitor to be used as the output capacitor for a voltage regulator connected to provide a regulated output voltage to an output load at an output node, said output capacitor to be connected in parallel across said load, said regulator required to maintain a regulated output voltage within a voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, determining the characteristic time constant Tc for the selected capacitor type, determining the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔIload and the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔIload, determining which of said absolute values is smaller, the smaller of said absolute values being a value m, determining a critical time constant Tcrit in accordance with the following: Tcrit=ΔIload/m, selecting, if Tc<Tcrit, an output capacitor having a capacitance Ce for connection across said load in accordance with Ce≧[ΔIload2/m+m(Tc2)]/2ΔVout, and selecting, if Tc≧Tcrit, an output capacitor having a capacitance Ce for connection across said load in accordance with Ce≧Tc/(ΔVout/ΔIload).
4. The method of claim 3, wherein said voltage regulator is a buck-type switching voltage regulator having an output inductor with an inductance L and which receives an input voltage Vin and produces an output voltage Vout, said value of m given by m=Vout/L if Vout is less than Vin−Vout and by (Vin−Vout)/L if Vout is greater than Vin−Vout.
5. The method of claim 3, wherein said voltage regulator includes a controllable power stage which provides current which maintains a regulated voltage at the regulator's output node in response to a signal received at a control input and a voltage error amplifier connected between said output node and said control input, said power stage having a transconductance g and said voltage amplifier having a gain K(s), the gain K(s) of said voltage error amplifier made equal to the following:K(s)=(−1/gRo) (1/(1+sReCe)) in which Re is the ESR of the output capacitor selected, s is the complex frequency, and Ro is a quantity given by:Ro=Re, if Ce≧Ccrit, or Ro=(ΔIload/2mCe)+(mCeRe2/2ΔIload), if Ce<Ccrit, where Ccrit is determined in accordance with Ccrit=ΔIload/mRe0, where Re0=Tc/C0 and C0=[ΔIload2/2m+mTc2/2]/ΔVout.
6. The method of claim 3, wherein said voltage regulator includes an impedance Z1 connected between said output node and a first node, an impedance Z2 connected between said first node and a reference voltage, a current sensor which has a transresistance Rs and produces an output voltage that varies with the output current delivered to said load, a summing circuit which produces an output voltage equal to the sum of the current sensor output voltage and the regulator's output voltage, and a controllable power stage which provides the regulator's output voltage in accordance with the voltage difference between the voltage at said first node and said summing circuit output voltage, further comprising the step of making the ratio of impedances Z1 and Z2 equal to the following:Z2/Z1=[Ro(1+sReCe)−Rs]/Rs in which Re is the equivalent series resistance of the output capacitor employed, and Ro is a quantity given by:Ro=Re, if Ce≧Ccrit, or Ro=(ΔIload/2mCe)+(mCeRe2/2Iload), if Ce<Ccrit, where Ccrit is determined in accordance with Ccrit=ΔIload/mRe0, where Re0=Tc/C0 and C0=[ΔIload2/2m+mTc2/2]/ΔVout.
7. A method of minimizing the size of a voltage regulator's output capacitor which enables the regulator's output voltage to be maintained within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, comprising the steps of:calculating a maximum equivalent series resistance Re(max) for an output capacitor to be employed by a voltage regulator which provides an output voltage to a load at an output node, said output capacitor to be connected in parallel across said load, said regulator required to maintain said output voltage within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, Re(max) calculated in accordance with the following: Re(max)=ΔVout/ΔIload, determining the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔIload and the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔIload, determining which of said absolute values is smaller, the smaller of said absolute values being a value m, determining a critical capacitance Ccrit in accordance with the following: Ccrit=ΔIload/mRe(max), selecting an output capacitor for connection across said load having an equivalent series resistance Re that is slightly less than or equal to Re(max) and a capacitance that is greater than or equal to Ccrit, and arranging the output impedance of said voltage regulator to be about equal to Re.
8. The method of claim 7, wherein said voltage regulator includes a controllable power stage which provides the regulator's output voltage in response to a signal received at a control input and a voltage error amplifier connected between said output node and said control input, said power stage characterized by a transconductance g, said step of arranging said output impedance to be about equal to Re accomplished by making the gain K(s) of said voltage error amplifier equal to the following:K(s)=(−1/gRe)(1/(1+sReCe)) in which Ce and Re are the capacitance and equivalent series resistance of the output capacitor employed.
9. A method of minimizing the size of a buck-type switching voltage regulator's output capacitor which enables the regulator's output voltage Vout to be maintained within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, comprising the steps of:calculating a maximum equivalent series resistance Re(max) for an output capacitor to be employed by a current-mode controlled switching voltage regulator which receives an input voltage Vin and provides an output voltage Vout to a load connected to an output node via an output inductor, said inductor alternately connected to Vin and ground via first and second switches, respectively, said output capacitor to be connected in parallel across said load, said regulator required to maintain Vout within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, Re(max) calculated in accordance with the following: Re(max)=ΔVout/ΔIload, determining a minimum inductance Lmin for said output inductor in accordance with the following: Lmin=VoutToffRe(max)/Vripple,p-p where Toff is the off time of said first switch and Vripple,p-p is the maximum allowed peak-to-peak output ripple voltage, selecting an output inductor for use in said regulator having an inductance L1 which is equal to or greater than Lmin, determining a minimum capacitance Cmin for said output capacitor in accordance with the following: Cmin=ΔIload/[Re(max)(Vout/L1)]if Vout<(Vin−Vout), and in accordance with the following: Cmin=ΔIload/[Re(max)((Vin−Vout)/L1)]if Vout>Vin−Vout, selecting an output capacitor for connection across said load having a capacitance Ce about equal to Cmin and an equivalent series resistance Re about equal to Re(max), and arranging the output impedance of said regulator to be about equal to Re.
10. The method of claim 9, wherein said voltage regulator includes a controllable power stage which provides the regulator's output voltage in response to a signal received at a control input and a voltage error amplifier connected between said output node and said control input, said power stage characterized by a transconductance g, said step of arranging said output impedance to be about equal to Re accomplished by making the gain K(s) of said amplifier equal to the following:K(s)=(−1/gRe)(1/(1+sReCe)) in which Ce and Re are the capacitance and equivalent series resistance of the output capacitor employed.
11. A voltage regulator which maintains its output voltage within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, comprising:a controllable power stage characterized by a transconductance g and connected to produce an output voltage Vout at an output node in accordance with a signal received at a control input, said output node connected to a load, an output capacitor connected to said output node and in parallel across said load, said output capacitor having an equivalent series resistance Re, and a voltage error amplifier connected between said output node and said control input, said controllable power stage, said output capacitor and said amplifier forming a voltage regulator required to maintain the voltage at said output node within a specified voltage deviation specification ΔVout for a step change in load current ΔIload, said output capacitor having a capacitance that is equal to or greater than a critical capacitance Ccrit, in which Ccrit is given by Ccrit=ΔIload/mRe, where m is equal to the smaller of 1)the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔIload, or 2)the absolute value of the minimum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔIload, said voltage regulator arranged to have an output impedance which is about equal to Re.
12. The voltage regulator of claim 11, wherein the gain K(s) of said voltage error amplifier is given by the following:K(s)=(−1/gRe)(1/(1+sReCe)) where g is equal to the transconductance of said controllable power stage, and Re and Ce are equal to the equivalent series resistance and capacitance, respectively, of said output capacitor.
13. The voltage regulator of claim 11, wherein said controllable power stage comprises a power circuit connected to produce said regulator's output voltage in accordance with a signal received at a control input, a current sensor connected in series between said power circuit and said output node which produces an output that varies with said power circuit's output current, and a current controller connected to receive the outputs of said voltage error amplifier and said current sensor as inputs and producing an output connected to said power circuit's control input for controlling said power circuit .
14. The voltage regulator of claim 13, wherein said current controller is an amplifier and said power circuit is a series pass transistor, said regulator being a linear voltage regulator.
15. The voltage regulator of claim 11, wherein said regulator is a switching voltage regulator.
16. The voltage regulator of claim 11, wherein said output capacitor has a capacitance about equal to Ccrit and an equivalent series resistance Re about equal to ΔVout/ΔIload, said capacitor being the smallest possible output capacitor which enables the regulator to maintain its output voltage within ΔVout for a step change in load current ΔIload.
17. A voltage regulator which maintains a regulated output voltage within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload, comprising:a controllable power stage characterized by a transconductance g and connected to produce an output voltage Vout at an output node in accordance with a signal received at a control input, said output node connected to an output load, an output capacitor connected to said output node and in parallel across said output load, and a voltage error amplifier connected between said output node and said control input, said power stage, said output capacitor and said amplifier forming a voltage regulator required to maintain a voltage at said output node within a specified voltage deviation specification ΔVout for a step change in load current ΔIload, said amplifier arranged to have a gain K(s) given by the following: K(s)=(−1/gRo)(1/(1+sReCe)) where g is equal to the transconductance of said controllable power stage, Re and Ce are equal to the equivalent series resistance and capacitance, respectively, of said output capacitor, and where Ro is equal to: Re, if Ce is greater than or equal to ΔIload/mRe, or to: Δload/2mCe+[mCe(Re)]/2ΔIload, if Ce is less than ΔIload/mRe, where m is equal to the smaller of 1)the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔIload, or 2)the absolute value of the minimum available slope of the current injected by the voltage regulator,toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔIload.
18. A voltage regulator which maintains a regulated output voltage within a specified voltage deviation specification ΔVout for a step change in load current ΔIload, said regulator comprising:a controllable power stage which provides an output voltage to a load at an output node in accordance with the voltage difference between a first control input and a second control input, an output capacitor connected to said output node and in parallel across said load, an impedance Z1 connected between said output node and a first node, an impedance Z2 connected between said first node and a reference voltage, a current sensor which has a transresistance Rs and produces an output voltage that varies with the output current delivered to said load, a summing circuit which produces an output voltage equal to the sum of the sensor output voltage and the voltage at said output node, said current sensor output voltage and said summing circuit output voltage connected to said first and second control inputs, respectively, said controllable power stage, said output capacitor, said impedances, said current sensor and said summing circuit forming a voltage regulator required to maintain the voltage at said output node within a specified voltage deviation specification ΔVout for a step change in load current ΔIload, said regulator arranged such that the ratio of impedances Z1 and Z2 is equal to the following: Z1/Z2=[Ro(1+sReCe)−Rs]/Rs where Re and Ce are equal to the equivalent series resistance and capacitance, respectively, of said output capacitor, and where Ro is equal to: Re, if Ce is equal to or greater than ΔIload/mRe, or to: ΔIload/2mCe+[mCe(Re)]/2ΔIload, if Ce is less than ΔIload/mRe, where m is equal to the smaller of 1)the absolute value of the maximum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔIload, or 2)the absolute value of the minimum available slope of the current injected by the voltage regulator toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔIload.
19. The voltage regulator of claim 18, wherein said controllable power stage comprises:a power circuit connected to produce said regulator's output voltage in response to a signal received at a control input, and a fast voltage controller producing an output signal to said control input of said power circuit in accordance with the voltage difference between the voltage at said first node and the output voltage of said summing circuit.
20. The voltage regulator of claim 19, wherein said power circuit comprises a pair of series-connected switches and an output inductor, said output inductor connected between the junction of said switches and said output node, and said fast voltage controller comprises a hysteretic comparator and a driving circuit, said driving circuit connected to control the states of said switches in accordance with a signal received at a control input, said comparator connected to receive the voltage at said first node and the output voltage of said summing circuit as inputs and producing an output connected to said driving circuit's control input.
21. The voltage regulator of claim 20, wherein said impedance Z1 is implemented with a resistor R1 and a capacitor C1 connected in parallel, and impedance Z2 is implemented with a resistor R2, said resistors R1 and R2 and capacitor C1 arranged such that the output impedance of said voltage regulator is equal to Re, whereby:R2/R1=(Ro−Rs)/Rs, and C1*R1=Ce[(RoRe)/Rs].
22. The voltage regulator of claim 18, wherein said current sensor and summing circuit comprise a resistor having a resistance Rs connected between said controllable output stage at a second node and said output node, the voltage at said second node being said summing circuit output voltage.
23. A method of enabling a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within specified boundaries for bidirectional step changes in load current of a specified maximum magnitude and to reduce the power consumption of the device being powered by the regulator when the regulator's output voltage transient V1 in response to a specified maximum step increase in load current is less than its voltage transient V2 in response to a specified maximum step decrease in load current, comprising the step of:compensating a voltage regulator which employs an output capacitor and is required to maintain a regulated output voltage within specified upper and lower boundaries for bidirectional step changes in load current of a specified maximum magnitude and which exhibits an output voltage transient V1 in response to a maximum step increase in load current that is less than the voltage transient V2 it exhibits in response to a maximum step decrease in load current such that the output voltage after a step decrease in load current peaks at said upper boundary and decreases to a value about equal to said lower boundary plus V1, said output capacitor being the smallest possible output capacitor that enables the regulator to provide said transient response.
24. A method of enabling a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload and to reduce the power consumption of the device being powered by the regulator when the regulator's output voltage transient V1 in response to a maximum step increase in load current is less than its voltage transient V2 in response to a maximum step decrease in load current, comprising the steps of:determining, for a voltage regulator connected to provide a regulated output voltage to an output load at an output node and having an output capacitor connected in parallel across said load and which is required to maintain said output voltage within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload and which exhibits an output voltage transient V1 in response to a maximum step increase in load current that is less than its voltage transient V2 in response to a maximum step decrease in load current, the absolute value of the maximum available slope of the current injected by said regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔIload and the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔIload, said regulator including a controllable power stage which provides the regulator's output voltage in response to a signal received at a control input and a voltage error amplifier connected between said output node and said control input, said power stage having a transconductance g and said voltage amplifier having a gain K(s), determining which of said absolute values is smaller, the smaller of said absolute values being a value m, determining a critical time constant Tcrit in accordance with the following: Tcrit=ΔIload/m, selecting a type of capacitor to be used as said output capacitor such that said capacitor's characteristic time constant Tc is less than Tcrit, determining a minimum capacitance Cmin in accordance with Cmin=[ΔIload2/m+m(Tc2)]/2ΔVout, selecting an output capacitor having a capacitance Ce for connection across said load in accordance with Ce ≧Cmin, and compensating said regulator such that the gain K(s) of said voltage error amplifier is made equal to the following: K(s)=(−1/gRo)(1/(1+sReCe)) in which Re is the equivalent series resistance of the output capacitor selected, s is the complex frequency, and Ro is a quantity given by: Ro=(ΔIload/2m1Ce)+(m1CeRe2/2ΔIload), where m1 is equal to the larger of said absolute values, and offsetting the output voltage such that, at maximum load, the output voltage settles at the minimum allowed output voltage.
25. A method of enabling a voltage regulator to employ the smallest possible output capacitor that allows the regulator's output voltage to be maintained within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload and to reduce the power consumption of the device being powered by the regulator when the regulator's output voltage transient V1 in response to a maximum step increase in load current is less than its voltage transient V2 in response to a maximum step decrease in load current, comprising the steps of:determining, for a voltage regulator connected to provide a regulated output voltage to an output load at an output node and having an output capacitor connected in parallel across said load and which is required to maintain said output voltage within a specified voltage deviation specification ΔVout for a bidirectional step change in load current ΔIload and which exhibits an output voltage transient V1 in response to a maximum step increase in load current that is less than its voltage transient V2 in response to a maximum step decrease in load current, the absolute value of the maximum available slope of the current injected by said regulator toward the parallel combination of the output load and output capacitor for a step increase in load current equal to ΔIload and the absolute value of the minimum available slope of the current injected toward the parallel combination of the output load and output capacitor for a step decrease in load current equal to ΔIload, said voltage regulator including an impedance Z1 connected between said output node and a first node, an impedance Z2 connected between said first node and a reference voltage, a current sensor which has a transresistance Rs and produces an output that varies with the output current delivered to said load, a summing circuit which produces an output voltage equal to the sum of the current sensor output voltage and the regulator's output voltage, and a controllable power stage which provides the regulator's output voltage in accordance with the voltage difference between the voltage at said first node and said summing circuit output voltage, determining which of said absolute values is smaller, the smaller of said absolute values being a value m, determining a critical time constant Tcrit in accordance with the following: Tcrit=ΔIload/m, selecting a type of capacitor to be used as said output capacitor such that said capacitor's characteristic time constant Tc is less than Tcrit, determining a minimum capacitance Cmin in accordance with Cmin=[ΔIload2/m+m (Tc2)]/2ΔVout, selecting an output capacitor having a capacitance Ce for connection across said load in accordance with Ce≧Cmin, compensating said regulator such that the ratio of impedances Z1 and Z2 made equal to the following: Z2/Z1=[Ro(1+sReCe)−Rs]/Rs in which Re is the equivalent series resistance of the output capacitor selected, s is the complex frequency, and Ro is a quantity given by: Ro=(ΔIload/2m1Ce)+(m1CeRe2/2ΔIload), where m1 is equal to the larger of said absolute values, andoffsetting the output voltage such that, at maximum load, the output voltage settles at the minimum allowed output voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of application Ser. No. 09/249,266, filed Feb. 12, 1999 now U.S. Pat No. 6,064,187.

US Referenced Citations (2)

Number	Name	Date	Kind
5774734	Kikinis et al.	Sep 1998
5912552	Takeishi	Jun 1999

Continuation in Parts (1)

	Number	Date	Country
Parent	09/249266	Feb 1999	US
Child	09/557785		US

Voltage regulator compensation circuit and method

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CROSS-REFERENCE TO RELATED APPLICATIONS

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