Patent Grant
11835979
This non-provisional application claims priority under 35 U.S.C. § 119(a) to Patent Application No. 110127784 filed in Taiwan, R.O.C. on Jul. 28, 2021, the entire contents of which are hereby incorporated by reference.
The present invention relates to a voltage generation technology, and in particular, to a voltage regulator device.
Generally, a voltage regulator that keeps an output voltage from being affected by a load includes an operational amplifier (OPA). The voltage regulator uses the OPA to lock a voltage, so that an output voltage does not change with a load. However, the OPA is a complex circuit including a plurality of sub-circuits with different functions. Therefore, the OPA may occupy a larger area of a voltage regulator or a chip. Secondly, the OPA is a complex circuit. Compared with a simple circuit, the OPA needs to perform more component variability compensation, which limits an operational bandwidth of the OPA during voltage regulation (for example, the OPA cannot operate in a higher-speed bandwidth).
In addition, a voltage follower is another circuit for generating a voltage, and has a simple structure. However, the voltage generated by the voltage follower changes under impact of a temperature. Secondly, because the voltage follower is an open loop, the voltage also varies with a load.
In summary, the present invention provides a voltage regulator device. According to some embodiments, the voltage regulator device can prevent an output voltage thereof from being affected by load and a temperature without performing redundant component variability compensation. According to some embodiments, the voltage regulator device can reduce an area occupied by itself on a device or a chip.
According to some embodiments, the voltage regulator device includes a first impedance, a reference current generation circuit, a current mirror circuit, a second impedance, and a negative feedback circuit. The first impedance has a first impedance value. The reference current generation circuit is coupled to the first impedance and a reference voltage. The reference current generation circuit has a first potential difference. The reference current generation circuit is configured to generate a reference current according to the reference voltage, the first potential difference, and the first impedance value. The current mirror circuit is coupled to the reference current generation circuit and a first node. The current mirror circuit is configured to output an output current to the first node according to the reference current. There is a first ratio between the output current and the reference current. The second impedance is coupled between the first node and a second node. The second impedance has a second impedance value. The second impedance is configured to generate an output voltage at the second node according to a voltage of the first node, the output current, and the second impedance value. There is a second ratio between the second impedance value and the first impedance value. The second ratio and the first ratio are inversely proportional to each other. The negative feedback circuit is coupled to the first node and the second node. The negative feedback circuit is configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. The voltage of the first node is substantially the same as the first potential difference, so that the output voltage conforms to the reference voltage.
In summary, according to some embodiments, the voltage regulator device has a simple structure, so that unnecessary component variability compensation is not required, and an operating bandwidth is not limited (for example, the voltage regulator device can operate in a high-speed bandwidth). According to some embodiments, the first ratio (the ratio between the output current and the reference current) and the second ratio (the ratio between the second impedance value and the first impedance value) are inversely proportional to each other, so that the output voltage is not affected by the temperature. According to some embodiments, the output voltage is adjusted by the negative feedback circuit, to prevent the output voltage from being affected by the load.
Terms, such as “first” and “second”, are used in this specification to distinguish referred components, not to order or limit differences of the referred components, and are not used to limit a scope of the present invention. In addition, terms, such as “couple”, are used mean that two or more components are directly in physical or electrical contact with each other, or are indirectly in physical or electrical contact with each other. For example, if the specification describes that a first device is coupled to a second device, it means that the first device may be directly and electrically connected to the second device, or indirectly and electrically connected to the second device through another device or connecting means.
The reference voltage Vref may be a temperature coefficient band gap reference voltage generated by a band gap reference voltage generation circuit (not shown). In other words, the reference voltage Vref may be a voltage that is irrelevant to a temperature coefficient or a voltage that does not vary with a temperature.
The first impedance R1 has a first impedance value. The first impedance R1 may be formed by passive components such as a resistor, a capacitor, and an inductor. The first impedance R1 is coupled between the ground terminal GND and the reference current generation circuit 11. In some embodiments, as shown in
The reference current generation circuit 11 has a first potential difference Vgs1. The reference current generation circuit 11 is configured to generate a reference current Im1 according to the reference voltage Vref, the first potential difference Vgs1, and the first impedance value. In some embodiments, as shown in Equation 1, the reference current Im2 is obtained by the reference current generation circuit 11 by dividing the reference voltage Vref minus the first potential difference Vgs1 by the first impedance value.
r1 is the first impedance value.
The current mirror circuit 13 is configured to output an output current Im2 to the first node N1 (described below) according to the reference current Im1, where there is a first ratio between the output current Im2 and the reference current Im1 (as shown in Equation 2).
Im2=Im1*k1 (Equation 2)
k1 is the first ratio.
The second impedance R2 has a second impedance value. The second impedance R2 may be formed by passive components such as a resistor, a capacitor, and an inductor. In some embodiments, as shown in
r1 is the first impedance value, r2 is the second impedance value, k1 is the first ratio, and k2 is the second ratio.
In some embodiments, the second ratio is determined according to a temperature coefficient of the first impedance R1 and a temperature coefficient of the second impedance R2. An example in which both the first impedance R1 and the second impedance R2 are resistances is used for description. Because the first impedance R1 and the second impedance R2 are made of different materials, the first impedance R1 and the second impedance R2 have different resistance temperature coefficients. Therefore, at the same temperature, the first impedance value is different from the second impedance value. The resistance temperature coefficient is a positive temperature coefficient or a negative temperature coefficient depending on a nature of the material (for example, if the material is a conductor, the temperature coefficient of the resistance is a positive temperature coefficient, and if the material is a semiconductor or an insulator, the temperature coefficient of the resistance is a negative temperature coefficient). Therefore, in a condition that the first impedance R1 and the second impedance R2 are made of the same material, the first impedance value is still different from the second impedance value when the first impedance R1 and the second impedance R2 are at different temperatures. In other words, because the first impedance R1 and the second impedance R2 vary with a temperature, the second ratio varies with the temperature. In some embodiments, the second ratio is directly proportional to the second impedance value, and the second ratio is inversely proportional to the first impedance value, but the present invention is not limited thereto. The second ratio may be directly proportional to the first impedance value, and the second ratio may be inversely proportional to the second impedance value.
In some embodiments, as shown in Equation 5, the output voltage Vout is obtained by the second impedance R2 by multiplying the output current Im2 by a second impedance value and then adding the voltage V1 of the first node N1.
Vout=V1+Im2*r2 (Equation 5)
Equation 6 may be obtained by integrating Equation 1 to Equation 5. It can be seen that the output voltage VOU, is irrelevant to the first impedance value and the second impedance value, that is, the output voltage Vout does not vary with a temperature.
Vout=Vref+V1−Vgs1 (Equation 6)
A negative feedback circuit 15 is configured to generate a feedback voltage Vth according to the voltage V1 of the first node N1, and adjust the output voltage Vout according to the feedback voltage Vfb. For example, when a load falls, the output voltage Vout rises. In this case, the negative feedback circuit 15 lowers the output voltage Vout according to the voltage V1 of the first node N1 and the feedback voltage Vout to stabilize the output voltage Vout at a voltage level. When the load rises, the output voltage Vout falls. In this case, the negative feedback circuit 15 raises the output voltage Vout according to the voltage V1 of the first node N1 and the feedback voltage Vfb to stabilize the output voltage Vout at the voltage level. In other words, the output voltage Vout is prevented by the negative feedback circuit 15 from varying with the load.
The voltage V1 of the first node N1 is substantially the same as the first potential difference Vgs1, so that the output voltage Vout conforms to the reference voltage Vout. Specifically, the output voltage Vout may vary with the temperature because the voltage V1 of the first node N1 may vary with the temperature. Thus, the output voltage Vout conforms to the reference voltage Vref and is irrelevant to the temperature when the voltage V1 of the first node N1 is substantially the same as the first potential difference Vgs1 For example, the voltage V1 of the first node N1 is a second potential difference Vgs2 of a sixth transistor M6 of the negative feedback circuit 15 (for example, the sixth transistor M6 is a metal oxide semiconductor (MOS) transistor, and the second potential difference Vgs2 is a potential difference between a gate and a source). Because the sixth transistor M6 has a negative temperature coefficient, the second potential difference Vgs2 changes under impact of a temperature (that is, when the temperature becomes higher, the second potential difference Vgs2 becomes smaller; and when the temperature becomes lower, the second potential difference Vgs2 becomes larger). Therefore, the output voltage Vout is irrelevant to the temperature when the voltage V1 (for example, the second potential difference Vgs2) of the first node N1 is substantially the same as the first potential difference Vgs1.
As shown in
As shown in
k3 is the third ratio, k4 is the fourth ratio, and k1 is the first ratio.
As shown in
The first transistor M1 is coupled between the working voltage terminal HV and the reference current generation circuit 11 (specifically, a source of the first transistor M1 is coupled to the working voltage terminal HV, and a drain of the first transistor M1 is coupled to the reference current generation circuit 11)., The reference current Im1 flows through the first transistor M1. The second transistor M2 is coupled between the working voltage terminal HV and the second current mirror circuit 131B (specifically, the source of the second transistor M2 is coupled to the working voltage terminal HV, and a drain of the second transistor M2 is coupled to the second current mirror circuit 131B). Gates of the first transistor M1 and the second transistor M2, and the drain of the first transistor M1 are coupled together. The first current mirror circuit 131A generates the mirror current Im3 at the drain of the second transistor M2 according to the reference current Im1 flowing through the first transistor M1, that is, the mirror current Im3 flows through the second transistor M2. In some embodiments, as shown in Equation 10, the third ratio is determined according to size ratios of the first transistor M1 and the second transistor M2 (for example, the potential difference from the drain to the gate of the first transistor M1 is equal to or close to the potential difference from the drain to the gate of the second transistor M2, so that a channel length modulation effect produced by the first transistor M1 and the second transistor M2 for the reference current Im1 and the mirror current Im3 can be ignored).
is the size ratio of the first transistor M1, where W is a width of the gate of the first transistor M1, and L is a length of the gate of the first transistor M1, and
is the size ratio of the second transistor M2, where W is the width of the gate of the second transistor M2, L is the length of the gate of the second transistor M2, and k3 is the third ratio.
In some embodiments, there are a plurality of first transistors M1 that are connected in parallel to each other and/or a plurality of second transistors M2 that are connected in parallel to each other. The third ratio is determined according to a quantity of the first transistors M1 and a quantity of the second transistors M2. For example, the quantity of the first transistors M1 that are connected in parallel to each other and the quantity of the second transistors M2 that are connected in parallel to each other affect a parameter of channel length modulation, and further affect the value of the mirror current Im3.
The third transistor M3 is coupled between a ground terminal GND and the first current mirror circuit 131A (specifically, the source of the third transistor M3 is coupled to the ground terminal GND, and a drain of the third transistor M3 is coupled to the first current mirror circuit 131A), The mirror current Im3 flows through the third transistor M3. The fourth transistor M4 is coupled between the ground terminal GND and the first node N1 (specifically, the source of the fourth transistor M4 is coupled to the ground terminal GND, and a drain of the fourth transistor M4 is coupled to the first node N1). The gates of the third transistor M3 and the fourth transistor M4, and the drain of the third transistor M3 are coupled together. The second current mirror circuit 131B generates the output current Im2 at the drain of the fourth transistor M4 according to the mirror current Im3 flowing through the third transistor M3, that is, the output current Im2 flows through the fourth transistor M4. In some embodiments, as shown in Equation 11, the fourth ratio is determined according to size ratios of the third transistor M3 and the fourth transistor M4 (for example, the potential difference from the drain to a gate of the third transistor M3 and the potential difference from the drain to the gate of the fourth transistor M4 are equal to or close to each other, so that the channel length modulation effects produced by the third transistor M3 and the fourth transistor M4 for the mirror current Im3 and the output current Im2 can be ignored).
is the size ratio of the third transistor M3, where W is the width of the gate of the third transistor M3, and L is the length of the gate of the third transistor M3, and
is the size ratio of the fourth transistor M4, where W is the width of the gate of the fourth transistor M4, L is the length of the gate of the fourth transistor M4, and k4 is the fourth ratio.
In some embodiments, there are a plurality of third transistors M3 that are connected in parallel to each other and/or a plurality of fourth transistors M4 that are connected in parallel to each other. The fourth ratio is determined according to a quantity of the third transistors M3 and a quantity of the fourth transistors M4. For example, the quantity of the third transistor M3 that are connected in parallel to each other and the quantity of the fourth transistors M4 that are connected in parallel to each other affect a parameter of channel length modulation, and further affect the value of the output current Im2.
It is worth noting that the first current mirror circuit 131A may also be implemented by an N-type MOS transistor or an N-type bipolar transistor, and the second current mirror circuit 131B may also be implemented by a P-type MOS transistor or a P-type bipolar transistor. In addition, in the foregoing case, how to appropriately adjust the structure of the current mirror circuit 13 (or the first current mirror circuit 131A and the second current mirror circuit 131B) can be derived from the disclosure of the present invention.
As shown in
Descriptions are made by using an example in which the fifth transistor M5 is an N-type MOS transistor. The first control terminal M5_g is a gate of the fifth transistor M5, the first terminal MS_s is a source of the fifth transistor M5, and a drain of the fifth transistor M5 is coupled to the current mirror circuit 13 (specifically, as shown in
In some embodiments, the fifth transistor M5 is an N-type MOS transistor or an N-type bipolar transistor, but the present invention is not limited thereto. The fifth transistor M5 may be a P-type MOS transistor or a P-type bipolar transistor. In addition, in the foregoing case, how to appropriately adjust the structure of the reference current generation circuit 11 can be derived from the disclosure of the present invention.
As shown in
In some embodiments, the feedback circuit 151 includes a sixth transistor M6. The sixth transistor M6 includes a second control terminal M6_g and a second terminal M6_s. The sixth transistor M6 is coupled among the ground terminal GND, the first node N1, and the voltage follower circuit 153. The second control terminal M6_g is coupled to the first node N1, and the second terminal M6_s is coupled to the ground terminal GND. There is the second potential difference Vgs2 forming the voltage V1 of the first node N1 between the second control terminal M6_g and the second terminal M6_s. In other words, the potential difference between the second control terminal M6_g and the second terminal M6_s (that is, the second potential difference Vgs2) is the voltage V1 of the first node N1. The sixth transistor M6 is configured to generate the feedback voltage Vfb according to the voltage V1 of the first node N1. In some embodiments, the sixth transistor M6 further includes a feedback terminal M6_d. The feedback terminal M6_d is coupled to a current source A1 and the voltage follower circuit 153. A terminal of the current source A1, other than terminals coupled to the feedback terminal M6_d and the voltage follower circuit 153, is coupled to the working voltage terminal HV. In other words, the current source A1 is coupled to the working voltage terminal HV, the voltage follower circuit 153, and the feedback terminal M6_d.
Descriptions are made by using an example in which the sixth transistor M6 is an N-type MOS transistor. The second control terminal M6_g is a gate of the sixth transistor M6, the second terminal M6_s is a source of the sixth transistor M6, and the feedback terminal M6_d is a drain of the sixth transistor M6. The sixth transistor M6 generates the feedback voltage VA at the feedback terminal M6_d according to the voltage V1 of the first node N1 and a current of the current source A1. Specifically, because the feedback terminal M6_d is coupled to the current source A1, the feedback terminal M6_d has a constant current. Therefore, when the load falls, the output voltage Vout rises, and the voltage V1 of the first node N1 rises (as shown in Equation 5). In this case, the sixth transistor M6 lowers the feedback voltage Vfb generated at the feedback terminal M6_d. When the load rises, the output voltage Vfb falls, and the voltage V1 of the first node N1 falls (as shown in Equation 5). In this case, the sixth transistor M6 raises the feedback voltage Vfb generated at the feedback terminal M6_d. The second potential difference Vgs2 is a gate-source voltage of the sixth transistor M6 (that is, the potential difference from the gate to the source). Because the second potential difference Vgs2 is affected by a temperature, the voltage V1 of the first node N1 and the output voltage Vout are further affected by the temperature. Therefore, to prevent the output voltage Vout from being affected by the temperature, the first potential difference Vgs1 between the first control terminal M5_g and the first terminal M5_s is made substantially the same as the second potential difference Vgs2. The fifth transistor M5 having the same specification as the sixth transistor M6, so that the output voltage Vout is irrelevant to the temperature. For example, referring to Equation 6, the voltage V1 of the first node N1 is the second potential difference Vgs2, and the second potential difference Vgs2 is substantially the same as the first potential difference Vgs1. Therefore, the output voltage Vout conforms to (for example, equals) the reference voltage Vref, and the output voltage Vout is irrelevant to the temperature.
In some embodiments, the sixth transistor M6 is an N-type MOS transistor or an N-type bipolar transistor, but the invention is not limited thereto. The sixth transistor M6 may be a P-type MOS transistor or a P-type bipolar transistor. In addition, in the foregoing case, how to appropriately adjust the structure of the feedback circuit 151 can be derived from the disclosure of the present invention.
In some embodiments, the voltage follower circuit 153 is the source follower circuit, including a seventh transistor M7. The seventh transistor M7 is an N-type MOS transistor. In some embodiments, the voltage follower circuit 153 is an emitter follower circuit. In this case, the seventh transistor M7 is an N-type bipolar transistor. Descriptions are made by using an example in which the voltage follower circuit 153 is a source follower circuit, and the seventh transistor M7 is an N-type MOS transistor. The seventh transistor M7 includes a third control terminal M7_g and a third terminal M7_s. The seventh transistor M7 is coupled between the working voltage terminal HV and the second node N2 (specifically, a drain of the seventh transistor M7 is coupled to the working voltage terminal HV, and the third terminal M7_s is coupled to the second node N2). The third control terminal M7_g is coupled to the feedback circuit 151 (specifically, the third control terminal M7_g is coupled to the current source A1 and the feedback terminal M6_d of the sixth transistor M6). The third control terminal M7_g is a gate of the seventh transistor M7, and the third terminal M7_s is a source of the seventh transistor M7. A ratio between an input voltage of a source follower circuit (a voltage from the third control terminal M7_g, that is, the feedback voltage Vfb) and an output voltage Vout, of the source follower circuit (a voltage from the third terminal M7_s, that is, the voltage of the second node N2) is approximately one (in other words, an amplification factor of the source follower circuit for amplifying the input voltage to the output voltage Vout is one or approximately one), and the input voltage and the output voltage are in phase with each other. Therefore, when the feedback voltage Vfb rises (that is, the load is rising at this time), the seventh transistor M7 raises the output voltage Vout through the third terminal M7_s according to the amplification factor (for example, raises the output voltage Vout to or close to the feedback voltage VA) to stabilize the output voltage Vout at a voltage level. When the feedback voltage Vfb falls (that is, the load is falling at this time), the seventh transistor M7 lowers the output voltage Vout through the third terminal M7_s according to the amplification factor (for example, lowers the output voltage Vout to or close to the feedback voltage Vfb) to stabilize the output voltage Vout at the voltage level. In this way, the output voltage Vout is not affected by the load.
In some embodiments, when the voltage follower circuit 153 is a source follower circuit, the seventh transistor M7 may be a P-type MOS transistor. In addition, in the foregoing case, how to appropriately adjust a structure of the voltage follower circuit 153 can be derived from the disclosure of the present invention. In some embodiments, when the voltage follower circuit 153 is an emitter follower circuit, the seventh transistor M7 may be a P-type bipolar transistor. In addition, in the foregoing case, how to appropriately adjust the structure of the voltage follower circuit 153 can be derived from the disclosure of the present invention.
It can be seen from the above that the voltage regulator device 10 can generate the output voltage Vout in an integrated circuit with a simple circuit structure, and the output voltage Vout is irrelevant to the temperature and the load. Operation of the voltage regulator device 10 does not require additional output pins and external components, and therefore, has an advantage of saving a circuit area. In addition, because no additional component variability compensation is required, an operating bandwidth is not limited.
In summary, according to some embodiments, the voltage regulator device has a simple structure, so that unnecessary component variability compensation is not required, and an operating bandwidth is not limited (for example, the voltage regulator device can operate in a high-speed bandwidth). According to some embodiments, the first ratio (the ratio between the output current and the reference current) and the second ratio (the ratio between the second impedance value and the first impedance value) are inversely proportional to each other, so that the output voltage is not affected by the temperature. According to some embodiments, the output voltage is adjusted by the negative feedback circuit, to prevent the output voltage from being affected by the load.
| Number | Date | Country | Kind |
|---|---|---|---|
| 110127784 | Jul 2021 | TW | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20070139030 | Lee | Jun 2007 | A1 |
| 20090302823 | Chao | Dec 2009 | A1 |
| 20130200872 | Friend | Aug 2013 | A1 |
| 20140055112 | Pigott | Feb 2014 | A1 |
| 20150177754 | Mengad | Jun 2015 | A1 |
| 20230163769 | Kumar | May 2023 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20230035977 A1 | Feb 2023 | US |
