Voltage regulator in semiconductor memory device

Abstract

Provided is a voltage regulator. The voltage regulator includes a level down shifter reducing an applied high voltage, a voltage divider dividing the reduced high voltage to generate a first division result, a comparator comparing a reference voltage to the first division result, and a driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider. The voltage divider divides the output voltage to generate a second division result serving as a voltage control signal fed back to the level down shifter.

Description

BRIEF DESCRIPTION OF THE FIGURE

FIG. 1 is a circuit diagram illustrating an exemplary voltage regulator according to an embodiment of the present invention.

Claims

1. A voltage regulator, comprising: a level down shifter reducing a high voltage;a voltage divider dividing the reduced high voltage to generate a first division result;a comparator comparing a reference voltage to the first division result to generate a comparison result; anda driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider,wherein the voltage divider divides the output voltage to generate a second division result, the second division result being fed back as a control voltage signal to the level down shifter.

2. The voltage regulator of claim 1, wherein the level down shifter comprises a high voltage, depletion type transistor.

3. The voltage regulator of claim 2, wherein the high voltage depletion type transistor reduces the high voltage using an internal channel formed during inactive periods of the voltage regulator.

4. The voltage regulator of claim 3, wherein the reduced high voltage generated during inactive periods of the voltage regulator corresponds to the high voltage minus a threshold voltage for the high voltage depletion type transistor.

5. The voltage regulator of claim 2, wherein the high voltage depletion type transistor reduces the high voltage in response to the control voltage signal during active periods of the voltage regulator.

6. The voltage regulator of claim 5, wherein the control voltage signal adjusts a width of a channel formed in the high voltage depletion type transistor during active periods of the voltage regulator.

7. The voltage regulator of claim 1, wherein the control voltage signal has a predetermined level lower than the level of the output voltage.

8. The voltage regulator of claim 7, wherein the output voltage and the control voltage signal respectively converge to a predetermined level during active periods of the voltage regulator.

9. The voltage regulator of claim 1, wherein the reduced high voltage is lower than a lowest breakdown voltage for transistors forming the voltage divider, comparator, and driver.

10. The voltage regulator of claim 2, wherein the reduced high voltage is a higher than or equal to a sum of a threshold voltage of the high voltage depletion type transistor and the control voltage signal.

11. A voltage regulator generating an output voltage at an output terminal, comprising: a level down shifter reducing a high voltage;a switch receiving the reduced high voltage and an enable signal;a first driver gated by an output of the switch to output the reduced high voltage;a second driver gated by the output of the first driver to output the reduced high voltage as the output voltage at the output terminal;a ripple eliminator connected between the output of the first driver and the output terminal;a voltage divider dividing the output voltage provided by the second driver to generate a first division result and a second division result; anda comparator comparing a reference voltage to the first division result to generate a comparison result, wherein the second driver generates the output voltage in relation to the comparison result voltage divider, andwherein the second division result is fed back as a control voltage signal to the level down shifter.

12. The voltage regulator of claim 11, wherein the level down shifter comprises a high voltage, depletion type transistor.

13. The voltage regulator of claim 12, wherein the high voltage depletion type transistor reduces the high voltage using an internal channel formed during inactive periods of the voltage regulator defined by the enable signal.

14. The voltage regulator of claim 13, wherein the reduced high voltage generated during inactive periods of the voltage regulator corresponds to the high voltage minus a threshold voltage for the high voltage depletion type transistor.

15. The voltage regulator of claim 12, wherein the high voltage depletion type transistor reduces the high voltage in response to the control voltage signal during active periods of the voltage regulator defined by the enable signal.

16. The voltage regulator of claim 15, wherein the control voltage signal adjusts a width of a channel formed in the high voltage depletion type transistor during active periods of the voltage regulator defined by the enable signal.

17. The voltage regulator of claim 11, wherein the control voltage signal has a predetermined level lower than the level of the output voltage.

18. The voltage regulator of claim 17, wherein the output voltage and the control voltage signal respectively converge to a predetermined level during active periods of the voltage regulator defined by the enable signal.

19. The voltage regulator of claim 11, wherein the reduced high voltage is lower than a lowest breakdown voltage for transistors forming the voltage divider, comparator, and driver.

20. The voltage regulator of claim 12, wherein the reduced high voltage is a higher than or equal to a sum of a threshold voltage of the high voltage depletion type transistor and the control voltage signal.