Claims
- 1. In a semiconductor circuit having a plurality of circuit elements, a voltage regulator comprising:
- a frequency compensated differential amplifier for generating a regulated voltage and having paired first and second self-biased input cascode transistors;
- a configurable resistive feedback network for setting the gain of said voltage regulator; and
- a plurality of source follower devices connected in parallel for buffering the output of said amplifier; a first of said source follower devices adapted for driving said feedback network and the remaining source follower devices adapted for providing a regulated supply voltage to said circuit elements.
- 2. The semiconductor circuit of claim 1 wherein said amplifier further comprises:
- a current source; and
- third, fourth, fifth and sixth transistors; said first and second transistors each having a threshold voltage that is less than the threshold voltage of said fifth and sixth transistors; the sources of said third and fourth transistors coupled to a power bus; the gate of said third transistor connected to the gate of said fourth transistor and to the drain of said third transistor; the drain of said third transistor further connected to the drain of said first transistor; the gate of said first transistor connected to the gate of said fifth transistor and to a bias voltage; the source of said first transistor connected to the drain of said fifth transistor; the sources of said fifth transistor and said sixth transistor connected at a common node and coupled to ground through said current source; the drain of said fourth transistor connected to the drain of said second transistor and to said first source follower device; the source of said second transistor connected to the drain of said sixth transistor; the gates of said second and sixth transistors connected at a common node and further connected to said feedback network.
- 3. In a semiconductor device having a plurality of core logic elements, a circuit for generating a regulated power supply voltage substantially independent of an external power supply comprising:
- a differential amplifier having self-biasing input pair cascode transistors, a feedback network for setting the gain of said amplifier coupled to one input of said amplifier, a plurality of source follower devices for buffering the output of said amplifier, one of said source follower devices adapted for driving said feedback network and the remaining source follower devices adapted for providing a regulated supply voltage to said semiconductor device, and a frequency compensation capacitor coupled between the output of said amplifier and the ground reference; and
- a bandgap generator for generating a reference bias voltage coupled to another input of said amplifier; said bandgap generator having a proportional- to-absolute temperature voltage source for generating a substantially temperature-independent reference bias voltage.
- 4. The semiconductor device of claim 3 wherein said proportional-to-absolute temperature voltage source further comprises circuit means for eliminating initial stable states where said reference bias voltage is held low after application of said external voltage.
- 5. The semiconductor device of claim 3 wherein said proportional-to-absolute temperature voltage source comprises a first and second pair of self-biased cascode MOS transistors each coupled to a first voltage supply by a current mirror and to the reference voltage source by transistors means adapted for providing a negative temperature coefficient.
- 6. The semiconductor device of claim 5 wherein said first and second pairs of self-biased cascode transistors comprise a first and second transistor, each having a first threshold voltage, and a third and fourth transistor having a second threshold voltage; the gates of said first and second transistors coupled to the drain of said fourth transistor; the gates of said third and fourth transistors resistively coupled to the drain of said fourth transistor by a bias resistor.
- 7. The semiconductor device of claim 3 wherein each of said self-biased input pair cascode transistors comprise a first and second transistor of the same conductivity type having different threshold voltages.
- 8. In a semiconductor device having a plurality of logic elements, a circuit for generating a regulated power supply voltage substantially independent of an external power supply comprising:
- a differential amplifier having self-biasing input pair cascode transistors, a configurable resistive feedback network for setting the gain of said amplifier coupled to one input of said amplifier, a plurality of source follower devices for buffering the output of said amplifier, one of said source follower devices adapted for driving said feedback network and the remaining source follower devices adapted for providing a regulated supply voltage to said logic elements, and a frequency compensation capacitor coupled between the output of said amplifier and the ground reference; and
- a bandgap generator for generating a reference bias voltage coupled to another input of said amplifier, said reference bias voltage having a positive temperature dependence;
- whereby said logic elements maintain a constant switching speed as temperature increases.
- 9. The semiconductor device of claim 8 wherein said bandgap generator has a first voltage source having a positive temperature dependence and a second voltage source having a negative temperature dependence, said first and second voltage sources summed together for generating reference bias voltage, said first voltage source larger than said second voltage source to dominate said second voltage source whereby said reference bias voltage has a positive temperature dependence.
- 10. The semiconductor device of claim 9 wherein said second voltage source comprises at least one bipolar transistor connected to supply a base-emitter voltage from ground.
Parent Case Info
This is a division of application Ser. No. 07/831,211 filed, Feb. 7, 1992, now U.S. Pat. No. 5,336,986.
US Referenced Citations (10)
Foreign Referenced Citations (1)
Number |
Date |
Country |
62-150935 |
Jul 1987 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
831211 |
Feb 1992 |
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