Patent Application
20150378379
The present document relates to multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. In particular, the present document relates to a method and a circuit for overvoltage compensation of such multi-stage amplifiers.
An example of multi-stage amplifiers are low-dropout (LDO) regulators which are linear voltage regulators which can operate with small input-output differential voltages. A typical LDO regulator 100 is illustrated in
The LDO regulator 100 of
In addition, the LDO regulator 100 may comprise an output capacitance Cout (also referred to as output capacitor or stabilization capacitor or bybass capacitor) 105 parallel to the load 106. The output capacitor 105 may be used to stabilize the output voltage Vout subject to a change of the load 106, in particular subject to a change of the load current Iload. It should be noted that typically the output current Iout at the output of the output amplification stage 103 corresponds to the load current Iload through the load 106 of the regulator 100 (apart from typically minor currents through the voltage divider 104 and the output capacitor 105). Consequently, the terms output current Iout and load current Iload are used synonymously, if not specified otherwise.
Typically, it is desirable to provide a stable output voltage Vout, even subject to transients of the load 106. By way of example, the regulator 100 may be used to provide a stable output voltage Vout to the processor of an electronic device (such as a smartphone). The load current Iload may vary significantly between a sleep state and an active state of the processor, thereby varying the load 106 of the regulator 100. In order to ensure a reliable operation of the processor, the output voltage Vout should remain stable, even in response to such load transients.
At the same time, the LDO regulator 100 should be able to react rapidly to load transients, i.e. the LDO regulator 100 should be able to rapidly provide the requested load current Iload, subject to a load transient. This means that the LDO regulator 100 should exhibit a high bandwidth.
The regulator 100 shown in
A possible approach to addressing the problem of overshoots of the output voltage of a multi-stage amplifier 100 is the use of an active pull down circuit which is configured to remove an extra charge from the output capacitor 105. The active pull down may be implemented as a comparator or as an amplifier.
When a comparator is used and the current which is sourced into the output node is lower than the sinking capability of the pull down circuit, a sawtooth oscillation is typically observed at the output node of multi-stage amplifier 100 (see
The present document is directed at providing circuitry which is configured to stabilize an active pull down circuit (also referred to as a current sinking circuit) of a multi-stage amplifier. In particular, the active pull down circuit is to be stabilized using an output capacitor 105 with a reduced capacitance, in order to reduce the cost and the size of the multi-stage amplifier. Furthermore, the consumed quiescent current of the multi-stage amplifier is to be reduced.
According to an aspect, a multi-stage amplifier, such as a linear regulator, is described. The multi-stage amplifier comprises a pass device (e.g. a power transistor) which is configured to source a load current at an output voltage to an output node of the multi-stage amplifier. The load current may be provided to a load of the multi-stage amplifier, if the load is coupled to the output node. The load current may be drawn from a high potential (e.g. from a supply voltage) of the multi-stage amplifier. For this purpose, a source of the pass device may be (directly) coupled to the high potential and a drain of the pass device may be (directly) coupled to the output node. The load current may correspond to the source-drain current through the pass device.
The multi-stage amplifier further comprises a first driver circuit which is configured to control the pass device based on a reference voltage and based on a first feedback voltage, wherein the first feedback voltage is derived from the output voltage (e.g. is proportional to the output voltage). The reference voltage may be used to set the desired level of the output voltage. The first driver circuit may be configured to generate a first gate voltage for a gate of the pass device, based on the reference voltage and based on the first feedback voltage. In particular, the first gate voltage may be derived based on a difference of the reference voltage and the first feedback voltage. The first gate voltage may be (directly) applied to the gate of the pass device.
The multi-stage amplifier typically comprises a plurality of amplification stages. The pass device may be part of an output stage of the multi-stage amplifier. Furthermore, the first driver circuit may comprise one or more amplification stages. In particular, the first driver circuit may comprise a differential amplification stage which is configured to derive an intermediate voltage based on a difference between the reference voltage and the first feedback voltage. The first gate voltage may be derived based on the intermediate voltage. Furthermore, the first driver circuit may comprise an intermediate amplification stage configured to derive the first gate voltage for controlling the pass device, based on the intermediate voltage. Hence, the first gate voltage may be proportional to the difference between the reference voltage and the first feedback voltage.
As such, the multi-stage amplifier comprises a first driver circuit and a pass device for providing the load current at the output node at a regulated output voltage. The first driver circuit and the pass device may be configured to provide a stable output voltage, even subject to load transients (notable subject to an increase of the load current, i.e. subject to a positive load transient, which typically leads to an undervoltage situation at the output node of the multi-stage amplifier).
Furthermore, the multi-stage amplifier comprises current sinking circuitry (also referred to as a pull down circuit) which may be used in case of an overvoltage situation at the output node of the multi-stage amplifier (when the output voltage exceeds a pre-determined desired level). The current sinking circuitry allows the multi-stage amplifier to react to a reduction of the load in a rapid and stable manner.
The multi-stage amplifier (notably the current sinking circuitry) comprises a sink transistor which is arranged in series with the pass device and which is configured to sink a first current from the output node to a low potential (e.g. to ground) of the multi-stage amplifier. The output node may correspond to a midpoint between the pass device and the sink transistor. For sinking the first current, a drain of the sink transistor may be (directly) coupled to the output node and a source of the sink transistor may be (directly) coupled to the low potential. As such, the first current may correspond to the drain-source current through the sink transistor.
In addition, the multi-stage amplifier (notably the current sinking circuitry) comprises a bypass transistor which is configured to couple a sense voltage which is derived from the output voltage to the low potential, in order to sink a second current from the output node to the low potential. For sinking the second current, a drain of the bypass transistor may be coupled to the output node via an intermediate resistor (e.g. via a so called ESR (Equivalent Serial Resistance) resistor, and a source of the bypass transistor may be (directly) coupled to the low potential. As such, the second current may correspond to the drain-source current through the bypass transistor. The sense voltage may be derived from the output voltage such that the sense voltage is proportional to the output voltage.
Furthermore, the multi-stage amplifier (notably the current sinking circuitry) comprises a second driver circuit which is configured to control the sink transistor and the bypass transistor, based on the reference voltage and based on a second feedback voltage, wherein the second feedback voltage is derived from the output voltage. In particular, the second driver circuit may be configured to generate a second gate voltage for a gate of the sink transistor and for a gate of the bypass transistor, based on the reference voltage and based on the second feedback voltage (notably based on a difference between the reference voltage and the second feedback voltage). For this purpose, the second driver circuit may comprise a differential amplifier which is configured to derive the second gate voltage for application to the gate of the bypass transistor and for application to the gate of the sink transistor based on the difference between the reference voltage and the second feedback voltage. The second gate voltage may be proportional to the difference between the reference voltage and the second feedback voltage.
In addition, the multi-stage amplifier comprises a voltage divider which is arranged between the output node and the low potential and which is configured to derive the first feedback voltage, the second feedback voltage and the sense voltage from the output voltage, such that the sense voltage is higher than the first feedback voltage and such that the first feedback voltage is higher than the second feedback voltage. Typically, the sense voltage, the first feedback voltage and the second feedback voltage are smaller than the output voltage. Furthermore, the sense voltage, the first feedback voltage and the second feedback voltage are usually proportional to the output voltage
By deriving the second feedback voltage such that it is lower than the first feedback voltage, it may be ensured that the sink transistor and the bypass transistor are only activated (in order to sink current from the output node), when the pass device is deactivated (i.e. when the pass device does not source any current). In particular, a dead band between the sourcing of current and the sinking of current at the output node may be provided. As a result of this, the operation of the multi-stage amplifier is stabilized.
Furthermore, by deriving the sense voltage such that it is greater than the first and second feedback voltage (and smaller than the output voltage), it is ensured that the drain-source voltage across the bypass transistor is smaller than the drain-source voltage across the sink transistor. As a result of this, the operating points of the bypass transistor and the sink transistor are (slightly) offset with respect to one another, thereby stabilizing the current sinking circuitry.
Overall, the above mentioned measures allow for the provision of a stable multi-stage amplifier which is configured to provide a stable output voltage, subject to positive load transients (for increasing load currents) and subject to negative load transients (for decreasing load current). Furthermore, the multi-stage amplifier exhibits a relatively low quiescent current, i.e. the multi-stage amplifier allows for a power efficient operation.
The voltage divider may comprise an internal ESR resistor which is configured to derive the sense voltage from the output voltage. By using an ESR resistor, it may be ensured that the sense voltage is (slightly) lower than the output voltage. Furthermore, the voltage divider may comprise a high resistor which is coupled to the output node via the ESR resistor and which is configured to derive the first feedback voltage from the output voltage. In addition, the voltage divider may comprise a dead band resistor which is coupled to the output node via the high resistor and which is configured to derive the second feedback voltage from the output voltage. In addition, the voltage divider may comprise a low resistor which, on a first side, is coupled to the output node via the dead band resistor, and which, on a second side, is (directly) coupled to the low potential. Hence, the voltage divider may comprise a serial arrangement comprising the ESR resistor which, on one side, is (directly) coupled to the output node and which, on the other side, is (directly) coupled to the high resistor, wherein the high resistor is (directly) coupled to the dead band resistor, wherein the dead band resistor is (directly) coupled to the low resistor, and wherein the low resistor is (directly) coupled to the low potential.
A resistance of the high resistor may be greater than a resistance of the internal ESR resistor by at least 1, 2, or 3 orders of magnitude. As such, the sense voltage may be only slightly lower than the output voltage, and the drain-source voltage across the bypass transistor may be only slightly lower than the drain-source voltage across the sink transistor, which may be beneficial regarding the stability of the output voltage during an overvoltage situation.
Furthermore, a size of the sink transistor may be greater than a size of the bypass transistor by at least 1, 2, or 3 orders of magnitude. As a result of this, the second current may be substantially smaller than the first current. This may be beneficial regarding the stability of the output voltage during an overvoltage situation.
The source of the bypass transistor may be coupled to the low potential via a first current limiting resistor and/or the drain of the bypass transistor may be coupled to the sense voltage via a second current limiting resistor. Such current limiting resistors may be used to set the operating point of the bypass transistor. In particular, the bypass transistor may be set within a linear region of the bypass transistor. By tuning the operating point of the bypass transistor relative to the operating point of the sink transistor, the stability of the current sinking circuit may be improved.
The multi-stage amplifier may further comprise a second bypass transistor which is arranged in parallel to the bypass transistor. The second driver circuit may be configured to also control the second bypass transistor. In particular, the second gate voltage may also be applied to a gate of the second bypass transistor. In a similar manner to the bypass transistor, a source of the second bypass transistor may be coupled to the low potential via a third current limiting resistor and/or a drain of the second bypass transistor may be coupled to the sense voltage via a fourth current limiting resistor. The third and/or forth current limiting resistor may be used to set the operating point of the second bypass transistor differently from the operating point of the bypass transistor. By using a plurality of bypass transistors and by tuning the resistor values in order to set different operating points for the plurality of bypass transistors, the stability of the current sinking circuit may be improved.
The multi-stage amplifier may further comprise an output capacitor which is arranged between the output node and the low potential. The output capacitor may create a zero within the transfer function of the multi-stage amplifier in conjunction with the bypass transistor (and the internal ESR resistor). This zero may be beneficial for the stability of the multi-stage amplifier.
The pass device may comprise or may be a P-type metaloxide semiconductor (MOS) transistor. The sink transistor may comprise or may be an N-type MOS transistor, and the bypass transistor may comprise or may be an N-type MOS transistor. Overall, the multi-stage amplifier may be implemented as an integrated circuit (IC), wherein typically only the output capacitor is implemented as an external component.
According to a further aspect, a method for reducing an overvoltage situation at an output node of a multi-stage amplifier is described. The method comprises sourcing a load current at an output voltage to the output node using a pass device. The load current may be drawn from a high potential of the multi-stage amplifier. The method further comprises controlling the pass device based on a reference voltage and based on a first feedback voltage derived from the output voltage. In addition, the method comprises sinking a first current from the output node to a low potential of the multi-stage amplifier using a sink transistor arranged in series with the pass device. The output node may correspond to a midpoint between the pass device and the sink transistor. Furthermore, the method comprises sinking a second current from the output node to the low potential using a bypass transistor which is configured to couple a sense voltage which is derived from the output voltage to the low potential. The method also comprises controlling the sink transistor and the bypass transistor, based on the reference voltage and based on a second feedback voltage derived from the output voltage. In addition, the method comprises deriving the first feedback voltage, the second feedback voltage and the sense voltage from the output voltage, such that the sense voltage is higher than the first feedback voltage and such that the first feedback voltage is higher than the second feedback voltage (and typically such that the sense voltage is lower than the output voltage).
It should be noted that the methods and systems including its preferred embodiments as outlined in the present document may be used stand-alone or in combination with the other methods and systems disclosed in this document. In addition, the features outlined in the context of a system are also applicable to a corresponding method. Furthermore, all aspects of the methods and systems outlined in the present document may be arbitrarily combined. In particular, the features of the claims may be combined with one another in an arbitrary manner.
In the present document, the term “couple” or “coupled” refers to elements being in electrical communication with each other, whether directly connected e.g., via wires, or in some other manner.
The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein
a illustrates an example block diagram of an LDO regulator;
b illustrates the example block diagram of an LDO regulator in more detail;
a shows a block diagram of an example multi-stage amplifier comprising an active pull down circuit;
b to 3e show example measurements;
a to 7c show example measurements; and
As already outlined above,
It is desirable to provide a multi-stage amplifier such as the regulator 100, 120, which is configured to generate a stable output voltage Vout subject to load transients. The output capacitor 105 may be used to stabilize the output voltage Vout, because in case of a load transient, an additional load current Iload may be provided by the output capacitor 105. Furthermore, schemes such as Miller compensation and/or load current dependent compensation may be used to stabilize the output voltage Vout.
At the same time, it is desirable to provide a multi-stage amplifier with a high bandwidth. The above stabilization schemes may lead to a reduction of the speed of the multi-stage amplifier. As such, it is desirable to provide a stabilization scheme which has reduced impact on the bandwidth of the multi-stage amplifier.
The circuit implementation of
The differential amplification stage 101 comprises the differential input pair of transistors P9251 and P8250, and the current mirror N9253 and N10252. The input of the differential pair is e.g. a 1.2V reference voltage 108 at P8 and the feedback 107 at P9 which is derived from the resistive divider 104 (with e.g. R0=0.8 MΩ and R1=1.2 MΩ).
The intermediate amplification stage 102 comprises a transistor N37260, wherein the gate of transistor N37260 is coupled to the stage output node 255 of the differential amplification stage 101. The transistor P158261 acts as a current source for the intermediate amplification stage 102, similar to transistor P29254 which acts as a current source for the differential amplification stage 101.
The output amplification stage 103 is coupled to the stage output node 262 of the intermediate amplification stage 102 and comprises a pass device or pass transistor 201 and a gate driver stage 110 for the pass device 201, wherein the gate driver stage comprises a transistor 270 and a transistor P11271 connected as a diode. This gate driver stage has essentially no gain since it is low-ohmic through the transistor diode P11271 which yields a resistance of 1/gm (output resistance of the driver stage 110 of the output amplification stage 103) to signal ground. The gate of the pass transistor 201 is identified in
In the present document, means for stabilizing the output voltage of a multi-stage amplifier such as the regulator 200 are described. These means may be used in conjunction with other stabilizing means, such as an output capacitor 105, Miller compensation 231 and/or load current dependent compensation 213, 214, 215. The described stabilizing means are configured to increase the stability of the multi-stage amplifier 200 subject to load transients, and at the same time to allow for a fast convergence of the multi-stage amplifier 200 subject to such load transients. In particular, the means which are described in the present document allow stabilizing the output voltage of the multi-stage amplifier 200 in case of an overvoltage situation.
a is an example schematic for an implementation of a current sink or over-voltage sink (also referred as current sinking circuitry or pull down circuit). In particular,
A second driver circuit 311 and a sink transistor 301 may be used to sink current from the output node 302 of the multi-stage amplifier 200, in case of an overvoltage situation. Under normal operation (i.e. if the feedback voltage 107 corresponds to or falls below the reference voltage Vref 108), the second feedback voltage 307 is lower than the reference voltage 108 (due to the dead band resistor 322). As a result of this, the gate of the sink transistor 301 is pulled to ground 332, thereby closing the sink transistor 301. Hence, under normal operation (i.e. within an undervoltage situation), no current is sunk from the output node 302 of the multi-stage amplifier 200.
In an overvoltage condition, if the second feedback voltage 307 is higher than or equal to the reference voltage Vref 108, the gate of the sink transistor 301 is pulled high, thereby opening the sink transistor 301 and thereby activating the current sink. The gate of the sink transistor 301 is driven by the second driver circuit 311 to sink the current from the output node 302 of the multi-stage amplifier 200. The dead band resistor 322 defines the level of the output voltage at which the current sink (i.e. the sink transistor 301) is activated. As such, the dead band resistor 322 defines a dead band between the deactivation of the sourcing of current (via the pass device 201) and the activation of the current sink (via the sink transistor 301).
If the second driver circuit 311 is configured as a comparator, the gate of the sink transistor 301 is driven either to the supply voltage 331 or to ground 332. If the second driver circuit 311 along with the sink transistor 301 and the output capacitor 105 is configured as an amplifier, the gate of the sink transistor 301 is regulated depending on the difference between the second feedback voltage 307 and the reference voltage Vref 108. This is illustrated in
c shows the case where the second driver circuit 311 of the sink transistor 301 is operated as an amplifier. Again the output voltage graph 351, the relative load current graph 352 and the gate voltage graph 353 at the gate of the sink transistor 301 are shown as a function of time. Again 1 mA of current is sourced into the output node 302 of the multi-stage amplifier 200, thereby creating an overvoltage situation. An oscillation with an amplitude of 70 mV is observed at the output node 302 of the multi-stage amplifier 200.
The oscillations of the output voltage graph of
d shows the phase margin graph 361 for the current sinking circuitry 311, 301 as a function of the load current which has to be sunk by the sink transistor 301. The graph has been prepared for an output capacitor 105 (
The current sinking circuitry 311, 301 has two dominant poles one at the gate of the sink transistor 301 and another one at the drain of the sink transistor 301 (i.e. at the output node 302 of the multi-stage amplifier 200). The provision of a Miller compensation is typically difficult to achieve, as the output capacitor 105 may vary from 0.47 μF to higher values. As the output capacitor 105 it typically implemented off-chip, i.e. not as an integrated component of an IC forming the multi-stage amplifier 200, the capacitance of the output capacitor 105 may suffer from variation due to temperature, DC bias, tolerances etc. This renders the provision of a reliable Miller compensation difficult. Furthermore, it is typically not possible to implement a substantial current within the current sinking circuitry 311, 301 as this would add to quiescent current consumption of the multi-stage amplifier 200. Hence, other means for stabilizing the operation of the current sinking circuitry 311, 301 are desirable.
A possible approach to stabilizing the current sinking circuitry 311, 301 is to provide an ESR (Equivalent Series Resistance) resistor 402 in series with the output capacitor 105, as shown in
e shows the phase margin graph 371 (as a function of the load current) of the current sinking circuitry 311, 301 of
The use of an additional ESR resistor 402 typically has a detrimental effect on the DC and transient load regulation of multi-stage amplifier 200. Therefore it is desirable to provide circuitry which has similar effects as an additional external ESR resistor 402, but which does not exhibit the detrimental effects of an additional external ESR resistor 402.
Typically, the size of the bypass transistor 501 is substantially smaller than the size of the sink transistor 301. As a result of this, the second current which may be sunk via the bypass transistor 501 is typically substantially (e.g. by one or more orders of magnitude) smaller than a first current which is sunk via the sink transistor 301.
As can be seen in
As can be seen in
b shows the open loop gain 721 and the phase 722 of the circuit shown in
As indicated above, the current flowing through the bypass transistor 501 is typically relatively small. A relatively high current through the bypass transistor 501 would change the regulating voltage within an overvoltage situation. The stabilizing circuitry may be modified to take on a substantially higher current at relatively low loads and smaller currents at relatively high loads. If more current is sunk via the bypass transistor 501 at lower loads, the effective value of the internal ESR resistor 521 increased, thereby increasing the stability of the current sinking circuitry 311, 301. Such a non-linear behavior regarding the amount of current which may be sunk via the bypass transistor 501 may be implemented using the circuitry shown in
c shows the transient response of the current sinking circuitry comprising internal ESR compensation. In particular, the output voltage graph 741, the load current graph 742 and the gate voltage graph 743 at the gate of the sink transistor are illustrated as a function of time. The graphs of
The method 800 also comprises sinking 804 a second current from the output node 302 to the low potential 332 using a bypass transistor 501 which is configured to couple a sense voltage 507 which is derived from the output voltage to the low potential 332. In addition, the method 800 comprises controlling 805 the sink transistor 301 and the bypass transistor 501, based on the reference voltage 108 and based on a second feedback voltage 107 derived from the output voltage. Furthermore, the method 800 comprises deriving 806 the first feedback voltage 107, the second feedback voltage 307 and the sense voltage 507 from the output voltage, such that the sense voltage 507 is higher than the first feedback voltage 107 and such that the first feedback voltage 107 is higher than the second feedback voltage 307.
In the present document, current sinking circuitry has been described which may be used within a multi-stage amplifier, in order to reduce the output voltage of the multi-stage amplifier in case of an overvoltage situation. The reduction of the output voltage may be achieved in a rapid and stable and power efficient manner.
It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102014212502.2 | Jun 2014 | DE | national |
