Patent Application
20130002213
The present invention relates broadly to a voltage regulator structure, to devices comprising the voltage regulator structure, and to a method of providing a regulated output voltage.
Voltage regulators find use in many applications, such as in the integrated circuits used in the automotive industry. For example, with reference to
In a back-up mode, again the first regulator 102 is switched off while the second regulator 104 remains on, but the switch 110 is in an off position. In this mode, the second regulator 104 no longer sees the external capacitance 112, and, with the first regulator 102 being switched off, the external load 112 will discharge. As a result, moving from the back-up mode to the run mode will have a charge-up delay.
In many applications, of which the system in
A need therefore exists to provide a regulator structure that seeks to address one or more of the abovementioned problems.
Embodiments of the present invention provide a regulator architecture providing a low drop out solution, stability over a large range of capacitive loads, and good current load regulation.
According to a first embodiment of the present invention, there is provided a regulator structure comprising a first differential amplifier configured to provide an output as one of the inputs into each of a second and third differential amplifiers; the second differential amplifier configured to provide an output to the gate of a first pmos transistor and to receive a drain voltage of the first pmos transistor as the other input; the first pmos transistor configured to have an external load applied at a drain at a regulated voltage; the third differential amplifier configured to provide an output to the gate of a second pmos transistor and to receive a drain voltage of the second pmos transistor as the other input; wherein the first differential amplifier is further configured to receive the drain voltage of the second pmos transistor and a reference voltage as inputs; and wherein the drain of the second pmos transistor is coupled to the gate of the first pmos transistor to replicate the regulated voltage at the drain of the second pmos transistor.
The first differential amplifier may have a higher gain than the second and third differential amplifiers.
The second and third differential amplifiers may have substantially the same specifications.
The drain of the second pmos transistor may be coupled to the gate of the first pmos transistor via a third pmos transistor.
The third pmos transistor may have a gate coupled to the gate of the first pmos transistor.
The drain of the third pmos transistor may be coupled to the drain of the second transistor.
The drain of the second pmos transistor may be coupled to the gate of the first pmos transistor via the third pmos transistor and a current mirror circuit.
The second and third pmos transistors may have substantially the same specifications.
A same supply voltage may be applied to the first, second, and third differential amplifiers.
The same supply voltage may be applied to the sources of the first and the second pmos transistors.
According to a second embodiment of the present invention, there is provided a device comprising a regulator structure as defined in the first aspect.
The device may comprise an automotive integrated circuit, a GPS transceiver, or a set-top box.
According to a third embodiment of the present invention, there is provided a method of providing a regulated voltage output, the method comprising the steps of providing a first differential amplifier configured to provide an output as one of the inputs into each of a second and third differential amplifiers, the second differential amplifier configured to provide an output to the gate of a first pmos transistor and to receive a drain voltage of the first pmos transistor as the other input; the first pmos transistor configured to have an external load applied at a drain at the regulated voltage, and the third differential amplifier configured to provide an output to the gate of a second pmos transistor and to receive a drain voltage of the second pmos transistor as the other input; providing the drain voltage of the second pmos transistor and a reference voltage as inputs to the first differential amplifier; and coupling the drain of the second pmos transistor to the gate of the first pmos transistor to replicate the regulated voltage at the drain of the second pmos transistor.
Embodiments of the invention will be better understood and readily apparent to one of ordinary skill in the art from the following written description, by way of example only, and in conjunction with the drawings, in which:
The low gain regulator 252 is essential to ensure stability across different capacitive loads 254. However, a low gain regulator 252 is not able to provide good load regulation (load regulation is change in output voltage with change in load current 256, wherein ideally the output voltage Vout should not change with changing load current). With increasing load as Vout falls, the regulator structure 250 functions to increase the second reference voltage VB that is applied as a reference voltage to each of the replica regulator circuit 260 and the low gain regulator 252. The benefit of this is that the change in VB produces a reduction in the fall of the regulated output Vout. This serves to improve load regulation.
Thus, the variable voltage reference generator 262 must be operable to generate a variable reference VB. To accomplish this, the load current sensing circuit 258 senses the load current of the low gain regulator 252. This sensed load current is converted to signal applied at the regulated output VZ as a feed back to the replica regulator circuit 260. The replica regulator circuit 260 is essentially a copy or replica of the low gain regulator 252 except that it has a ratioed current capability (in order to keep current consumption under check). The application of the sensed load current output signal to the replica regulator circuit 260 causes the regulated output VZ to fall.
The voltage VZ is sensed by the variable voltage reference generator 262 which functions to differentially compare the voltage VZ to the reference voltage Vref. The variable voltage reference generator 262 then responds to the detected difference between the voltage VZ to the reference voltage Vref by adjusting the second reference voltage VB that is applied as a reference voltage to each of the replica regulator circuit 260 and the low gain regulator 252.
A third differential amplifier 306 (D3) also has VB as an input and drives the gate of a driver pmos 308. The drain of the driver pmos 308 is the output Vout of the regulator structure 300, and is fed back to the input of differential amplifier 306.
In one example implementation, the high gain amplifier 302 has a gain of about 45-50 dB, whereas the differential gain amplifiers 304 and 306 have a relatively lower gain of about 20-30 dB, such that the differential amplifiers 304, 306 can be readily stabilized, as will be appreciated by a person skilled in the art. The amplifiers 304 and 306 preferably have the same or similar specifications.
A sense pmos transistor 310 senses the load current through the driver pmos transistor 308 and feeds back a scaled current to the pmos transistor 312. Because of this feedback current, VB rises with rising load current improving the load regulation, as will be described in more detail below.
The driver pmos transistor 308 in an example implementation is a large pmos device to provide the output current, whereas the pmos transistor 312 is a small pmos device. The pmos transistor 310 is a scaled version of pmos transistor 308. The scale range can for example be around 1000 or less and pmos transistors 312 and 310 may, but are not limited to, having the same size used to sense the current flowing through pmos transistor 308. The sizes of the transistors in various embodiments depend on the value of load current to be supplied, input supply, etc., as will be appreciated by a person skilled in the art.
In the example embodiment, the current through the driver pmos transistor 308 is thus sensed through the sense pmos transistor 310, which is of scaled-down dimension from pmos transistor 308 as mentioned above. The sensed current is then fed as a load current to pmos transistor 312, through a current mirror circuit 319, formed by two nmos transistors 320, 322 in this example embodiment.
As differential amplifier 306 is a low gain amplifier in the example embodiment, and Vout is fed back to the differential amplifier 306 to drive the gate of the driver pmos 308, Vout is well regulated. However, for a fixed level of VB, only a limited load current regulation would be achieved by way of the differential amplifier 306 and the driver pmos 308. Therefore, in the example embodiment, a replica of Vout is produced at the drain of the pmos 312 via the sensing pmos 310. The scaling is chosen such that Vz is equal to Vout. Thus, the replica of Vout is fed back to both, high gain differential amplifier 302 and low gain amplifier 304.
In the regulator structure 300, VB therefore changes when Vout changes. In particular, if Vout decreases, as a result of an increased load current drawn, VB will rise at the output of the high gain differential amplifier 302. In turn, the increased VB at the input of low gain differential amplifiers 306 and 304 achieves that, despite being a low gain differential amplifier, the current load regulation range is increased accordingly.
Regulator structure 300 may be viewed as consisting of a main loop 314 including the high gain differential amplifier 302, a secondary loop 316 including the low gain differential amplifier 306, and a replica loop 318 including the low gain differential amplifier 304, for “replicating” the secondary loop 316 and providing a replica of Vout as feed back to the high gain differential amplifier 302.
Furthermore, the regulator structure 300 does not require a large dropout. Instead, assuming for example Vout at 1.2 volt, Vin needs only to be equal to or marginally larger than the sum of Vout and Vds of the pmos, i.e. Vin may be about 1.5 volt.
The example embodiment described can provide a regulator architecture being a low drop out solution but providing stable operation over a large range of capacitive loads, and good current load regulation. The example embodiment can find application in numerous devices in which low power consumption regulator circuits exhibiting stability over a large range of capacitive loads and with good current load regulation, such as, but not limited to, automotive integrated circuits, GPS transceivers, set-top box, etc.
The described embodiments of the present invention can provide a regulator architecture providing a low drop out solution, stability over a large range of capacitive loads, and good current load regulation.
While this detailed description has set forth some embodiments of the present invention, the appended claims cover other embodiments of the present invention which differ from the described embodiments according to various modifications and improvements. For example, while single transistor elements have been described with reference to the example implementation shown in
Within the appended claims, unless the specific term “means for” or “step for” is used within a given claim, it is not intended that the claim be interpreted under 35 U.S.C. 112, paragraph 6.
