BACKGROUND
Many electronic systems include a voltage regulator. For example, battery powered devices often include a DC-DC voltage regulator to provide power at a different voltage than provided by the battery. In general, voltage regulators may be switching or linear. Advantages of linear regulators include low noise (no switching noise) and small size (no large inductors or transformers). One particular linear voltage regulator design is the Low-Drop-Out (LDO) regulator. One advantage of LDO regulators is that the minimum input/output differential voltage at which the regulator can no longer regulate (drop out voltage) is low, hence the name Low-Drop-Out. Another advantage of LDO regulators is a rapid response to a load change.
Many systems, particularly battery powered systems, are switched to a very-low-power sleep mode during periods of inactivity. When the system “wakes up” (comes out of sleep mode), the power supply sees an instantaneous change in load current from essentially zero load current to a large load current. Even though LDO regulators have a relatively fast response to a load change compared to other regulator designs, there is still a finite response time (called wake-up time) during which the output voltage and current may ring around their steady-state values over a finite settling time. In some LDO regulators, additional current (boost current) is supplied by a separate parallel path during wake-up time to reduce the response time. Switching in the boost current can cause voltage glitches and can increase the peak magnitude of output voltage ringing.
Some systems monitor power supply voltages and reset the system when a power supply voltage exceeds a certain range. Voltage ringing during wake-up and voltage glitches from boost current can cause a spurious system reset. A system reset can be catastrophic, for example, in a mission-critical computer system. Accordingly, to avoid spurious system resets, in some systems the voltage reset range is permanently fixed at a wide range such that expected worst case transients do not cause a reset. Alternatively, in some systems voltage monitoring is completely suspended during the entire wake-up period.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram schematic of an example embodiment of a system.
FIG. 2 is a timing diagram illustrating voltage output from a voltage regulator in the system of FIG. 1.
FIG. 3 is a flow chart for a method of managing power to a system.
DETAILED DESCRIPTION
In the following discussion, a system is described having continuous monitoring of voltage regulator output but with variable power management thresholds for system reset. Relaxed thresholds are used during low power and wake-up when there may be glitches and ringing, and more stringent thresholds are used during normal operation.
FIG. 1 shows part of a system 100 including an example voltage regulator 102. The example is simplified to facilitate discussion and illustration. In the example of FIG. 1, the voltage regulator 102 is a linear LDO regulator. The voltage regulator 102 includes a series transistor 104 (a power FET in the example of FIG. 1) driven by a feedback amplifier 106. The feedback amplifier 106 regulates the output voltage VOUT to equal a reference voltage VREF. In addition (optionally), a transistor 108 is enabled by a BOOST signal to provide additional current (boost current) at the output of the voltage regulator 102 when there is a need to rapidly transition from a low load current to a high load current during wake-up.
The system 100 also shows a power management system 110. The power management system 110 generates a RESET signal to reset the system 100 when the output voltage VOUT is outside a specified range (above a high threshold or below a low threshold). The power management system 110 may also generate the BOOST signal.
FIG. 2 is an example timing diagram for the system 100. At time t0, the system 100 and the voltage regulator 102 are in a low-power sleep mode, the boost current transistor 108 is off, and the range between the LOW THRESHOLD and the HIGH THRESHOLD is set by the power management system 110 to set to be relatively high. At time t1, the system 100 wakes up, and the voltage regulator 102 switches to a high power mode. If there is a boost current transistor 108, then at time t1 the boost current transistor 108 is turned ON. During low power mode (before t0), and during wake-up, the range between LOW THRESHOLD and HIGH THRESHOLD is set to be sufficiently high so that worst case ringing of VOUT will not trigger a system reset. At time t2, the transient ringing of the output voltage VOUT has settled substantially and the range between the LOW THRESHOLD and HIGH THRESHOLD is set by the power management system 110 to be relatively low. If there is a boost current transistor 108 then the boost current transistor 108 is turned OFF at time t2. The time period between t1 and t2 may be a predetermined fixed time based on expected worst case settling times.
In some prior art systems, the LOW THRESHOLD and HIGH THRESHOLD are fixed at levels to accommodate worst case VOUT transients and ringing, such as the levels shown between t1 and t2 in FIG. 2. Fixed thresholds reduce protection during normal operation after wake-up. In some prior art systems, power management is turned off during wake-up, which results in no protection during wake-up against harmful VOUT transients. In addition, if there is a period of no protection, there is an opportunity for possible system tampering or attack. The system illustrated in FIGS. 1 and 2 is more robust, providing continuous power management (to protect against harmful transients during wake-up and to protect against tampering or attack), with relaxed thresholds during low power and wake-up (to avoid spurious resets), and more stringent thresholds during normal operation (to provide improved protection during normal operation).
FIG. 3 is a flow chart for a method 300 of managing power to a system. At step 302, a power management system continuously monitors an output voltage of a voltage regulator. At step 304, the power management system determines whether the output voltage is outside a range. At step 306, the power management system generates a reset signal when the output voltage is outside the range. At step 308, the power management system sets the range to a relatively low range during normal operation of the system. At step 310, the power management system sets the range to a relatively high range during a low power mode and during a wake-up from a low power mode,
Patent Application
20170068263
