Patent Application
20230266783
Most integrated circuit devices have become so complex that it is impractical for electronic device designers to design them from scratch. Instead, electronic device designers rely on predefined modular units of integrated circuit layout designs, arranging and joining them as needed to implement the various functions of the desired device. Each modular unit has a defined interface and behavior that has been verified by its creator. Though each modular unit may take a lot of time and investment to create, its availability for re-use and further development cuts product cycle times dramatically and enables better products. The predefined units can be organized hierarchically, with a given unit incorporating one or more lower-level units and in turn being incorporated within higher-level units. Many organizations have libraries of such predefined modular units for sale or license, including, e.g., embedded processors, memory, interfaces for different bus standards, power converters, frequency multipliers, sensor transducer interfaces, to name just a few. The predefined modular units are also known as cells, blocks, cores, and macros, terms which have different connotations and variations (“IP core”, “soft macro”) but are frequently employed interchangeably.
The modular units can be expressed in different ways, e.g., in the form of a hardware description language (HDL) file, or as a fully-routed design that could be printed directly to a series of manufacturing process masks. Fully-routed design files are typically process-specific, meaning that additional design effort would usually be needed to migrate the modular unit to a different process or manufacturer. Conversely, modular units in HDL form require subsequent synthesis, placement, and routing steps for implementation, but are process-independent, meaning that different manufacturers can apply their preferred automated synthesis, placement, and routing processes to implement the units using a wide range of manufacturing processes. By virtue of their higher-level representation, HDL units may be more amenable to modification and the use of variable design parameters, whereas fully-routed units may offer better predictability in terms of areal requirements, reliability, and performance. While there is no fixed rule, digital module designs are more commonly specified in HDL form, while analog and mixed-signal units are more commonly specified as a lower-level, physical description.
Many modular units, such as high bandwidth serializer/deserializer (SerDes) modules, are sensitive to power supply noise. Such noise, which often results from signal transitions in high bandwidth circuitry, increases jitter in transmitted signals and receiver clocks and influences the operation of amplifiers used for equalization and symbol decisions. Though there exist various techniques for limiting power supply noise to acceptable levels, they are overly complex, power hungry, or simply infeasible for use as part of a predefined modular unit.
Accordingly, there are disclosed herein power supply noise reduction methods and low drop out (LDO) voltage regulators with capacitively coupled supply noise-reducing components. One illustrative voltage regulator includes: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.
An illustrative voltage regulation method includes: coupling a supply voltage to an output node using a pass transistor having an n-type conduction channel; using an operational amplifier to derive a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node; deriving a ripple cancellation signal from the supply voltage with a buffer; supplying the control signal to a gate or base of the pass transistor; and imposing the ripple cancellation signal on the control signal via a coupling capacitor that couples the buffer to the base or gate of the pass transistor.
An illustrative computer-readable information storage medium stores a hardware description language (HDL) design of a low drop out (LDO) voltage regulation circuit, the design specifying: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.
Each of the foregoing regulator, method, and design, may be implemented individually or conjointly, together with any one or more of the following features in any suitable combination: 1. a feedforward capacitor coupling the supply voltage to an input of the buffer. 2. a bias voltage is supplied to the input of the buffer via a feedforward resistor. 3. the feedforward resistor and feedforward capacitor jointly act as a high pass filter. 4. the pass transistor is an n-type metal oxide semiconductor (NMOS) transistor. 5. the buffer is an inverting buffer comprising a first NMOS transistor in series with a second NMOS transistor, the first NMOS transistor having a fixed bias and the second NMOS transistor having a gate capacitively coupled to the supply voltage to generate the ripple cancellation signal on an intermediate node between the first and second NMOS transistors. 6. the buffer has a gain of about minus one. 7. the pass transistor has a gate capacitance and a ratio of the gate capacitance to the coupling capacitance determines a scaling factor for the ripple cancellation signal. 8. a resistive voltage divider that provides the scaled voltage of the output node to an inverting node of the operational amplifier.
Note that the specific embodiments given in the drawings and following description do not limit the disclosure. On the contrary, they provide the foundation for one of ordinary skill to discern the alternative forms, equivalents, and modifications that are encompassed in the claim scope.
Pass transistor M0 is an n-channel metal oxide semiconductor (NMOS) transistor, having a gate that receives a control signal VC from operational amplifier 104. The operational amplifier 104 receives a reference voltage VREF at its non-inverting input V+ and an unscaled or scaled version of the regulated voltage VOUT at its inverting input V−, amplifying the difference between the two to drive the gate of the pass transistor M0. There are many suitable ways to generate the reference voltage VREF available in the academic literature, though a bandgap voltage reference may be preferred due to stability and ease of implementation.
As such reference voltages are typically a fraction of the desired regulated voltage VOUT, a resistive voltage divider 106 may be used for scaling. Voltage divider 106 supplies a scaled voltage VOUT*R2/(R1+R2) to the inverting input V− of operational amplifier 104. So long as the supply voltage VIN sufficiently exceeds the desired voltage VOUT, amplifier 104 provides negative feedback, raising the control signal voltage VC (and regulated voltage VOUT) when the inverting input voltage V− is less than noninverting input voltage V+ and lowering the control signal voltage (and VOUT) when the inverting input voltage V− is greater than noninverting input voltage V+. In this fashion, amplifier 104 forces the difference between its input terminals to zero, thereby setting VOUT=VREF*(R1+R2)/R2.
Ideally, the regulated voltage VOUT is independent of the supply voltage VIN, and so long as the supply voltage's rate of variation does not exceed the amplifier's ability to adjust the control voltage, the performance is close to ideal. However, the pass transistor's inherent gate capacitance CG combines with the amplifier's output conductance to impose an upper limit on the rate of variation that can be corrected and thus an upper limit on the noise frequencies that can be suppressed.
It should be noted, however, that an intrinsic input capacitance (possibly augmented with a discrete or integrated input capacitor) CIN cooperates with the power supply impedance to act as a low pass filter that suppresses power supply noise above a certain cutoff frequency. For feasible combinations of input capacitance and supply impedance, this cutoff frequency is well above the upper limit that amplifier 104 can cope with. These two frequencies define an intermediate of noise frequencies that can leak through the illustrative voltage regulator to cause undesired variation in the regulated voltage VOUT. As one example, the range of intermediate frequencies is 2 megahertz to 10 megahertz for certain contemplated voltage regulator embodiments.
A summing amplifier 208 combines the feedback signal VFB with a feed forward signal VFF to produce supply a control signal Vs to the gate of pass transistor MP. The control signal Vs is expressible as
A feed forward amplifier 210 produces the feed forward signal VFF, which is expressible as
The feed forward amplifier acts as a high pass filter for frequencies in excess of approximately 1/2πRFF1CFF, which can be chosen so that the feed forward signal VFF represents the middle-frequency noise components of the supply voltage. The resistances of the summing amplifier 208 enable the control voltage to suppress these noise components from the regulated voltage VOUT.
The use of two additional operational amplifiers and their supporting components significantly increases circuit complexity, consuming more area, more power, and necessitating careful calibration for correct performance. The use of a PMOS pass transistor MP, which relies on reduced-mobility charge carriers, further limits the efficiency and performance of regulator circuit 200.
In contrast, the illustrative voltage regulator circuit 300 of
Coupling capacitor CFF couples variations of the supply voltage VIN to the gate of current sink transistor M1, producing a ripple cancellation signal voltage VRC on the intermediate node. Coupling capacitor CFF combines with resistor RFF to act as a high pass filter. For supply voltage variations having frequencies above 1/2πRFFCFF, the cancellation signal voltage VRC includes negative variations at the corresponding frequencies. Inverting buffer 310 can be configured to provide a gain of −1 for the range of intermediate noise frequencies described above. Coupling capacitor CC and gate capacitance CG can act as an impedance voltage divider, scaling the cancellation signal VRC by 1/(1+CG/CC). The gate voltage of pass transistor M0 is the control signal VC (see
The coupling capacitance CC is accordingly chosen to match the negative variations of the cancellation signal voltage with the corresponding supply voltage variations in the intermediate noise frequency range.
In this fashion, the illustrated regulator directly subtracts the supply voltage noise from the regulated voltage, substantially improving the power supply rejection ratio (PSRR) at intermediate noise frequencies, leading to significantly reduced jitter and reduced bit error rates in SerDes modules using the illustrated voltage regulator. The use of capacitive coupling and inverting buffer greatly reduces complexity, area, and power consumption as compared with the regulator circuit 200 (
Numerous alternative forms, equivalents, and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, voltage regulator circuit 300 is implemented using NMOS transistors, but those familiar with the art will recognize how the disclosed principles can be used with other semiconductor technologies including PMOS, CMOS, JFET, and BJT. It is intended that the claims be interpreted to embrace all such alternative forms, equivalents, and modifications that are encompassed in the scope of the appended claims
