Patent Application
20090276642
The present invention relates to computer systems; more particularly, the present invention relates to regulating voltage in a microprocessor.
Growing demand for integrated circuits (ICs), for example microprocessors, with ever higher levels of performance and functionality have driven these devices to circuit densities beyond 100 million transistors per die. This number may soon exceed one billion transistors on a single die. The growth in transistor density has been made possible by the use of MOSFET transistors with gate lengths below 100 nm. As gate length has shortened, power supply voltages have fallen, in some cases, to below 1 V.
Even in a mobile computing environment (laptop), high-speed microprocessors, with clock speeds in excess of 2 GHz, may require in excess of 100 watts of power when operating at maximum load. With operating voltages below 1 V, this translates to power supply currents that reach beyond 100 A. Nevertheless, when used in a mobile environment, the same microprocessor must often draw less than 1 watt of “average power” due to battery considerations.
Integrated circuits are typically powered from one or more DC supply voltages provided by external supplies and converters. The power is provided through pins, leads, lands, or bumps on the integrated circuit package. The traditional method for providing such high power to integrated circuits may involve the use of a high-efficiency, programmable DC-to-DC (switch-mode) power converter located near the IC package.
This type of converter (buck regulator) may use a DC input voltage as high as 48V and provide a DC output voltage below 2 V. Conventional DC-to-DC power converters use switching frequencies in the neighborhood of 200 KHz, with some high-end units in the 1-2 MHz range. Such converters usually require a handful of relatively large components, including a pulse-width modulation (PWM) controller, one or more power transistors, filter and decoupling capacitors, and one or more large inductors and/or transformers.
Typical switch-mode power converters include one or more phases to supply the full output current. However, in many instances it may be inefficient to implement full operation of the converter, especially in applications that have low (e.g., nearly 0) current draw.
The invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
A voltage regulator having a suspend mode is described. In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
A chipset 107 may also be coupled to bus 105. Chipset 107 includes a memory control hub (MCH) 110. MCH 110 may include a memory controller 112 that is coupled to a main system memory 115. Main system memory 115 stores data and sequences of instructions that are executed by CPU 102 or any other device included in system 100. In one embodiment, main system memory 115 includes dynamic random access memory (DRAM); however, main system memory 115 may be implemented using other memory types. Additional devices may also be coupled to interconnect 105, such as multiple CPUs and/or multiple system memories.
MCH 110 is coupled to an input/output control hub (ICH) 140 via a hub interface. ICH 140 provides an interface to input/output (I/O) devices within computer system 100. In addition, computer system 100 includes a power supply 165 to provide power to CPU 102 and chipset 107. In one embodiment, power supply 165 is implemented as multiple cascaded supplies, where a first supply converts the AC input from a wall outlet to a set of standard voltage rails, and a set of downstream supplies (often referred to as a point-of-load regulators) convert the standard voltages to the less standardized voltages directly used by advanced logic ICs.
Referring back to
FSM control block 420 implements various FSMs to control various voltage control parameters. In one embodiment, FSM control block 420 includes ramp rate control, power throttle and loadline adjust current. VR 430 includes a compensator 432 and a pulsewidth modulator 436. Compensator 432 receives a target voltage from control block and compares the target voltage to an actual voltage received from one or more of the cores 0-3.
In response, compensator 432 generates an error term that is used to drive to zero error using negative feedback. Pulsewidth modulator 436 generates pulse signals to control current based upon the error term received from compensator 432. The pulse signals are transmitted from pulsewidth modulator 436 to power converter 210 to control the activation of the power FETs at each phase.
In normal operation, CPU 102 components may demand a very high current from power converter 210, which is generally the motivation for designing a voltage regulator with multiple phases. In normal operation, the current demand is generally high enough that multiple phases can continuously be pulsed, and the energy lost in continuous pulsing is small compared to the total current draw.
However at certain instances (e.g., where CPU 102 goes into a sleep state), it would be inefficient for power converter 210 to continuously pulse even a single phase. According to one embodiment, whenever the CPU 102 cores go into a sleep state, power control unit 250 and power converter 210 go into a suspend mode. In such an embodiment, a clock supplying power control unit 250 is deactivated.
In such an embodiment, the current draw at CPU 102 is sufficiently low so as to enable the charge stored at the output filter capacitors to supply power to CPU for a predetermined period of time. For example, if the CPU 102 sleep state duration is in a range of a few (e.g., 2-4) milliseconds operation at power control unit 250 and power converter 210 may be suspended until CPU 102 is reactivated. Thus, the power FET switches at power converter 210 are deactivated (e.g., no current generated by power converter 210) until CPU 102 is reactivated.
In another embodiment, power control unit 250 monitors the CPU 102 voltage whenever it and power converter 210 are in the suspend state. In this embodiment, power converter 210 remains in the suspend state until the voltage falls below a predetermined threshold (e.g., 1.2V). Once the voltage falls below the threshold, VR 430 exits the suspend state and transmits a pulse to activate one or both of the phases at power converter 210 in order to supply current to CPU 102. In a further embodiment, VR 430 may reenter the suspend state once current is supplied to CPU 102 as long as CPU 102 remains in the sleep state. Subsequently, the CPU 102 is again monitored by power control unit 250.
In yet another embodiment, whenever CPU 102 is in the suspend state and the CPU 102 voltage is above the threshold voltage, power converter 210 will enter an adaptive diode emulation mode. In such a mode, one phase is repeatedly sequenced through the following states: only upper FET on (UPPER state), only lower FET on (LOWER state), both FETs off (OFF state). Further, the repeated sequencing is performed at a largely fixed frequency, and the portion of time spent in each state is adapted to maintain a desired voltage. In another embodiment, the UPPER state time and the LOWER state time may be largely fixed, while the OFF state time is adapted to maintain a desired voltage.
The above-described power management mechanism yields an increase in battery life in a mobile computer system.
Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as essential to the invention.
This application is a continuation of U.S. patent application Ser. No. 11/416,534 filed on May 3, 2006.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11416534 | May 2006 | US |
| Child | 12502023 | US |
