This application claims the benefit of German Application No. 102020115851.3, filed on Jun. 16, 2020, which application is hereby incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present disclosure relates to the field of voltage regulator circuits, in particular to a low-dropout regulator (LDO regulator) having a fast step response to abrupt load current changes.
BACKGROUND
Voltage regulators (VREGs) with pass transistors coupled in series to the load are widely used in large integrated circuits (ICs) not only to provide stable supply voltages for various supply lines within the chip but also to separate supply lines at the same voltage in order to prevent or reduce coupling-in of noise and leakage. A typical example is separating the supply line of digital circuit portions, which are heavily impacted by switching noise, from the supply line of noise-sensitive analog circuit portions.
In such cases the VREG should minimize the transient overshoots or undershoots occurring in its regulated output voltage when the load current or the supply voltage abruptly varies. Usually, a decoupling capacitor is placed at the VREG output as a charge buffer that filters the transient step response to abrupt load changes. However, integrating sufficiently large capacitors or providing enough pins for external decoupling capacitors are expensive design choices which are not acceptable in many applications.
Apart from relying on large decoupling (filter) capacitors, typical approaches to improving the step response of an LDO regulator to load changes include: increasing the bandwidth of the voltage control loop; employing a high-slew rate error amplifier, and passive local feedback loops. However, the effectiveness of these approaches is limited as they tend to require large current consumption, and they only work with particular types of error amplifiers and pass transistors. In many cases, it is rather difficult to ensure the stability of the resulting LDO regulators because the circuitry that improves the transient response interferes with the operation of the voltage control loop.
In view of the above, there is room for improvement of LDO regulators with regard to their step response without requiring relatively large filter capacitors.
SUMMARY
A voltage regulator is described herein. In accordance with one embodiment, the voltage regulator includes a transistor having a load current path connecting an input node with an output node, wherein the input node is configured to receive an input voltage and the output node is configured to provide an output voltage. The voltage regulator further includes a main control loop coupled between the output node and a control electrode of the transistor and configured to control a voltage applied to the control electrode so that the output voltage matches a set-point. Furthermore, the voltage regulator includes a supplemental control loop that is coupled between the output node and the control electrode of the transistor and configured to detect a transient in the output voltage and to adjust the voltage applied to the control electrode in response to the detection of a transient.
Moreover, a voltage regulation method is described. In accordance with one embodiment, the method includes providing an output voltage to a load using a transistor that has a load current path connecting an input node with an output node. The method further includes controlling—using a main control loop—a voltage applied to a control electrode of the transistor so that the output voltage matches a set-point; detecting a transient in the output voltage; and adjusting the voltage applied to the control electrode in response to the detection of a slope. In one specific embodiment the output of the transient detector may be AC-coupled to the control electrode of the transistor.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be better understood with reference to the following drawings and descriptions. The components in the figures are not necessarily to scale; instead emphasis is placed on illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings:
FIG. 1 illustrates one example of a typical VREG structure;
FIG. 2 is an exemplary timing diagram illustrating the step response of the VREG of FIG. 1 to an abrupt increase of the load current;
FIG. 3 illustrates one embodiment of an improved VREG structure;
FIGS. 4a and 4b illustrate two exemplary implementations of a transient detector used in the embodiment of FIG. 3;
FIG. 5 is a flow chart illustrating the function of the circuit shown in FIG. 3;
FIG. 6 includes timing diagrams further illustrating the function of the circuit of FIG. 3
FIGS. 7a-7c and 8a-8b include various exemplary implementations of slope detection circuits which may be used in the transient detector of FIG. 4;
FIGS. 9a-9b and 10a-10b include various exemplary implementations of amplifiers which may be used in the transient detector of FIG. 5;
FIG. 11 is a circuit diagram illustrating one example of the transient detector composed of slope detectors constructed in accordance with FIG. 7b, and amplifiers constructed in accordance with FIG. 9a;
FIG. 12 is a circuit diagram illustrating one example of the transient detector composed of slope detectors constructed in accordance with FIG. 8a, and amplifiers constructed in accordance with FIG. 10; and
FIG. 13 is a circuit diagram illustrating one example of the transient detector composed of slope detectors constructed in accordance with FIG. 7c, and amplifiers constructed in accordance with FIG. 9a.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
In the following detailed description, reference is made to the accompanying drawings. The drawings form a part of the description and, for the purpose of illustration, show examples of how the embodiments may be used and implemented. FIGS. 1 and 2 illustrate a simplified circuit diagram of a VREG and, respectively, its step response to abrupt load current changes in a situation, in which the output capacitor has a capacitance small enough to not dominate the step response.
According to the example of FIG. 1 an LDO regulator uses a pass transistor T1 whose load current path is connected between an input node IN and an output node OUT to regulate the output voltage VOUT available at the output node. The pass transistor may be an MOS field effect transistor (MOSFET) for which the load current path is usually referred to as the drain-source current path (equivalent to collector-emitter current path in case of bipolar transistors). N-type or P-type MOS transistors may be used (corresponds to NPN and PNP type in case bipolar transistors are used instead of MOS transistors). The control electrode of the transistor T1, which is the gate in case of a MOS transistors and the base in case to a bipolar transistor, is connected to and driven by the output of an error amplifier EA, which is a difference amplifier such as, for example an operational amplifier. The error amplifier EA receives a reference voltage VREF at its non-inverting input and a feedback voltage VFB at its inverting input, and outputs the control voltage VG (gate voltage in case of a MOS transistor) which is supplied to the control electrode of transistor T1. The feedback voltage VFB represents the output voltage VOUT. In the depicted example, the feedback voltage VFB is proportional to the output voltage VOUT, wherein
That is, the voltage divider composed of the resistors R1 and R2 downscales the output voltage VOUT to obtain the feedback voltage VFB. The output capacitor COUT is connected between the output node OUT and ground node GND.
Given a step in the output current ILOAD from 0 amperes to a maximum value IMAX the maximum output voltage swing ΔVOUT,max and the response time Δt1 of the control loop can be approximated as follows:
wherein BWci is the closed-loop bandwidth of the system, tSR is the time needed to charge the parasitic gate capacitance CPAR of the pass transistor T1, ΔV is the voltage swing at the gate of the pass transistor, and ISR is the maximum current available to charge/discharge the parasitic gate capacitance CPAR.
Apart from relying on large decoupling capacitors, typical approaches to improving the step response of an LDO regulator to load changes include: increasing the bandwidth of the voltage control loop; employing a high-slew rate error amplifier, and passive local feedback loops. However, the effectiveness of these approaches is limited as they tend to require large current consumption, and they only work with particular types of error amplifiers and pass transistors. In many cases, it is rather difficult to ensure the stability of the resulting LDO regulators because the circuitry that improves the transient response interferes with the operation of the voltage control loop.
The embodiments described herein aim at overcoming at least some of these issues. According to some embodiments, a circuit for detecting fast transients (transient detector), which does not interfere with the operation of the main voltage-control loop, is added to the typical VREG structure shown in FIG. 1. The transient detector may be used together with several types of error amplifiers such as, for example, Miller operational transconductance amplifiers (OTAs) or folded cascode OTAs. These can be used together with both, N-type and P-type, pass transistors and are effective in reducing the transient output voltage overshoot/undershoot caused by sharp variations of the load current ILOAD.
FIG. 3 illustrates one embodiment which includes the mentioned transient detector. The circuit of FIG. 3 is the same as in FIG. 1 except for the additional transient detector TD that is coupled to the output node to receive the output voltage VOUT. Further, the transient detector has a first and a second output coupled to the gate electrode of the transistor T1 via a first capacitor CL2H and a second capacitor CH2L, respectively. As can be seen in FIG. 3, the transient detector forms part of a second, fast control loop that can operate independent from the main control loop formed by the error amplifier EA. The transient detector TD is configured to detect the slope (amplitude and sign) of output voltage transients, and the information is conveyed to two (one for each sign, i.e. positive and negative slopes) amplifiers that directly drive the gate electrode of transistor T1. The amplifiers are shown in FIG. 4a and FIG. 4b (denoted as amplifiers A1 and A2), illustrate two exemplary implementations of the transient detector TD of FIG. 3. Accordingly, the amplifiers A1 and A2 drive the gate of transistor T1 only during output voltage transients and their outputs are AC-coupled (i.e. DC-decoupled) to the gate of transistor T1 by using capacitors CH2L and CL2H (dependent on whether a positive or a negative slope is detected), so that in steady-state operation the transient detector TD does not interfere with the main voltage control loop. The example of FIG. 4a, includes one slope detection circuit 11 that is configured to detect positive slopes and negative slopes in the regulated output voltage Vo-r. Positive slopes are characterized by a positive time derivative (dVOUT/dt>0) while negative slopes are characterized by a negative time derivative (dVOUT/dt<0). The example of FIG. 4b, may be regarded as special case of the example of FIG. 4a. Accordingly, a first slope detection circuit 11a and a second detection circuit 11b are used to detect positive and, respectively, negative slopes.
When the value of the output voltage VOUT decreases—for example, due to a suddenly increasing load current—the slope detection circuit 11 generates a signal SLPN at its first output, which indicates the detection of the (negative) slope. The amplifier A1 receives the signal SLPN which triggers the injection of charge into (i.e. a charging of) the capacitor CL2H. As capacitor CL2H is connected between the output of amplifier A1 and the gate of the transistor T1, it follows that the gate voltage VG (and thus also the gate-source voltage VGS) of the transistor T1 increases, which results in a lower on-resistance RON of the transistor load current path. Therefore, the voltage drop across the transistor load current path is reduced which counteracts the output voltage decrease; the value of the output voltage VOUT again increases, even before the main voltage control loop (including the error amplifier EA) is able to react to the initial output voltage transient. Finally, the output voltage VOUT is driven back to its steady-state value with the help of the main feedback loop.
Similarly, when the value of the output voltage VOUT increases—for example, due to a suddenly decreasing load current—the slope detection circuit 11 generates a signal SLPP at its second output, which indicates the detection of the slope. The amplifier A2 receives the signal SLPP which triggers a discharge of the capacitance CH2L which is connected to the output of amplifier A2. As capacitor CH2L is connected between the output of amplifier A2 and the gate of the transistor T1, it follows that the gate voltage VG of transistor T1 decreases, which results in an increase of the transistors on-resistance RON. Therefore, the voltage drop across the transistor load current path is increased which counteracts the output voltage overshoot; the value of the output voltage VOUT again decreases, even before the main voltage control loop is able to react to the initial output voltage transient. Finally, the output voltage VOUT is driven back to its steady-state value with the help of the main feedback loop. It is understood that the slope detection circuit 11 may include a first slope detection circuit 11a for detecting positive slopes and a second slope detection circuit 11b for detecting negative slopes. In this case, which is illustrated in FIG. 4b, the first slope detection circuit 11a provides the signal SLPP and the second slope detection circuit 11b provides the signal SLPN.
Before discussing various implementations of the transient detector TD, the function of the transient detector TD is explained using the flow chart of FIG. 5. During steady state, the transient detector TD has no effect on the regulated output voltage VOUT because the transient detector is AC-coupled to (i.e. DC-decoupled from) the gate electrode of transistor T1. That is, during steady state, the transient detector TD is merely monitoring the output voltage VOUT (see FIG. 5, step S1). As soon as a transient occurs in the output voltage VOUT, the transient detector TD detects the transient (see FIG. 5, step S2), wherein two cases are distinguished. At the onset of the transient the slope of the voltage VOUT is either positive (dVOUT/dt>0) or negative (dVOUT/dt<0). The first case is indicated by the level of signal SLPP falling to a LOW level (see FIG. 5, step S3, SLPP having a HIGH level during steady state and falls to lower values upon occurrence of a positive slope). Similarly, the second case is indicated by the level of signal SLPN rising to a HIGH level (see FIG. 5, step S4, SLPN having a LOW level during steady state and rises to higher values upon occurrence of a negative slope). The signals SLPP and SLPN are amplified (cf. FIG. 3, amplifiers A1 and A2) and—due to the amplifiers A1 and A2 being AC coupled to the gate of transistor T1—the gate voltage VG decreases (see FIG. 5, step S5) or increases (see FIG. 5, step S6) thereby counteracting the respective transient. This mechanism (steps S3 and S5 or S4 and S6) is maintained as long as the output voltage changes, i.e. as long as the time derivative dVOUT/dt of the output voltage VOUT is positive or negative (see FIG. 5, steps S7 and S8). When the transient has decayed, the transient detector TD again monitors the output voltage VOUT for a further transient (see FIG. 5, step S1). As will be discussed later, the concept illustrated in FIG. 5 can be modified to ensure that the transient detector will only become active when the steepness of the slope is above a specific threshold value TH. In this case, the conditions illustrated in FIG. 5, step S2, are dVOUT/dt>TH for positive slopes and dVOUT/dt<−TH for negative slopes. It is understood that different threshold absolute values may be applied for positive and negative slopes. The threshold may be readily implemented by providing an offset current at the input of the amplifiers A1, A2 (see, e.g. FIG. 9, offset current iCLAMP).
The mechanism explained above with reference to the flow chart of FIG. 5 is further illustrated by the timing diagrams of FIG. 6. In the example of FIG. 6, the load current iLOAD rises from a relatively low level to a higher level at time instant t1 and falls back to the initial low level at time t3 (see top timing diagram of FIG. 6). As a result of the load current change transients occur in the output voltage signal VOUT, wherein the first transient (at t1) starts with a negative slope (due to the rising load current) and the second transient (at t3) starts with a positive slope. The transients reach their respective maximum voltage swing at time instants t2 and t4, respectively (see second timing diagram of FIG. 6). The corresponding signals SLPN and SLPP generated by the slope detection circuit 11 (or the slope detection circuits 11b and 11a, respectively), are illustrated in the third and fourth timing diagram of FIG. 6.
As mentioned above, during steady state (for example before t1) the signal SPLN is at a LOW level and the signal SLPP is at a HIGH level. At time t1—i.e. at the onset of the negative slope—the signal SLPN rises to higher levels. Similarly, at time t3—i.e. at the onset of the positive slope—the signal SLPP drops to lower levels. The signals SLPN and SLPP are amplified by amplifiers A1 and A2 (see FIGS. 3 and 4). These amplifiers may be current output amplifiers, and the output current of the amplifiers charge/discharge the coupling capacitors CL2H and CH2L. The corresponding amplifier output voltages VL2H and VH2L are shown in the fifth and the sixth diagram of FIG. 6. It is noted that it may take some time until the capacitor voltages and thus the voltages VL2H and VH2L return to their steady state values (see FIG. 6, times t2′ and t4′).
FIGS. 7 and 8 illustrate various exemplary implementations of slope detection circuits which may be used in the transient detector of FIGS. 3 and 4. In these implementations the slope detectors have a current output, i.e. the signals SPLN and SPLP are represented by currents iSLPN and iSLPP. For example, FIG. 7a illustrates a simple differentiator circuit composed of a capacitor CD that is used as differentiator and connected to a transistor TD operating as a MOS diode (i.e. a transistor TD whose gate is biased with the drain voltage). The current iSLPP passing through the capacitor CD is substantially proportional to the (positive) time derivative dVOUT/dt of the monitored output voltage. Various implementations of differentiator circuits exist. In an alternative example, the transistor is replaced by a simple resistor to obtain an RC differentiator circuit. In the examples described herein, a passive circuit element like a capacitor CD is used as differentiator. It is understood that active differentiators may also be used instead, which e.g. include one or more operational amplifiers.
FIG. 7b illustrates a further exemplary implementation of a (negative) slope detection circuit. In this example, a bias current source QBIAS (providing current i) is connected between ground and the source electrode of a transistor TD whose gate is biased with a constant volt VBIAS. Further, the source electrode of transistor TD is coupled to the output voltage VOUT to be monitored. The bias voltage VBIAS is set to a value such that the current source QBIAS remains active during negative slopes of the output voltage signal VOUT. As a result, the drain current iSLPN of transistor TD increases above the value of bias current iB in response to the negative slope of output voltage VOUT.
FIG. 7c illustrates another exemplary implementation of a slope detection circuit, which is able to detect both, positive and negative slopes in the output voltage to be monitored. In this example, a first current mirror composed of n-channel MOS transistors TD1 and TD1′ and a second current mirror composed of p-channel MOS transistors TD2 and TD2′ are coupled in series as shown in FIG. 7c. Accordingly, the source electrodes of the transistors TD1′ and TD2′ are connected at a circuit node which is biased with a voltage VCM (common mode voltage). The drain electrodes of the transistors TD1′ and TD2′ are connected with the respective gate electrodes. Thus, the transistors TD1′ and TD2′ form the input branches of the two current mirrors. Further, the drain electrode of transistor TD2′ is coupled with a low supply potential (e.g. ground potential) via a current source QBIAS2. Similarly, the drain electrode of transistor TD1′ is coupled with a high supply potential VS via another current source QBIAS1. The load current paths of transistors TD1′ and TD2′ may be regarded as input branches of the current mirrors.
The source electrodes of transistors TD1 and TD2, whose load current paths may be regarded as output branches of the current mirrors, are connected to each other at a circuit node that is coupled to the output voltage to be monitored via a capacitor CD. The drain currents of transistors TD1 and TD2 are denoted as iSLPN and, respectively, iSLPP and represent the signals SLPN and SLPP discussed above and shown in FIG. 4. During steady state, the drain currents of TD1 and TD2 are equal to bias currents iB set by current sources QBIAS1 and, respectively, QBIAS2. During a negative slope of the output voltage VOUT, the current passing through capacitor CD will be subtracted from the common circuit node of the source electrodes of transistors TD1 and TD2. As a result, the drain currents iSLPN will increase and iSLPP will decrease by the same difference amount. Similarly, a positive slope in the output signal VOUT will cause a current through capacitor CD that will be injected into the common circuit node of the source electrodes of transistors TD1 and TD2. Consequently, the drain currents iSLPP will increase and iSLPN will decrease by the same amount. In essence, the examples of FIGS. 7b and 7c may be regarded as current buffers having a differentiator (differentiating element, capacitor CD) coupled to their inputs.
FIG. 8 illustrates two further exemplary implementations of slope detection circuit, which make use of differential pairs (also known as long-tailed pairs). In the example of FIG. 8a, the source electrodes of transistors TL and TR are connected via two resistors R, wherein the common circuit node M between the two resistors R is coupled to the lower supply potential (ground potential) via a bias current source QBIAS providing a bias current iB. The gate electrodes of both transistors TL and TR are biased with a bias voltage VBIAS. The drain current of transistor TL is the output current iSLPN. The output voltage VOUT to be monitored is coupled to the source electrode of transistor TL via capacitor CD. The example of FIG. 8b, is constructed very similar to the example of Fig. a. However, in FIG. 8b the resistors R can be omitted and the source electrodes are directly connected to circuit node N. Instead, a resistor RD is connected between the gate electrodes of transistors TR and TL, and the output voltage VOUT to be monitored is coupled to the gate electrode of transistor TL. It is understood that differential pairs are commonly used in difference amplifiers and thus as such known to a skilled person and not discussed in greater detail herein.
FIG. 9 illustrates two exemplary implementations of current amplifiers that may be used in the transient detector of FIG. 4 (cf. FIG. 4, amplifiers A1 and A2). The two examples illustrated in FIGS. 9a and b, are based on a 1:K current mirror wherein K denotes the gain. According to the example of FIG. 9a, the load current path of transistor TL forms the input branch and the load current path of transistor TR forms the output branch of the current mirror. The gate electrodes of both transistors, TR and TL, are connected to the drain electrode of transistor TL to form the current mirror. The input current iSLPP is received at the drain electrode of the transistor TL and the amplifier output voltage VH2L is provided at the drain electrode of transistor TR, which is coupled to the upper supply potential VS via a current source providing the bias current iB.
A further current source providing a current iCLAMP is connected in parallel to the load current path of transistor TL. This current iCLAMP can be considered as an offset current subtracted from the current to be amplified. This offset current has the effect that the transient detector does not react to transient with relatively flat slopes. FIG. 9b illustrates a minor modification, in which a second transistor TL′ is connected in series to transistors TL to obtain an amplifier with a non-linear increasing gain.
The examples of FIG. 10 illustrate two variants of a common-source amplifier stage which may be used as amplifiers A1 and A2 (see FIG. 4). The amplifier in FIG. 10a, uses an n-channel MOS transistor T1 for amplifying the signal SLPP (current iSLPP), whereas the amplifier in diagram (b) uses a p-channel MOS transistor T2 for amplifying the signal SLPN (current iSLPN). The drain electrodes of transistors T1 and T2 are connected to the (lower and, respectively, upper) supply voltage via current sources providing bias current iB. Similar as in the previous examples of FIG. 9, current sources providing an offset current iCLAMP are connected between the gate electrode of Transistor T1 and T2 and the (lower and, respectively, upper) supply voltage.
FIG. 11 illustrates one example of the transient detector TD which is composed of slope detection circuits 11a and 11b for detecting positive and, respectively, negative slopes in the output voltage VOUT to be monitored and amplifiers A1 and A2. In the depicted example, the slope detection circuit 11b corresponds to the circuit of FIG. 7b. The slope detection circuit 11a is the complementary circuit using p-channel MOS transistor TDP (instead of the n-channel MOS transistor TDN used in the slope detection circuit 11b). The amplifier A2 in FIG. 11 corresponds to the current mirror circuit of FIG. 9a. The amplifier A1 in FIG. 11 is the complementary circuit using p-channel MOS transistors TLP and TRP (instead of the n-channel MOS transistors TLN and TRN used in amplifier A2).
It is understood that the example of FIG. 11 can be modified by using the common-source amplifiers in accordance with FIG. 10a and FIG. 10b, as amplifiers A2 and A1, respectively (instead of the current mirror circuit of FIG. 9). A further embodiment may be obtained by combining differential pairs in accordance with FIG. 8 (as slope detectors) and current mirror circuits in accordance with FIG. 9 (as amplifiers). The example of FIG. 12 illustrates another example of the transient detector TD which is composed of slope detection circuits 11a and 11b, which are constructed as differential pairs in accordance with FIG. 8a, and amplifiers, which are constructed as common source circuits in accordance with FIG. 10. The differential pair forming the negative slope detection circuit 11b corresponds to the circuit of FIG. 8a. The positive slope detection circuit 11a is the complementary circuit which uses p-channel MOS transistors instead of n-channel MOS transistors. The differential pairs are loaded with current mirrors that are implemented by transistors TQ1, TQ1′ (for neg. slope detection circuit 11b) and TQ2, TQ2′ (for pos. slope detection circuit 11a). Transistors TQ1′ and TQ2′ are sized N times larger than TQ1 and, respectively, TQ2 such that they provide a suitable offset current which is subtracted from iSLPN and, respectively, iSLPP. Current mirrors as active loads for difference amplifiers are commonly known to a skilled person and thus not further discussed herein. In the current embodiment, the current mirrors have a further output branch formed by transistors TQ1″ and TQ2″ which are coupled as active loads to the drains of the transistors T1N and, respectively, T1P, which form the common source amplifiers A2 and A1. In the general example of FIG. 10, these active loads are symbolized by the current sources providing bias current iB.
A further exemplary implementation of the transient detector TD is illustrated in FIG. 13. The depicted example is basically a combination of the slope detection circuit 11 of FIG. 7c, and the amplifiers A1, A2 constructed in accordance with FIG. 9a. Amplifier A2 corresponds to the example of FIG. 9a, and amplifier A1 is the complementary circuit using complementary transistor types (p-channel MOS transistors instead of n-channel MOS transistors). It is noted that the slope detection circuit 11 may be regarded as a combination of a positive slope detection circuit 11a, which is substantially formed by the current mirror of transistors TD2 and TD2′, and a negative slope detection circuit 11b, which is substantially formed by the current mirror of transistors TD1 and TD1′. Different to the previous examples of FIGS. 11 and 12, only one differentiator—capacitor CD—is needed in the depicted example. The capacitor CD is used by both parts 11a and 11b of the slope detection circuit 11.
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (units, assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond—unless otherwise indicated—to any component or structure, which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure, which performs the function in the herein illustrated exemplary implementations of the invention.
Patent Application
20210389790
