Patent Application
20170322573
The present document relates to a voltage regulator. In particular, the present document relates to a voltage regulator exhibiting reduced internal losses and/or reduced internal current, notably in case of dropout situations.
Voltage regulators are frequently used for providing a load current at a stable load voltage to different types of loads (e.g. to the processors of an electronic device). A voltage regulator derives the load current from an input node of the regulator, while regulating the output voltage at the output node of the regulator in accordance to a reference voltage.
The present document addresses the technical problem of providing a voltage regulator which exhibits reduced internal losses and/or reduced internal current, notably in case of dropout situations. According to an aspect, a regulator (notably a voltage regulator such as a low dropout regulator) is described. The voltage regulator is configured to provide an output current at an output voltage at an output node, based on an input voltage at an input node.
The voltage regulator comprises a pass transistor (notably an n-type MOS transistor) for deriving the output current at the output node from the input voltage at the input node. Furthermore, the voltage regulator comprises a drive transistor forming a current mirror in conjunction with the pass transistor, such that the output current through the pass transistor is dependent on (e.g. proportional to) a drive current through the drive transistor. In addition, the voltage regulator comprises an auxiliary transistor arranged such that at least a fraction of the drive current through the drive transistor flows through the auxiliary transistor. Furthermore, the voltage regulator comprises amplification circuitry configured to set the drive current through the drive transistor in dependence of the output voltage and in dependence of a reference voltage, if the voltage regulator is regulating the output voltage.
The voltage regulator further comprises control circuitry which is configured to detect an indication for a dropout situation for which a difference between the input voltage and the output voltage falls below a dropout voltage of the voltage regulator. The control circuitry is further configured, in reaction to this, to increase a resistance of the auxiliary transistor to reduce the fraction of the drive current flowing through the auxiliary transistor.
By increasing the resistance of an auxiliary transistor, the internal current of the voltage regulator may be reduced during dropout situations, thereby increasing the power efficiency of the voltage regulator.
According a further aspect, a corresponding method for operating a voltage regulator is described.
In the present document, the term “couple” or “coupled” refers to elements being in electrical communication with each other, whether directly connected e.g., via wires, or in some other manner.
The invention is explained below in an exemplary manner with reference to the accompanying drawings, wherein
As outlined above, the present document is directed at providing a voltage regulator with reduced internal losses. An example of a voltage regulator is an LDO (low dropout) regulator. A typical LDO regulator 100 is illustrated in
The LDO regulator 100 of
In addition, the LDO regulator 100 may comprise an output capacitance Cout (also referred to as output capacitor or stabilization capacitor or bybass capacitor) 105 parallel to the load 106. The output capacitor 105 is used to stabilize the output voltage VOUT subject to a change of the load 106, in particular subject to a change of the requested load current or output current Iload/IOUT.
The present document is directed at increasing current efficiency when a voltage regulator 100 (notably an NMOS LDO) is close to dropout or in dropout conditions. In such situations, the regulation of the voltage regulator typically causes relatively large internal currents while trying to maintain a stable operation condition (notably while trying to maintain a stable output voltage). In this context, it is desirable to maximize the gate drive (i.e. the gate voltage) for the pass transistor 201, wherein the gate drive may be dependent on the supply voltage of the voltage regulator 100 and/or on the input voltage Vin of the voltage regulator 100 and/or by stress limits of the oxide gate of the pass transistor 201. In the present document, circuitry is described which reduces the internal currents of the voltage regulator 100 in such a Loss-of-Regulation (LoR) condition (in particular in a dropout situation). The situation of a limited supply voltage and/or input voltage Vin may be considered to be a special case for such an LoR condition. In particular, the circuitry enables maximum allowable gate voltages for the pass transistor 201 (to reduce losses at the pass transistor 201) and reduced internal drive currents (to reduce internal losses of the voltage regulator 100) within a dropout situation.
The voltage regulator 100 may comprise a variable impedance within the output stage 103, 110, 201. This is illustrated in
In case of a gain reduction, the voltage regulation loop of the voltage regulator 100 reacts in order to maintain regulation. This may be detected by observing internal nodes of the regulator 100. As soon as gain reduction (i.e. a dropout condition) is detected, the variable impedance 214 may be increased by the gain control unit 213 and by doing this the required current for driving pass transistor 201 may be reduced, thereby increasing efficiency. The driver stage unit 212 may be configured to maintain a controlled input current under all supply voltage 131 conditions.
As illustrated in
The circuitry 300 further comprises a voltage clamp circuit 303 for clamping the gate of the NMOS drive diode 114. Furthermore, the circuitry 300 comprises a current limit circuit comprising the NMOS transistors 304, 305, 306 and the current source 308, which acts on the voltage clamp circuit 303. The current limit circuit forms the current control unit 211 of
The gate voltage of the pass transistor 201 should remain limited (to a certain maximum value) at any time. Once the gate voltage reaches such a limit, a loss-of-regulation (LoR) condition occurs. In case of a loss-of-regulation condition, the internal drive current 220 should be reduced, while maintaining the gate voltage limited, thereby increasing efficiency of the regulator 100.
The voltage clamp circuit 303 limits the gate-source voltage across the pass transistor 201 and stops a further increase of the drive current through the drive current transistor 111. The auxiliary transistor 302 reduces the current which is required for achieving this condition.
While the current limit circuit 304, 305, 306, 308 discharges the gate voltage of a current limit transistor 306 in order to reach the low regulation limit voltage (which is approximately the threshold voltage Vth of the current limit transistor 306), the auxiliary transistor 302 is also turned off. The parallel device 301 is then defining the minimum current flowing within this branch. The current limit would then settle into this lower current requirement set by device 301.
In case of a LoR condition, a voltage increase occurs within the second stage 102. This activates the control circuit 400 for the voltage clamping circuit 302 via the transistor 404, the current mirror 403, 402 and the current source 401. As a result of this, the auxiliary transistor 302 is turned off, thereby reducing the current of the current limit loop 304, 305, 306, 308. There are a few gates shown as unconnected in
As a result of this, the VDS (drain-source) voltage across the transistor 113 is also applied across the transistor 112 to enforce the same operating point and to maintain linearity of the current mirror ratio.
As a result of reducing the drive current (and of increasing the impedance), the pole of the output node at the transistor 302 typically changes.
A LoR condition may occur, when the input voltage 131 drops below the output voltage 132. As a result of this, the output voltage 132 eventually drops to the level of the input voltage 131, thereby causing the gate of the pass transistor 201 to rise (in order to counter the drop of the output voltage 132). The increased gate voltage may be detected e.g. using the control circuit 400 of
It may occur that gain limitation is caused by other conditions e.g. an insufficient drive voltage across drive diode 114, when the supply voltage VDD 133 and the output voltage Vout 132 are too close. In this case the output of the second stage 102 would react, but the VGS limit loop (notably control circuit 400) would not be activated.
As such, the present document describes a voltage regulator 100 which is configured to provide an output current at an output voltage 132 at an output node of the voltage regulator 100, based on an input voltage 131 at an input node of the voltage regulator 100. The input voltage 131 may be different from a supply voltage 133 which is used for operating the voltage regulator 100. In particular, the input voltage 131 may be closer to the (target) output voltage 132 than the supply voltage 133, thereby increasing the efficiency of the voltage regulator 100.
The voltage regulator 100 comprises a pass transistor 201 (notably an NMOS or n-type metal oxide semiconductor transistor) for deriving the output current at the output node from the input voltage 131 at the input node. Furthermore, the voltage regulator 100 comprises a drive transistor 114 (notably an NMOS transistor) forming a current mirror in conjunction with the pass transistor 201, such that the output current through the pass transistor 201 is dependent on (notably proportional to) a drive current through the drive transistor 114 (notably to the drive diode 114). In particular, a gate of the pass transistor 201 may be (directly) coupled to a gate of the drive transistor 114. Furthermore, the sources of the pass transistor 201 and the drive transistor 114 may be (directly) coupled.
In addition, the voltage regulator 100 comprises an auxiliary transistor 302 (notably an NMOS transistor) which is arranged such that at least a fraction of the drive current through the drive transistor 114 flows through the auxiliary transistor 302. In particular, the source of the auxiliary transistor 302 may be (directly) coupled to the drain of the drive transistor 114. Furthermore, the drain of the auxiliary transistor 302 may be (directly) coupled to the gate of the drive transistor 114.
The voltage regulator 100 further comprises amplification circuitry 101, 102 which is configured to set the drive current through the drive transistor 114 in dependence of the output voltage 132 (notably of a feedback voltage 107 which is derived from, e.g. which is proportional to, the output voltage 132) and in dependence of a reference voltage 108, if the voltage regulator 100 is regulating the output voltage 132. The amplification circuitry 101, 102 may comprise a differential amplification stage 101 (notably a differential amplifier) which is configured to determine a first intermediate output voltage in dependence of the output voltage 132 and in dependence of the reference voltage 108. Furthermore, the amplification circuitry 101, 102 may comprise a drive current transistor 111 (e.g. an NMOS transistor) which is configured to generate an internal current in dependence of the first intermediate output voltage. The drive current may then be derived from the internal current (e.g. using a current mirror 112, 113). Furthermore, the amplification circuitry 101, 102 may comprise a second amplification stage 102 which is configured to generate a second intermediate output voltage in dependence of the first intermediate output voltage. The drive current transistor 111 may then be configured to generate the internal current in dependence of the second intermediate output voltage.
The voltage regulator 100 further comprises control circuitry 300, 400 which is configured to detect an indication for a dropout situation. A dropout situation may be a situation for which a difference between the input voltage 131 and the output voltage 132 falls below a dropout voltage of the voltage regulator 100. As a result of this, the voltage regulation loop of the voltage regulator 100 may be disturbed. The indication for the dropout situation may be detected e.g. based on the drive current (as illustrated e.g. in the context of
The control circuitry 300, 400 may be configured to increase a resistance of the auxiliary transistor 302 in order to reduce the fraction of the drive current flowing through the auxiliary transistor 302, in reaction to detecting an indication for a dropout situation. As a result to this, the internal current within the voltage regulator 100 may be reduced during dropout of the voltage regulator 100, thereby reducing the power consumption of the voltage regulator 100.
The voltage regulator 100 may comprise a resistive device 301 which is arranged in parallel to the auxiliary transistor 302, wherein the resistive device 301 may e.g. comprise a resistor. The (entire) drive current may then flow through the parallel arrangement of the auxiliary transistor 302 and the resistive device 301. By making use of a resistive device 301, the internal current within the voltage regulator 100 may be limited in a reliable and precise manner.
The voltage regulator 100 may comprise circuitry 304, 305, 308 for determining an indication of the drive current and for comparing the indication of the drive current with a first dropout reference current. In particular, the control circuit 300, 400 may comprise a first current mirror 304, 305 (notably an NMOS current mirror) and a first current source 308, wherein the first current source 308 is configured to provide the first dropout reference current. A first input transistor 304 (notably an NMOS transistor) of the first current mirror 304, 305 may be coupled to the auxiliary transistor 302. In particular, a drain of the first input transistor 304 may be (directly or indirectly) coupled to a drain of the auxiliary transistor 302. A first output transistor 305 (e.g. an NMOS transistor) of the first current mirror 304, 305 may be coupled to the first current source 308.
The circuitry 304, 305, 308 for determining an indication of the drive current and for comparing the indication of the drive current with a first dropout reference current may be part of the control circuit 300, 400, and the indication for a dropout situation may be detected based on the comparison between the indication of the drive current and the first dropout reference current. In particular, a gate of the auxiliary transistor 302 may be coupled to a midpoint between the first output transistor 305 and the first current source 308, notably via an offset voltage 307. As a result of this, the auxiliary transistor 302 may be turned off (e.g. with a certain delay given by the offset voltage 307), if the midpoint between the first output transistor 305 and the first current source 308 indicates that the drive current increases (e.g. beyond the first dropout reference current). Hence, a reliable detection for a dropout situation is provided.
The voltage regulator 100 may comprise a voltage clamp transistor 303 (e.g. a PMOS transistor) which is configured to clamp the drive voltage at the gate of the pass transistor 201 to a fixed voltage level (notably if a dropout situation has been detected). The voltage clamp transistor 303 may be arranged in series with the first input transistor 304. Furthermore, the (source of the) voltage clamp transistor 303 may be coupled to the gate of the pass transistor 201 and to the drain of the auxiliary transistor 302. Furthermore, the drain of the voltage clamp transistor 303 may be coupled (directly) to the drain of the first input transistor 304. By clamping the gate of the pass transistor 201 to a fixed voltage level, the pass transistor 201 and/or the drive transistor 114 may be protected during a dropout situation, while maintaining the pass transistor 201 turned on (to reduce power losses of the voltage regulator 100).
The voltage regulator 100 may comprise a current limit transistor 306 (e.g. an NMOS transistor) which is arranged in series with the drive current transistor 111. In particular, a drain of the current limit transistor 306 may be coupled to a source of the drive current transistor 111. The current limit transistor 306 may be controlled based on the comparison between the indication of the drive current and the first dropout reference current, notably based on the voltage level at the midpoint between the first output transistor 305 and the first current source 308. For this purpose, the gate of the current limit transistor 306 may be coupled (directly) to the midpoint between the first output transistor 305 and the first current source 308. By making use of a current limit transistor 306, the current limitation within the voltage regulator 100 may be further improved.
The voltage regulator 100 may comprise a second current mirror 112, 113 (e.g. a PMOS current mirror) which comprises a second input transistor 112 (e.g. a PMOS transistor) which is arranged in series with the drive current transistor 111 and a second output transistor 113 (e.g. a PMOS transistor) which is arranged in series with the auxiliary transistor 302. In particular, a drain of the second input transistor 112 may be (directly) coupled to a drain of the drive current transistor 111. Furthermore, a drain of the second output transistor 113 may be (directly) coupled to the drain of the auxiliary transistor 302. The second current mirror 112, 113 may be used to generate the drive current from the current flowing through the drive current transistor 111.
As indicated above, the second current mirror 112, 113 may be a p-type current mirror. The voltage regulator 100 may comprise circuitry 500 for enforcing the gate-drain voltage across the second input transistor 112 to be equal to the gate-drain voltage across the second output transistor 113. By doing this, the linearity of the second current mirror 112, 113 may be improved.
The control circuit 300, 400 may be configured to control the auxiliary transistor 302 in dependence of the second intermediate output voltage. In other words, a dropout situation may be detected based on the second intermediate output voltage. The control circuit 300, 400 may comprise circuitry 404 (e.g. a (PMOS) transistor) for generating a control current in dependence of the second intermediate output voltage. The second intermediate output voltage may be applied to a source of the PMOS transistor. Furthermore, the control circuit 300, 400 may comprise circuitry 401, 402, 403 for comparing the control current with a second dropout reference current, wherein the auxiliary transistor 302 is controlled in dependence of the comparison between the control current and the second dropout reference current. In particular, the circuitry 401, 402, 403 for comparing may comprise a current mirror 402, 403 and a current source 401 for generating the second dropout reference current. A midpoint between the output transistor 402 of the current mirror 402, 403 and the current source 401 may be (directly) coupled to the gate of the auxiliary transistor 302. By doing this, a dropout situation may be detected in a reliable manner and internal currents may be reduced accordingly.
The amplification circuitry 101, 102 may be operated using a supply voltage 133 which is different from the input voltage 131 (wherein the supply voltage 133 is typically higher than the input voltage 131). The pass transistor 201 is typically controlled via a drive voltage applied to the gate of the pass transistor 201. The voltage regulator 100 may comprise a second auxiliary transistor 902 (e.g. a PMOS transistor) which is arranged in series with the drive current transistor 111. A drain of the second auxiliary transistor 902 may be coupled to the drain of the drive current transistor 111. Furthermore, a source of the second auxiliary transistor 902 may be coupled to the drain of the second input transistor 112 of the second current mirror 112, 113. Furthermore, a second resistive device (e.g. a resistor) may be arranged parallel to the second auxiliary transistor 902.
The voltage regulator 100 may comprise second control circuitry 900 which is configured to detect an indication for a situation where the drive voltage is insufficient for enabling the voltage regulator 100 to regulate the output voltage 132. Such a situation may occur e.g. when the supply voltage 133 becomes too close to the output voltage 132. The control circuitry 900 may be further configured, in reaction to detecting such a situation, to increase a resistance of the second auxiliary transistor 902 to reduce the internal current through the drive current transistor 111. By doing this the power efficiency of the voltage regulator 100 may be further increased.
The voltage regulator 100 may comprise decoupling circuitry 700, 802, 813, 814 for decoupling the amplification circuitry 101, 102 from a gate capacitance 701 of the pass transistor 201. The decoupling circuitry 700, 802, 813, 814 may comprise e.g. a buffer 700 which is arranged between the gate of the drive transistor 114 and the gate of the pass transistor 201. Alternatively or in addition, the decoupling circuitry 700, 802, 813, 814 may comprise e.g. replica circuitry 813, 814, 802 of the auxiliary transistor 302 and of the drive transistor 114. By making use of decoupling circuitry 700, 802, 813, 814, the stability of the voltage regulator 100 may be increased (notably during dropout situations).
The method 1000 comprises detecting 1001 an indication for a dropout situation during which a difference between the input voltage 131 and the output voltage 132 falls below a dropout voltage of the voltage regulator 100. Furthermore, the method 1000 comprises, in reaction to this, increasing 1002 a resistance of the auxiliary transistor 302 to reduce the fraction of the drive current flowing through the auxiliary transistor 302.
It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102016207714.7 | May 2016 | DE | national |
