Voltage sustainer for above V.sub.CC level signals

Abstract

This present invention provides a voltage sustainer which eliminates the DC current problems of conventional voltage sustainers. The embodiment of the voltage sustainer of the present invention comprises a first field effect transistor (FET) having its drain connected to a supply voltage and its drain connected to a second FET; a second FET having its drain connected to the source of the first FET, its source connected to an output node and its gate connected to the source of a third FET; a third FET having its source connected to the gate of the second FET and its drain connected to the output node; a first MOS capacitor having one side connected to receive an input signal and its other side connected to the interconnection between the source of the first FET and the drain of the second FET; and a second capacitor having one side connected to receive the input signal and its other side connected to the source of the third FET.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuits and, in particular, to an improved integrated voltage sustainer circuit.

2. Discussion of the Prior Art

As shown in FIG. 1, a conventional voltage sustainer includes two field effect transistors (FETs) 10 and 12 which are sequentially connected, in diode configuration, between a supply voltage V.sub.CC and an output node A. An MOS capacitor 14 has one of its sides connected to receive an input signal .phi.s. The other side of capacitor 14 is connected to the interconnection between the source of transistor 10 and the drain of transistor 12. The input signal .phi.s toggles between OV and V.sub.CC. When the input signal .phi.s goes low, node B in FIG. 1 is precharged to V.sub.CC -VT through transistor 10, where V.sub.T is the threshold voltage of each of the two transistors 10 and 12. When input .phi.s goes high, node B is pumped by capacitor 14 to 2V.sub.CC -V.sub.T. This voltage travels through transistor 12 and sustains node A at 2V.sub.CC -2V.sub.T.

The disadvantage of the conventional voltage sustainer configuration illustrated in FIG. 1 is that if node A goes low, i.e. to ground, than DC current is initiated from the supply V.sub.CC through both transistor 10 and transistor 12 to ground.

SUMMARY OF THE INVENTION

This present invention provides a voltage sustainer which eliminates the DC current problems associated with conventional voltage sustainers. A preferred embodiment of the voltage sustainer of the present invention comprises a first field effect transistor (FET) having its drain connected to a supply voltage and its source connected to a second FET; a second FET having its drain connected to the source of the first FET, its source connected to an output node and its gate connected to the source of a third FET; a third FET having its source connected to the gate of the second FET and its drain connected to the output node; a first MOS capacitor having one side connected to receive an input signal and its other side connected to the interconnection between the source of the first FET and the drain of the second FET; and a second MOS capacitor having one side connected to receive the input signal and its other side connected to the source of the third FET.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simple schematic diagram illustrating a conventional voltage sustainer circuit.

FIG. 2 is a schematic diagram illustrating a preferred embodiment of a voltage sustainer circuit in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 illustrates a preferred embodiment of a voltage sustainer circuit in accordance with the present invention.

As shown in FIG. 2, two field effect transistors (FETs) 20 and 22 are sequentially connected between a supply voltage V.sub.CC and an output Node A. An input signal .phi.s is commonly provided both to the input side of MOS capacitor 24 and to the input side of MOS capacitor 26. The opposite sides of both capacitor 24 and of capacitor 26 are connected to node B and node C, respectively. Node B is the common connection between the source of transistor 20 and the drain of transistor 22. Node C is connected to the gate of transistor 22. A third FET 28 has its source connected to node C and its drain connected to the output node A.

Thus, to overcome the DC current problem described above with respect to the prior art, and in accordance with the present invention, capacitor 26 and transistor 28 have been added to the conventional voltage sustainer configuration shown in FIG. 1.

In the circuit shown in FIG. 2, if node A goes to ground, then node C is discharged to ground through transistor 28. Thus, DC current flow is prevented. When node A goes high to above the supply level V.sub.CC, then node C is precharged to V.sub.CC -V.sub.T through transistor 28. In this case, the input signal .phi.s will pump both nodes B and C, via capacitors 24 and 26, respectively, to 2V.sub.CC -V.sub.T which travels through transistor 22 and sustains node A at the 2V.sub.CC -2V.sub.T level.

Thus, the voltage sustainer of the present invention provides the same capability to sustain node A at the 2V.sub.CC- -2V.sub.T level as does the conventional sustainer shown in FIG. 1, but eliminates the DC current problem.

It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that structure within the scope of these claims and their equivalents be covered thereby.

Claims

1. A circuit for sustaining a preselected voltage level, the circuit comprising:

(a) a first field effect transistor (FET) having its drain connected to a supply voltage and its source connected to a second FET;

(b) said second FET having its drain connected to the source of the first FET, its source connected to an output node and its gate connected to the source of a third FET;

(c) said third FET having its source connected to the gate of the second FET and its drain connected to the output node;

(d) a first capacitor having one side connected to receive an input signal and its second side connected to the interconnection between the source of the first FET and the drain of the second FET; and

(e) a second capacitor having one side connected to receive the input signal and its other side connected to the source of the third FET.