WAFER BACKSIDE CLEANING APPARATUS AND METHOD OF CLEANING WAFER BACKSIDE

BACKGROUND

As consumer devices have gotten smaller and smaller in response to consumer demand, the individual components of these devices have necessarily decreased in size as well. Semiconductor devices, which make up a major component of devices such as mobile phones, computer tablets, and the like, have been pressured to become smaller and smaller, with a corresponding pressure on the individual devices (e.g., transistors, resistors, capacitors, etc.) within the semiconductor devices to also be reduced in size.

As consumer devices decrease, controlling variations in the photoresist exposure operation becomes more important. It is necessary to limit photolithographic exposure focus and overlay errors. Photoresist-coated wafers undergo wafer backside cleaning and polishing prior to selective exposure of the photoresist to actinic radiation in order to reduce focus and overlay errors. However, the wafer backside cleaning and polishing can scratch the wafer backside thereby reducing yield. A wafer backside cleaning and polishing method and wafer backside cleaning and polishing apparatus that reduce or eliminate wafer backside scratching are desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A shows a top view of a wafer cleaning and polishing pad according to an embodiment of the disclosure.

FIG. 1B shows a side view of the wafer cleaning and polishing pad shown in FIG. 1A.

FIG. 2 shows a profile view of a wafer cleaning and polishing pad according to an embodiment of the disclosure.

FIG. 3 shows a process flow for a method of cleaning and polishing a wafer according to an embodiment of the disclosure.

FIG. 4 shows another process flow for a method of cleaning and polishing a wafer according to an embodiment of the disclosure.

FIG. 5 shows another process flow for a method of cleaning and polishing a wafer according to an embodiment of the disclosure.

FIGS. 6A, 6B, 6C, and 6D illustrate the result of backside cleaning and polishing according to embodiments of the disclosure.

FIGS. 7A, 7B, 7C, and 7D illustrate the result of backside cleaning and polishing according to embodiments of the disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “made of” may mean either “comprising” or “consisting of.”

Semiconductor wafers are subject to a wafer backside cleaning and polishing operations after coating the front side of the wafer with a photoresist and prior to selective exposure of the photoresist to improve yield of the exposure operation. Particles remaining on the wafer backside or scratches on the wafer backside can cause focus errors or overlay errors. Cleaning and polishing the wafer backside can reduce focus and overlay errors during the photolithographic exposure operation in a stepper or scanner.

According to various embodiments of the disclosure, a wafer cleaning and polishing pad having a material having a specific range of hardness and coefficients of friction is provided. The material has a higher hardness and a lower coefficient of friction than conventional cleaning and polishing pads. The higher hardness pad as disclosed herein provides improved cleaning and polishing of the wafer surface, while the lower coefficient of friction inhibits scratching of the wafer surface. In some embodiments of the disclosure, backside wafer cleaning and polishing is performed after coating the wafer with photoresist and before selectively exposing the photoresist to actinic radiation. However, the present disclosure is not limited to this operation, and the wafer cleaning and polishing operation can be performed at any suitable time during the semiconductor device manufacturing process.

FIG. 1A shows a top view of a wafer cleaning and polishing pad 10 according to an embodiment of the disclosure. As shown in FIG. 1A, the wafer cleaning and polishing pad 10 includes a polishing surface 15 and a base 20. The polishing surface 15 includes a first material having a high hardness and low static coefficient of friction.

In some embodiments, the polishing surface 15 includes the first material having a Shore D hardness ranging from about 50 to about 80. In some embodiments, the Shore D hardness of the first material of the polishing surface 15 ranges from about 55 to about 75, about 60 to about 70, or about 50 to about 70, inclusive of any hardness values therebetween.

In some embodiments, the polishing surface 15 includes the first material having a static coefficient of friction ranging from about 0.01 to about 0.6. In some embodiments, the static coefficient of friction of the first material of the polishing surface 15 ranges from about 0.01 to about 0.55, about 0.01 to about 0.5, about 0.01 to about 0.45, about 0.01 to about 0.40, about 0.01 to about 0.39, about 0.01 to about 0.35, about 0.01 to about 0.3, about 0.01 to about 0.2, about 0.01 to about 0.1, about 0.05 to about 0.6, about 0.05 to about 0.55, about 0.05 to about 0.5, about 0.05 to about 0.45, about 0.05 to about 0.40, about 0.05 to about 0.39, about 0.05 to about 0.35, about 0.1 to about 0.6, about 0.1 to about 0.55, about 0.1 to about 0.5, about 0.1 to about 0.45, about 0.1 to about 0.40, about 0.1 to about 0.39, about 0.1 to about 0.35, about 0.1 to about 0.3, or about 0.1 to about 0.2, inclusive of any static coefficient of friction values therebetween.

In some embodiments, the first material of the polishing surface 15 includes a fluoropolymer. In some embodiments, the fluoropolymer is selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and/or a mixture thereof.

In some embodiments, the base 20 includes a second material that has a Shore D hardness ranging from about 50 to about 80. In some embodiments, the Shore D hardness of the second material of the base 20 ranges from about 55 to about 75, about 60 to about 70, or about 50 to about 70, inclusive of any hardness values therebetween.

In some embodiments, the second material has a static coefficient of friction higher than about 0.4, about 0.6, about 0.8, about 1.0, about 1.2, about 1.4, or about 1.5. In some embodiments, the second material has a static coefficient of friction ranging from about 0.4 to about 1.5. In an embodiment, the second material includes a material made of a polyvinyl chloride or any suitable plastic material.

In an embodiment, the wafer cleaning and polishing pad 10 has a disk shape as shown in FIG. 1A. In an embodiment, the wafer cleaning and polishing pad 10 includes a plurality of grooves. In some embodiments, the grooves include a varying groove depth from the center of the wafer cleaning and polishing pad 10 to the edge. In some embodiments, the groove depth increases from the center of the wafer cleaning and polishing pad 10 to the edge. In some embodiments, the groove depth decreases from the center of the wafer cleaning and polishing pad 10 to the edge. In some embodiments, the grooves prevent the formation of polishing marks by trapping the polishing particles within the grooves so that during polishing, the contact area of the polishing particles form a line of contact area as opposed to point contact areas. The wafer cleaning and polishing pad 10 can be any suitable shape or form and the shape of the pad 10 shown in FIG. 1A is simply for illustrative purposes, and is therefore non-limiting.

FIG. 1B shows a side view of the wafer cleaning and polishing pad 10 shown in FIG. 1A. As shown in FIG. 1B, the wafer cleaning and polishing pad 10 includes the polishing surface 15 disposed on a middle layer 25 and the base 20. In some embodiments, the base 20 has a larger dimension than either or both of the polishing surface 15 or/and the middle layer 25, and thus surrounds circumferentially either or both the polishing surface 15 or/and the middle layer 25. The geometric arrangement shown in FIG. 1B is for illustrative purposes and thus is non-limiting, and any suitable geometric arrangement can be applied.

In some embodiments, the middle layer 25 includes a third material that has a lower hardness and higher static coefficient of friction compared to the first material of the polishing surface 15. In some embodiments, the third material includes a shock absorbing or buffer material. In some embodiments, the third material is configured to absorb pressure points and redistribute the pressure so as to form a more uniform pressure across surfaces of the middle layer 25 and/or the polishing surface 15. In some embodiments, the third material has a Shore D hardness ranging from about 10 to about 50. In some embodiments, the third material has a Shore D hardness below about 50, about 45, about 40, about 35, about 30, about 25, about 20, or about 15. In some embodiments, the third material has a Shore D hardness that varies from the center to the edge of the middle layer 25. In some embodiments, the varying Shore D hardness value of the middle layer 25 ranges from about 10 to about 50.

In some embodiments, the third material has a static coefficient of friction higher than about 0.4, about 0.6, about 0.8, about 1.0, about 1.2, about 1.4, or about 1.5. In some embodiments, the third material has a static coefficient of friction ranging from about 0.4 to about 1.5. In an embodiment, the third material includes a material made of a polyvinyl alcohol, a polyurethane, or any suitable material.

In some embodiments, the wafer cleaning and polishing pad 10 includes the polishing surface 15, the base 20, and the middle layer 25. In some embodiments, the wafer cleaning and polishing pad 10 includes the polishing surface 15, and the base 20, without the middle layer 25. When redistribution of the pressure is not an issue, the polishing surface 15 is disposed directly over the base 20 in some embodiments. In some embodiments, the wafer cleaning and polishing pad 10 includes the polishing surface 15, and the middle layer 25.

FIG. 2 illustrates a profile view of a wafer cleaning and polishing pad 110 according to an embodiment of the disclosure. As illustrated in FIG. 2, the wafer cleaning and polishing pad 110 includes a polishing surface 115. The radius of the wafer cleaning and polishing pad 110 is shown in FIG. 2 from left to right, starting from the center of the wafer cleaning and polishing pad 110 on the left side to the edge of the wafer cleaning and polishing pad 110 on the right side of the figure. In some embodiments, the polishing surface is not planar relative to the horizontal plane. The polishing surface 115 is shown with a bend, and the distance 130 of the bend from the horizontal plane (in millimeters) increases from the center of the wafer cleaning and polishing pad 110 to an edge of the wafer cleaning and polishing pad 110. The bending distance 130 is configured to counter a bending 135 of the wafer or to apply pressure uniformly across a surface of the wafer while the wafer is being cleaned or polished, so that the bending of the wafer is cancelled to produce a flat, uniformly polished wafer. In some embodiments, the countering of the bending of the wafer occurs by increasing the pressure on the wafer by the wafer cleaning and polishing pad 110 while polishing. In some embodiments, the pressure exerted on the wafer varies from the center of the wafer to the edge of the wafer. As shown in FIG. 2, the bending of the polishing surface 115 ranges from about 1 mm at the center to about 3 mm at the edge so that the pressure exerted properly accommodates the bending to maintain the flatness of the wafer while polishing. As described herein, the pressure gradient (e.g., non-uniform pressure) can be exerted using a shock absorbing or buffer material, such as, for example, the third material of the middle layer 25, to ensure optimal contact between the wafer cleaning and polishing pad 110 and the backside of the wafer from the center to the edge.

In some embodiments, the polishing surface 115 includes a varying thickness across the polishing surface 115 to counter bending of the wafer and/or the wafer cleaning and polishing pad 110 during a cleaning and polishing operation to improve the wafer backside flatness. In such instances, the shock absorbing or buffer material, such as the third material of the middle layer 25 is configured to ensure optimal contact between the wafer cleaning and polishing pad 110 and the backside of the wafer from the center to the edge.

In some embodiments, the wafer cleaning and polishing pad 110 shown in FIG. 2 is identical to the wafer cleaning and polishing pad 10 of FIG. 1A. Accordingly, the components of wafer cleaning and polishing pad 110 are identical to those of wafer cleaning and polishing pad 10.

In some embodiments, the wafer cleaning and polishing pad 110 shown in FIG. 2 is similar to the wafer cleaning and polishing pad 10 of FIG. 1A, but with a gradient in the thickness across the polishing surface. In some embodiments, the thickness of the polishing surface increases from the center to the edge of the wafer cleaning and polishing pad 110 by about 0.1 mm to about 4 mm, about 0.5 mm to about 3.5 mm, about 1 mm to about 3 mm, about 1.2 mm to about 2.8 mm, or about 1.5 mm to about 2.5 mm, inclusive of any range of values therebetween.

FIG. 3 shows a process flow for a method 300 of cleaning and polishing a wafer according to an embodiment of the disclosure. The method 300 includes providing a first wafer surface of the wafer, at operation S302.

In some embodiments of the disclosure, the wafer is a semiconductor wafer or a substrate. In some embodiments, the wafer includes a single crystalline semiconductor layer on at least its surface. In some embodiments, the wafer includes a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the wafer is made of Si. In some embodiments, the wafer is a silicon wafer. In some embodiments, the wafer is a semiconductor-on-insulator substrate fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

At operation S304, the method 300 includes providing a pad having a polishing surface, wherein the polishing surface includes a material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6. In some embodiments, the pad is the wafer cleaning and polishing pad 10 as shown and described with respect to FIG. 1A and/or the wafer cleaning and polishing pad 110 as shown and described with respect to FIG. 2. In some embodiments, the material is the first material as described with respect to FIG. 1A.

In some embodiments, the polishing surface used in the method 300 includes a fluoropolymer selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and a mixture thereof.

In some embodiments, the pad includes at least one of a middle layer or a base. In some embodiments, the pad includes the polishing surface and the middle layer. In some embodiments, the pad includes the polishing surface and the base. In some embodiments, the base includes the second material (as shown and described with respect to FIG. 1A). In some embodiments, the middle layer includes the third material (as shown and described with respect to FIG. 1B) having a lower surface hardness and a higher coefficient of friction than the first material. In some embodiments, the polishing surface includes a plurality of grooves with a varying groove depth from center of the pad to an edge of the pad.

At operation S306, the method 300 includes contacting the first wafer surface with the polishing surface of the pad. In some embodiments, contacting the first wafer surface includes either rotating the wafer or the pad with respect to each other so as to clean or polish the first wafer surface. In some embodiments, the first wafer surface is a backside surface of the wafer wherein a photoresist coating is formed on an opposite surface of the wafer.

At operation S308, the method 300 optionally includes supplying a liquid to the first wafer surface during the contacting, wherein the liquid comprises deionized water, isopropanol, acetone, and mixtures thereof.

At operation S310, the method 300 optionally includes coating a second wafer surface opposing the first wafer surface with a photoresist.

At operation S312, the method 300 optionally includes heating the wafer after coating the second wafer surface with the photoresist.

At operation S314, the method 300 optionally includes selectively exposing the photoresist with actinic radiation to produce a latent pattern in the photoresist.

At operation S316, the method 300 optionally includes heating the wafer after the selectively exposing the photoresist. In some embodiments, the wafer is heated at a temperature ranging from about 40° C. to about 200° C. for about 10 seconds to about 5 minutes.

At operation S318, the method 300 optionally includes developing the photoresist with the latent pattern to produce a patterned photoresist.

In some embodiments, the wafer is coated with a photoresist and then the coated wafer undergoes backside surface cleaning and polishing starting at operation S302. During the cleaning and polishing operation, particles are removed from the wafer by contacting the wafer backside with a pad. The cleaning and polishing operation according to the present disclosure provides a smooth and flat wafer backside without scratches and particle contamination. In some embodiments, the wafer or the pad is rotated during the cleaning and polishing operation. In some embodiments, a liquid is applied to the backside surface of the wafer during the cleaning and polishing operation. In some embodiments, the pressure of the pad contacting the wafer, the rotation speed of the wafer or pad, and the type of liquid is adjusted to optimize the cleaning and polishing operation.

FIG. 4 shows another process flow for a method 400 of cleaning and polishing a wafer according to an embodiment of the disclosure. The method 400 begins with providing a first wafer surface of the wafer, at operation S402.

At operation S404, the method 400 includes providing a pad having a polishing surface, wherein the polishing surface includes a fluoropolymer selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, and polyethylenetetrafluoroethylene. In some embodiments, the wafer is the same as the wafer of the method 300, as described with respect to of FIG. 3. In some embodiments, the wafer is coated with a photoresist and then the coated wafer undergoes backside surface cleaning and polishing starting at operation S402.

In some embodiments, the polishing surface includes a material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6. In some embodiments, the material is the first material as described with respect to FIG. 1A.

In some embodiments, the pad includes at least one of a middle layer or a base. In some embodiments, the pad includes the polishing surface and the middle layer. In some embodiments, the pad includes the polishing surface and the base. In some embodiments, the base includes the second material (as shown and described with respect to FIG. 1A). In some embodiments, the middle layer includes the third material (as shown and described with respect to FIG. 1B) having a lower surface hardness and a higher coefficient of friction than the first material. In some embodiments, the polishing surface includes a plurality of grooves with varying groove depth from center of the pad to an edge of the pad.

At operation S406, the method 400 includes contacting the first wafer surface with the polishing surface of the pad. In some embodiments, contacting the first wafer surface includes either rotating the wafer or the pad with respect to each other so as to clean or polish the first wafer surface. In some embodiments, the first wafer surface is a backside surface of the wafer wherein a photoresist coating is formed on an opposite surface of the wafer.

At operation S408, the method 400 optionally includes supplying a liquid to the first wafer surface during the contacting, wherein the liquid comprises deionized water, isopropanol, acetone, and mixtures thereof.

At operation S410, the method 400 optionally includes coating a second wafer surface opposing the first wafer surface with a photoresist.

At operation S412, the method 400 optionally includes heating the wafer after coating the second wafer surface with the photoresist.

At operation S414, the method 400 optionally includes selectively exposing the photoresist with actinic radiation to produce a latent pattern in the photoresist.

At operation S416, the method 400 optionally includes heating the wafer after the selectively exposing the photoresist. In some embodiments, the wafer is heated at a temperature ranging from about 40° C. to about 200° C. for about 10 seconds to about 5 minutes.

At operation S418, the method 400 optionally includes developing the photoresist with the latent pattern to produce a patterned photoresist.

During the cleaning and polishing operation, particles are removed from the wafer by contacting the wafer backside with a pad. The cleaning and polishing operation according to the method 400 provides a smooth and flat wafer backside without scratches and particle contamination.

FIG. 5 shows another process flow for a method 500 of cleaning and polishing a wafer according to an embodiment of the disclosure. The method 500 includes providing a first wafer surface of the wafer, at operation S502.

In some embodiments, the wafer is the same as the wafer of the method 300, as described with respect to of FIG. 3. In some embodiments, the wafer is coated with a photoresist and then the coated wafer undergoes backside surface cleaning and polishing starting at operation S502.

In some embodiments, the pad is the same as the wafer cleaning and polishing pad 10 as shown and described with respect to FIG. 1A and/or the wafer cleaning and polishing pad 110 as shown and described with respect to FIG. 2. In some embodiments, the polishing surface includes a material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6. In some embodiments, the material is the first material as described with respect to FIG. 1A.

In some embodiments, the polishing surface includes a fluoropolymer selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, and polyethylenetetrafluoroethylene.

At operation S504, the method 500 includes providing a pad having a polishing surface, wherein the pad includes a middle layer and a base. In some embodiments, the base includes the second material (as shown and described with respect to FIG. 1A). In some embodiments, the base includes the third material (as shown and described with respect to FIG. 1B) having a lower surface hardness and a higher coefficient of friction than the first material. In some embodiments, the polishing surface includes a plurality of grooves with varying groove depth from center of the pad to an edge of the pad.

At operation S506, the method 500 includes contacting the first wafer surface with the polishing surface of the pad. In some embodiments, contacting the first wafer surface includes either rotating the wafer or the pad with respect to each other so as to clean or polish the first wafer surface. In some embodiments, the first wafer surface is a backside surface of the wafer wherein a photoresist coating is formed on an opposite surface of the wafer.

At operation S508, the method 500 optionally includes supplying a liquid to the first wafer surface during the contacting, wherein the liquid includes deionized water, isopropanol, acetone, and mixtures thereof.

At operation S510, the method 500 optionally includes coating a second wafer surface opposing the first wafer surface with a photoresist.

At operation S512, the method 500 optionally includes heating the wafer after coating the second wafer surface with the photoresist.

At operation S514, the method 500 optionally includes selectively exposing the photoresist with actinic radiation to produce a latent pattern in the photoresist.

At operation S516, the method 500 optionally includes heating the wafer after the selectively exposing the photoresist. In some embodiments, the wafer is heated at a temperature ranging from about 40° C. to about 200° C. for about 10 seconds to about 5 minutes.

At operation S518, the method 500 optionally includes developing the photoresist with the latent pattern to produce a patterned photoresist.

During the cleaning and polishing operation, particles are removed from the wafer by contacting the wafer backside with a pad. The cleaning and polishing operation according to the method 500 provides a smooth and flat wafer backside without scratches and particle contamination.

FIGS. 6A, 6B, 6C, and 6D illustrate the result of wafer cleaning and polishing according to embodiments of the disclosure. FIG. 6A illustrates a wafer having a plurality of particles or defects 650a disposed near the center of the wafer, e.g. the “dirty wafer”. FIG. 6B shows a surface profile of the dirty wafer as a function of the radius R of the wafer shown in FIG. 6A. As illustrated in the surface profile, a plurality of peaks 650b can be identified between radius marks 15 and 60 in the surface profile of the wafer signifying the presence of plurality of particles or defects 650a.

FIG. 6C illustrates the wafer as shown in FIG. 6A that has undergone the wafer cleaning and polishing process as disclosed herein using the cleaning and polishing apparatus as disclosed herein. FIG. 6D shows a surface profile of the wafer that has been cleaned, e.g. the “clean wafer”. As illustrated in FIG. 6D, the surface profile of the clean wafer no longer shows the plurality of peaks 650b that were present in FIG. 6B. After the cleaning and polishing operation, the plurality of particles or defects 650a are removed from the wafer the cleaning and polishing operation according to the methods disclosed herein, which results in a smooth and flat wafer backside without scratches and particle contamination. In particular, the wafer cleaning and polishing method and cleaning and polishing devices of the present disclosure provide an improvement in backside particle removal and flatness over 90% compared to conventional wafer cleaning and polishing. By comparing the surface profile of the dirty wafer of FIG. 6B and that of the cleaned wafer in FIG. 6D, the difference in the surface roughness exhibits an unexpected improvement of over 90% in terms of surface profile measurements. For example, the peak height of the wafer due to the plurality of particles or defects 650a decreases from 445 nm to 26 nm at the radius R value 33.

FIGS. 7A, 7B, 7C, and 7D illustrate the result of wafer cleaning and polishing according to embodiments of the disclosure. FIG. 7A illustrates a wafer having a plurality of particles or defects 750a disposed near the center of the wafer, e.g. the “dirty wafer”. FIG. 7B shows a surface profile of the dirty wafer as a function of the radius R of the wafer shown in FIG. 7A. As illustrated in the surface profile, a plurality of peaks 750b can be identified between radius values 15 and 70 in the surface profile of the wafer signifying the presence of plurality of particles or defects 750a.

FIG. 7C illustrates the wafer as shown in FIG. 7A that has undergone the wafer cleaning and polishing process as disclosed herein using the cleaning and polishing apparatus as disclosed herein. FIG. 7D shows a surface profile of the wafer that has been cleaned, e.g. the “clean wafer”. As illustrated in FIG. 7D, the surface profile of the clean wafer no longer shows the plurality of peaks 750b that were present in FIG. 7B. After the cleaning and polishing operation according to embodiments of the disclosure, the plurality of particles or defects 750a are removed from the wafer, which results in a smooth and flat wafer backside without scratches and particle contamination. In particular, the wafer cleaning and polishing method and cleaning and polishing devices of the present disclosure provide an improvement in backside particle removal and flatness over 90% compared to conventional wafer cleaning and polishing. By comparing the surface profile of the dirty wafer of FIG. 7B and that of the cleaned wafer in FIG. 7D, the difference in the surface roughness exhibits an unexpected improvement of over 90% in the surface profile measurements. For example, the peak height of the wafer due to the plurality of particles or defects 750a decreases from 800 nm to 61 nm at the radius R value 145.

It is understood that the semiconductor devices formed according to the disclosed methods undergo further processes, including material deposition, implantation, or etching operations, to form various features such as field effect transistors, cap insulating layers, contacts/vias, silicide layers, interconnect metal layers, dielectric layers, passivation layers, metallization layers with signal lines, etc. In some embodiments, one or more layers of conductive, semiconductive, and insulating materials are formed over the substrate, and a pattern is formed in one or more of the layers.

A wafer backside cleaning and polishing apparatus and the methods of operating the apparatus as described herein allow for reduction or elimination of wafer backside scratching. According to various embodiments of the disclosure, the disclosed apparatus and methods provide an expected improvement in the reduction of photolithographic exposure focus and overlay errors, and provide an unexpected improvement in the yield in the production of high quality devices.

An embodiment of the disclosure is a wafer cleaning and polishing pad. The wafer cleaning and polishing pad includes a pad having a polishing surface, wherein the polishing surface includes a first material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6. In an embodiment, the first material is a fluoropolymer. In an embodiment, the fluoropolymer is selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and a mixture thereof. In an embodiment, the wafer cleaning and polishing pad includes at least one of a middle layer or a base. In an embodiment, the base includes a second material. In an embodiment, the middle layer includes a third material having a lower surface hardness and a higher coefficient of friction than the first material. In an embodiment, the second material or the third material has a static coefficient of friction ranging from 0.4 to 1.5. In an embodiment, the second material is a polyvinyl chloride and the third material is a polyvinyl alcohol or a polyurethane. In an embodiment, a bending of the polishing surface increases from center of the pad to an edge of the pad or the pad is configured to uniformly apply pressure across a surface of a wafer during cleaning and polishing. In an embodiment, the bending of the polishing surface increases from 1 mm to 3 mm from the center of the pad to the edge of the pad to accommodate the applied pressure.

Another embodiment of the disclosure is a wafer cleaning and polishing chamber. The chamber includes a cleaning and polishing solution supply, a wafer support, a motor configured to spin the wafer support, a polishing arm, and a wafer cleaning and polishing pad fixed to the polishing arm. The wafer cleaning and polishing pad includes a pad having a polishing surface, and wherein the polishing surface includes a first material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6. In an embodiment, the polishing surface comprises a fluoropolymer selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and a mixture thereof. In an embodiment, the pad further includes at least one of a middle layer or a base. In an embodiment, the base includes a second material. In an embodiment, the middle layer includes a third material having a lower surface hardness and a higher coefficient of friction than the first material. The second material is a polyvinyl chloride or the third material is a polyvinyl alcohol or a polyurethane. In an embodiment, the second material or the third material has a static coefficient of friction ranging from 0.4 to 1.5. In an embodiment, a bending of the polishing surface increases from 1 mm to 3 mm from center of the pad to an edge of the pad or the pad is configured to uniformly apply pressure across a surface of a wafer during cleaning and polishing.

Another embodiment of the disclosure is a method of cleaning and polishing a wafer. The method includes providing a first wafer surface, providing a pad having a polishing surface, wherein the polishing surface includes a material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6, and contacting the first wafer surface with the polishing surface of the pad. In an embodiment of the method, contacting the first wafer surface includes either rotating the wafer or the pad with respect to each other so as to clean or polish the first wafer surface. In an embodiment, the first wafer surface is a backside surface of the wafer having a photoresist coating on an opposite surface of the wafer. In an embodiment, the method includes supplying a liquid to the first wafer surface during the contacting, wherein the liquid comprises deionized water, isopropanol, acetone, and mixtures thereof. In an embodiment, the method also includes coating a second wafer surface opposing the first wafer surface with a photoresist. In an embodiment, the method includes heating the wafer after coating the second wafer surface with the photoresist. In an embodiment, the method includes selectively exposing the photoresist with actinic radiation to produce a latent pattern in the photoresist. In an embodiment, the method includes heating the wafer after the selectively exposing the photoresist. In an embodiment, the method further includes developing the photoresist with the latent pattern to produce a patterned photoresist. In an embodiment of the method, the polishing surface includes a fluoropolymer selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and a mixture thereof. In an embodiment, the pad includes at least one of a middle layer or a base. The base includes a second material. The middle layer includes a third material having a lower surface hardness and a higher coefficient of friction than the first material. In an embodiment, wherein the second material is a polyvinyl chloride and the third material is a polyvinyl alcohol or a polyurethane.

Another embodiment of the disclosure is a semiconductor device processing apparatus. The apparatus includes a cleaning and polishing chamber and a processing chamber downstream from the cleaning and polishing chamber. The cleaning and processing chamber includes a cleaning and polishing solution supply, a wafer support, a motor configured to spin the wafer support, a polishing arm, and a wafer cleaning and polishing pad fixed to the polishing arm. The wafer cleaning and polishing pad includes a pad having a polishing surface, and wherein the polishing surface includes a material having a Shore D hardness ranging from 50 to 80, and a coefficient of static friction ranging from 0.01 to 0.6. In an embodiment, the processing chamber includes a wafer stepper or a wafer scanner. In an embodiment, the apparatus further includes a photoresist coating chamber upstream from the cleaning and polishing chamber. In an embodiment, the polishing surface has a static coefficient of friction ranging from 0.05 to 0.4. In an embodiment, the polishing surface has a static coefficient of friction less than or equal to 0.1. In an embodiment, the polishing surface is made of a fluoropolymer. In an embodiment, the fluoropolymer is selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and a mixture thereof. In an embodiment, the pad includes an base. In an embodiment, the base includes a material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.4 to 1.5. In an embodiment, the base comprises a polyvinyl chloride. In an embodiment, the pad includes a middle layer, wherein the middle layer is formed of a material having a lower surface hardness and a higher coefficient of friction than the polishing surface. In an embodiment, the middle layer includes a material having a Shore D hardness ranging from 15 to 50 and a static coefficient of friction ranging from 0.4 to 1.5. In an embodiment, the middle layer includes a polyvinyl alcohol or a polyurethane. In an embodiment, a bending of the polishing surface increases from center of the pad to an edge of the pad. In an embodiment, the pad is configured to uniformly apply pressure across a surface of a wafer during cleaning and polishing. In an embodiment, the bending of the polishing surface increases from 1 mm to 3 mm from the center of the pad to the edge of the pad to accommodate the applied pressure. In an embodiment, the third material of the middle layer reduces in thickness to accommodate the bending of the polishing surface.

Another embodiment of the disclosure is a method of cleaning and polishing a wafer. The method includes providing a first wafer surface, providing a pad having a polishing surface, wherein the polishing surface includes a fluoropolymer selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and a mixture thereof. In an embodiment, the pad includes at least one of a middle layer or a base. The base includes a second material that is different from the first material. The middle layer includes a third material having a lower surface hardness and a higher coefficient of friction than the first material. The method also includes contacting the first wafer surface with the polishing surface of the pad. In an embodiment of the method, contacting the first wafer surface includes rotating the wafer or the pad with respect to each other so as to clean or polish the first wafer surface. In an embodiment, the first wafer surface is a backside surface of the wafer having a photoresist coating on an opposite surface of the wafer. In an embodiment, the method includes supplying a liquid to the first wafer surface during the contacting, wherein the liquid comprises deionized water, isopropanol, acetone, and mixtures thereof. In an embodiment, the method also includes coating a second wafer surface opposing the first wafer surface with a photoresist. In an embodiment, the method includes heating the wafer after coating the second wafer surface with the photoresist. In an embodiment, the method includes selectively exposing the photoresist with actinic radiation to produce a latent pattern in the photoresist. In an embodiment, the method includes heating the wafer after the selectively exposing the photoresist. In an embodiment, the method further includes developing the photoresist with the latent pattern to produce a patterned photoresist. In an embodiment of the method, the polishing surface includes a material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6. In an embodiment, a thickness of the polishing surface increases from center of the pad to an edge of the pad.

Another embodiment of the disclosure is a method of cleaning and polishing a wafer. The method includes providing a first wafer surface, providing a pad having a polishing surface, wherein the pad includes at least one of a middle layer or a base, wherein the base includes a second material that is different from the first material, and the middle layer includes a third material having a lower surface hardness and a higher coefficient of friction than the first material, and contacting the first wafer surface with the polishing surface of the pad. In an embodiment of the method, contacting the first wafer surface includes either rotating the wafer or the pad with respect to each other so as to clean or polish the first wafer surface. In an embodiment, the first wafer surface is a backside surface of the wafer having a photoresist coating on an opposite surface of the wafer. In an embodiment, the method includes supplying a liquid to the first wafer surface during the contacting, wherein the liquid comprises deionized water, isopropanol, acetone, and mixtures thereof. In an embodiment, the method also includes coating a second wafer surface opposing the first wafer surface with a photoresist. In an embodiment, the method includes heating the wafer after coating the second wafer surface with the photoresist. In an embodiment, the method includes selectively exposing the photoresist with actinic radiation to produce a latent pattern in the photoresist. In an embodiment, the method includes heating the wafer after the selectively exposing the photoresist. In an embodiment, the method further includes developing the photoresist with the latent pattern to produce a patterned photoresist. In an embodiment, the polishing surface includes a material having a Shore D hardness ranging from 50 to 80 and a static coefficient of friction ranging from 0.01 to 0.6. In an embodiment of the method, the polishing surface includes a fluoropolymer selected from the group consisting of a polyvinylfluoride, polyvinylidene fluoride, polyethylenedifluoride, polytetrafluoroethylene, perfluoroalkoxy polymer, fluorinated ethylene-propylene copolymer, polyethylenetetrafluoroethylene, polyethylenechlorotrifluoroethylene, and a mixture thereof. In an embodiment, a thickness of the polishing surface increases from center of the pad to an edge of the pad.

The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

WAFER BACKSIDE CLEANING APPARATUS AND METHOD OF CLEANING WAFER BACKSIDE

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