Wafer support of semiconductor manufacturing apparatus

Information

  • Patent Grant
  • D1078667
  • Patent Number
    D1,078,667
  • Date Filed
    Wednesday, February 22, 2023
    2 years ago
  • Date Issued
    Tuesday, June 10, 2025
    4 months ago
  • Inventors
    • Jinden; Tatsuki
    • Morita; Shinya
  • Original Assignees
  • Examiners
    • Oswecki; Elizabeth J
    Agents
    • FITCH, EVEN, TABIN & FLANNERY, LLP
  • US Classifications
    Field of Search
    • US
    • D13 182
    • D15 144
    • D15 1441
    • D15 199
    • 118 715000
    • 118 500000
    • 118 728000
    • 118 729000
    • 211 041180
    • 432 253000
    • 432 258000
    • 156 345510
    • 156 345520
    • 156 345530
    • 156 345550
    • 414 217000
    • 414 220010
    • 414 935-941
    • CPC
    • C23C16/458
    • C23C16/4581
    • C23C16/4582
    • C23C16/4583
    • C23C16/4584
    • C23C16/4587
    • C23C16/4588
    • C30B3/14
    • H01L21/673
    • H01L21/67303
    • H01L21/67306
    • H01L21/67309
    • H01L21/67313
    • H01L21/67316
    • H01L21/67323
    • H01L21/67326
    • H01L21/6733
  • International Classifications
    • 1303
    • Term of Grant
      15Years
Abstract
Description


FIG. 1 is a front, top and right side perspective view of a wafer support of semiconductor manufacturing apparatus-showing our new design;



FIG. 2 is a front elevational view thereof;



FIG. 3 is a left side elevational view thereof;



FIG. 4 is a right side elevational view thereof;



FIG. 5 is a top plan view thereof;



FIG. 6 is a bottom plan view thereof.



FIG. 7 is a rear elevational view thereof;



FIG. 8 is a cross-sectional view taken along line 8-8 in FIG. 2;



FIG. 9 is a cross-sectional view taken along line 9-9 in FIG. 2;



FIG. 10 is an enlarged portion view taken from encircled portion labeled, “FIG. 10,” in FIG. 2;



FIG. 11 is a perspective view of FIG. 8, shown without broken line environment, for ease of illustration;



FIG. 12 is a front elevational view of FIG. 11;



FIG. 13 is a left side elevational view of FIG. 11;



FIG. 14 is a right side elevational view of FIG. 11;



FIG. 15 is a top plan view of FIG. 11;



FIG. 16 is a bottom plan view of FIG. 11; and,



FIG. 17 is a rear elevational view of FIG. 11.


The even dashed broken lines in the drawings are for the purpose of illustrating portions of the article that form no part of the claimed design.


The dot, dot dashed broken lines in the drawings are for the purpose of illustrating the boundaries of the enlarged portion view of FIG. 10 in FIGS. 2 and 10 and form no part of the claimed design.


The single dot dashed lines in the drawings represent the boundary between the part for which the design is claimed and the part not claimed.


Claims
  • The ornamental design for a wafer support of semiconductor manufacturing apparatus, as shown and described.
Priority Claims (1)
Number Date Country Kind
2022-019755 D Sep 2022 JP national
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Number Date Country
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Non-Patent Literature Citations (2)
Entry
Vertical Column Wafer Boat & Pedestal,https://www.veteksemi.com/vertical-column-wafer-boat-pedestal.html, Copyright © 2024. (Year: 2024).
Customized Silicon Carbide (SIC) Boat for Wafer Handling,https://www.msesupplies.com/products/customized-silicon-carbide-sic-boat, © 2024. (Year: 2024).