Patent Application
20090057837
Not applicable.
This present subject matter relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for determining wafer identity using edge notches encoding a wafer identification descriptor.
During the manufacture of semiconductor devices, semiconductor wafers, each including a plurality of individual die, are subjected to a number of processing steps. Typically, wafers are grouped into lots that are processed together. Each lot may contain, for example, 25 individual wafers. As a lot of wafers progresses through the processing line, the wafers are typically housed in a carrier.
One issue associated with the wafer identification code 30 is that it tends to become harder to read as the wafer 10 progresses through the manufacturing process. Wafers 10 are subjected to a wide variety of processes, such as chemical and physical etching, polishing, annealing, that have a tendency to degrade the wafer identification code 30. The wafer processing tends to cause a darkening of the wafer surface, resulting in poor optical contrast between the wafer scribe and the wafer surface. In some cases the degradation in the wafer identification code 30 is sufficiently severe that it can no longer be read. One technique for countering the degradation is the use of self correcting coding techniques, such as two dimensional bar coding, that encode redundant information in horizontal and vertical patterns. If a portion of the pattern is obscured, the missing information may sometimes be recreated from the redundant information. Even with such information redundancy, some wafer identification codes 30 may still degrade to the point where they are unreadable.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
The following presents a simplified summary of the disclosed subject matter in order to provide a basic understanding of some aspects of the disclosed subject matter. This summary is not an exhaustive overview of the disclosed subject matter. It is not intended to identify key or critical elements of the disclosed subject matter or to delineate the scope of the disclosed subject matter. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
One aspect of the disclosed subject matter is seen in an apparatus including a semiconductor wafer having a surface terminating in an edge. A plurality of notches is defined along the edge. The plurality of notches encodes a wafer identification descriptor for the wafer.
Another aspect of the disclosed subject matter is seen a system for identifying wafers. Each wafer includes a surface terminating in an edge and a plurality of notches defined along the edge. The system includes a scanner adapted to scan at least a portion of a wafer including the plurality of notches and decode the scan of the plurality of notches to generate a wafer identification descriptor for the wafer.
The disclosed subject matter will hereafter be described with reference to the accompanying drawings, wherein like reference numerals denote like elements, and:
While the disclosed subject matter is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the disclosed subject matter to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosed subject matter as defined by the appended claims.
One or more specific embodiments of the disclosed subject matter will be described below. It is specifically intended that the disclosed subject matter not be limited to the embodiments and illustrations contained herein, but include modified forms of those embodiments including portions of the embodiments and combinations of elements of different embodiments as come within the scope of the following claims. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. Nothing in this application is considered critical or essential to the disclosed subject matter unless explicitly indicated as being “critical” or “essential.”
The disclosed subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the disclosed subject matter with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the disclosed subject matter. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Referring now to the drawings wherein like reference numbers correspond to similar components throughout the several views and, specifically, referring to
The particular notch structure used to define the wafer identification descriptors 220 may vary depending on the particular embodiment. Generally, by varying the width of the identification notches 230 and/or the spacing between the identification notches 230, a code may be defined.
Turning to
It is also contemplated that the wafer 200, 300 be provided without an orientation notch 210 or flat 310. The identification notches 230 may be provided with defined start and stop patterns (e.g., defined by the outermost notches 230) that may be used to align the wafer 200 and read the wafer identification descriptor 220 in a single action, thereby reducing cycle time.
Various pieces of equipment in a fabrication facility may be equipped with hardware for reading the wafer identification descriptors 320. This equipment may include wafer sorters, process tools, metrology tools, transport devices, etc.
In some instances, a wafer 200, 300 that has been misprocessed may be reclaimed. Because the reclaimed wafer 200, 300 is subjected to a different process flow than the original wafer the first time it was processed, it is assigned a new identity.
Using edge notches 230, 330 to define wafer identification descriptors 220, 320 as described herein, has numerous advantages. The edge notches 230, 330 are less susceptible to processing related damage that renders other types of identification codes unreadable. Discoloration of the wafer surface does not tend to degrade the wafer identification descriptors 220, 320. The algorithm required to read and decode the identification notches 220, 320 is considerably less complex than the optical techniques employed to read conventional surface scribed identification codes. This reduction in complexity allows scanners to be provided in a wider variety of applications without introducing the configuration control issues present with conventional scanning algorithms, which are frequently modified to attempt to better read the distorted codes.
The particular embodiments disclosed above are illustrative only, as the disclosed subject matter may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the disclosed subject matter. Accordingly, the protection sought herein is as set forth in the claims below.
