Patent Application
20070097825
The present invention relates to readout systems utilized in data storage devices. More specifically, the present invention provides high speed readout for an optical disk drive system which does not require the use of read signal phase locked loops.
Data storage systems are an integral part of today's society, storing massive amounts of information related to many different topics. Generally speaking, these data storage systems all include a storage media of some type, and related electronics to coordinate the storage and retrieval of information. Various types of storage media exist, which can be separated into two primary categories—magnetic and optical. Further, storage systems often include both removable and permanent media, each having particular advantages and disadvantages.
As known by those skilled in the art, several different components of the data storage system are required in order to coordinate the reading and writing of information. As an example, various synchronization systems are required to synchronize the flow of data with the movement of media and related components. Specifically, the rotation rate of the storage media must first be controlled and synchronized with other systems in the data storage device. Further, all systems must coordinate a consistent data format (i.e., physical layout) so that meaningful information is reproduced. Additionally, in optical storage devices the laser systems and related readout systems must also be carefully coordinated. Data storage systems also often include error correcting capability, which obviously requires additional coordination.
In addition to all the above-referenced operational concerns, data storage systems, generally speaking, are continuing to grow in size, speed and capacity. This is simply consistent with the demands for data storage capabilities and data processing capabilities. Today's storage systems are measured in gigabytes and are growing continually larger. Naturally, with capacities on this order, several operating characteristics are changing. For example, with data capacities at increased levels, the storage density of particular media is required to increase. With optical drives, increased density requires smaller spot and mark sizes, which thus requires increased precision in all related systems. Further, to deal with this increased capacity, comes increased demand for speed. Many factors effect overall speed, but a high rate of data through-put is required so that large amounts of data can be moved into and out of the data storage system.
Naturally, the readout systems which retrieve data from the media, along with all internal operating systems, must operate at faster speeds and higher capacities to meet the demands of related systems. Again, with these speed concerns in mind, a high rate of data through-put is particularly dependent upon the operation of the readout. More specifically, the readout system must be able to transfer data at sufficient rates to meet the desired data through-put rate.
Traditionally, readout systems within a storage system incorporate some kind of sampling loop including a PLL (phase locked loop). However, the delays incorporated in the PLL can detrimentally affect the bandwidth or stability of the readout system. That is, delays of traditional phase lock loops have limited the bandwidth, thus limiting the overall through-put from the data storage system. In addition, these systems typically require additional data overhead (longer VFO field) to allow for the PLL to become locked. Thus, it is desirable to minimize or eliminate the delays, in order to provide the desired bandwidth. Additionally, phase errors are often created by phase lock loops which also must be dealt with. Optical effects also have many detrimental results which can distort the signals causing detrimental effects to the system. Typical corrective efforts to deal with these optical effects (e.g., equalizers and related conditioning circuitry) can also create delays in the PLL based readout system. Again, for all these reasons, it is desirable to minimize delays in systems using phase locked loops.
In addition to the specific issues related to phase locked loops mentioned above, it is generally very desirable to create a read channel design which has a high bandwidth. Such design would generate a high through-put/data rate and provide the necessary speed for operation. Further, it would be beneficial to eliminate or avoid the above-referenced short comings in existing readout systems.
The present invention provides a readout system which creates a synchronous read signal from quasi-synchronous sample data. By utilizing this methodology, PLLs can effectively be eliminated from the readout system, thus eliminating the problems associated with increasing signal processing delays and helping to increase the bandwidth.
Generally speaking, the readout system of the present invention reconstructs the waveform to provide a sample that is equivalent to one which would have been sampled at precisely the right time. This avoids delays in timing issues inherent in existing readout systems, and again increases bandwidth. Further, the system of the present invention allows for the use of additional systems that provide conditioning and/or corrections desired. For example, the present invention can utilize an equalizer and other signal conditioning components to provide additional accuracy. This use of an equalizer provides compensation for many different things, such as defocus, disk tilts, cover layer deficiencies, and other undesirable optical effects.
As part of the waveform reconstruction, an accurate determination of the phase errors is required for effective operation. Following the determination of the phase errors, appropriate adjustments can then be made to achieve the reconstructed sample. More specifically, mathematical processing is used to determine appropriate signal sample values. Lastly, based upon the phase error and mathematical processing, the system is capable of skipping samples or inserting samples to appropriately adjust for bit slip (as described below, a condition where the magnitude of the phase error becomes to large to allow for simple adjustments to be made).
Generally speaking, the readout system includes an A-D converter which receives the readout signal and provides a converted digital signal to a digital equalizer. The digital equalizer is used for signal conditioning and other well known functions. Connected to the output of the digital equalizer is a specialized phase detector, which is utilized for analyzing the conditioned signal and determining the phase error value. The system then includes a waveform reconstructor component, which is utilized to reconstruct the readout signals. The waveform reconstructor and the specialized phase detector cooperate with a number of FIFO registers to accommodate bit slip of the quasi-synchronous data. Lastly, a read offset control is utilized to center the waveform before the channel bit decoder processes it. The read offset control is the only feedback loop utilized in the system.
In operation, the ADC receives the readout signal and converts it to a digital signal in a typical manner. As also typical with many readout systems, the ADC is synchronized with a signal from the media. In preferred embodiments, this signal is a wobble clock signal that is derived from a wobble structure on the media itself.
The output from the ADC is fed to a digital equalizer to provide magnitude and phase adjustments for optimal data decoding. Generally speaking, the equalizing functions are well known by those skilled in the art, and provide several advantages for optical read systems. The various coefficients for use by the equalizer are provided by feedback coming from the readout sections.
The output from the equalizer is provided to a specialized phase detector which calculates a phase error based on an anticipated signal characteristic. In addition, the specialized phase detector also calculates an estimated phase error at each midpoint, which is one half of the system channel bit. In order to achieve both calculations (phase error and midpoint phase error), first and second derivatives are utilized in the analysis to provide further accuracy. The use of these more comprehensive signal processing components allows for a more accurate phase error measurement and subsequent recreation of the waveform.
Within the specialized phase detector, the phase error calculations and read signal sampling are both utilized to set up a phase window centered at a zero point and extending one half sample period in both the positive and negative directions. Thus, the phase window of +/−0.5 T allows for two samples within the window (i.e., the actual read sample and a computed midpoint sample). By further analyzing these two samples, determination is then made as to which sample is closer zero. The “better” of these phase error calculations is then selected and output as the utilized phase error. Stated alternatively, this analysis allows for a determination of the most desirable sample of these two calculated phase error values. Thus, the read sample phase error or midpoint phase error, whichever is closest to zero, can then be utilized for further operations. This selected phase error is then output to the waveform reconstructor and to a register pointer/control device, which coordinates corrections to accommodate bit slip.
As mentioned above, the present invention reconstructs the waveform as if it had been sampled at precisely the right time. In doing so, the system recognizes that phase errors will create issues that must be accounted for. If the phase errors get too large, bit slip can occur wherein the reconstructed sample is determined to be at a position where either the next sample or the previous sample should be utilized. In order to accommodate this, the present invention includes a register pointer/control mechanism, along with a number of FIFO registers to manage and account for any bit slips. More specifically, the register pointer and control maintains a pointer to signal that sample insertions or deletions should be made. Generally speaking, this controls the timing aspect of the reconstruction activities. While the phase errors are within controlled levels, the pointer stays at a constant level and no adjustments are made. However, when the phase error gets sufficiently large in magnitude (either positive or negative slips), a shift is effectively instituted, causing either a sample deletion or sample insertion.
As mentioned, the present invention further includes a waveform reconstructor which receives both readout samples from the equalizer, and phase error signals from the specialized phase detector. The waveform reconstructor then calculates a reconstructed sample value based on these inputs. By accomplishing this reconstruction in this way, the waveform reconstructor can adjust for phase errors in its calculation. Additionally, the waveform reconstructor calculates an insert sample. This insert sample is of a value that would be appropriate if insertion is required. Both the reconstructed sample and the insertion sample are provided to a reconstruction register and an insert register respectively. These registers also receive control signals from the register pointer/control system of the present invention. Additional registers included in the system are utilized to track synchronization of equalizer and insert operations. All of these registers are identical and controlled by the same register pointer and control system.
At an output stage of the present invention, a multiplexer is utilized to receive both the reconstructed and the insert sample. Based upon a control signal from the register pointer/control mechanism, either the appropriate reconstructed sample or insert sample is output to a channel bit decoder. The output is also provided to a read offset control for use in monitoring read offsets. Naturally, the channel bit decoder provides an output to subsequent systems which provides for effective decoding of the marks and spaces saved on the disk.
As mentioned above, the read offset control also receives the reconstructed waveform samples from the multiplexer. The read offset control calculates offset errors and outputs appropriate adjustment signals, as is well know by those skilled in the art.
Lastly, a target pattern generator is utilized to provide a final check on the system operation. The target pattern generator receives the channel bit decoder output, and feeds back a signal which is combined with a delayed version of the reconstructed waveform to produce an error signal for the adaptive equalizer. The adaptive equalizer error signal controls the adjustment of the equalizer coefficient values.
As evident from the discussion above, the present invention is configured and designed to specifically provide a read channel with high bandwidth capable of accommodating data rates required by today's systems. Further, the system is set up and specifically designed to provide a synchronous read signal from a quasi-synchronous data sample. This feature allows for the elimination of a classic phase lock loop, thus avoiding the undesirable characteristics of those systems.
Further objects and advantages of the present invention can be seen from the following detailed description, in conjunction with the drawings, in which:
The present invention relates to a readout system used within a data storage device. While the data storage device can take many forms, one exemplary system is shown in
Laser assembly 36 is also connected to a read/write channel 26 for transferring the appropriate signals to and from the media 12. Similarly, read/write channel 26 is attached to controller 20 which coordinates the overall operation of storage device 10. Laser assembly 36 includes a typical split detector (not shown) used for tracking on media 12. As further outlined below, this split detector provides signals indicative of the structures present on the surface of media 12, including addressing information signals, data signals, and synchronization signals.
As illustrated in
Referring now to
In optical disk recording, a quasi-synchronous sampling is typically generated using a wobble PLL (not shown) that is locked to a wobbled groove that is mastered on the disk. The wobble PLL generates wobble clock signal 48 which is a higher multiple of the frequency of the wobbled groove. Wobble clock signal 48 is frequency locked to the channel bit rate of the recorded data, and is used as the time base for sampling analog read signal 46. Analog read signal 46 is converted to a digital sample value using ADC 44. In this embodiment, ADC output 50 (read_adc[0]) is assumed to be a signed 8-bit value with the zero level at the center of the analog input range. ADC output 50 is a quasi-synchronous signal as a result of its being frequency locked to wobble clock signal 48.
The ADC output 50 is then provided to an adaptive digital equalizer 52 to produce an equalized read signal 54 (read_eq). Digital equalizer 52 is a multi-tap transversal FIR filter (21-tap for the example) employing Sign-Data Least Mean Squares (LMS) coefficient adaptation. Adaptive Digital Equalizer 52 is implemented using inputs from ADC Plus 60, the Target Pattern Generator 290 and Adaptive Coefficients Components 62, as shown in
Referring now to
Referring again to
A specialized phase detector 80 receives the offset controlled read signal 70, and generally speaking, is utilized to determine the phase difference between the quasi-synchronous samples, and an ideally sampled data point. This phase error is calculated and normalized to range of −0.5 T to +0.5 T, where T is the channel bit period of the sampled read signal 46.
Referring to
Specialized phase detector 80 begins its processing by generating several signals that are all derived from offset controlled read signal 70 (read_d0). More specifically, these signals are:
A midpoint signal 158 (mid_d0) is also computed from the offset controlled read signal 70 (read_d0), along with related first derivative 160 (mid_d1) and second derivative 162 (mid_d2). These signals are calculated as follows:
In order to achieve efficient operation, several practical considerations are made by waveform reconstructor 40. For example, “smaller” marks and spaces are not used. The resolution of 2 T and 3 T marks and spaces is very low. Due to the extremely high linear density of the recorded data with respect to the readout spot size, Therefore, specialized phase detector 80 of the present embodiment determines the phase error using only 4 T and longer marks and spaces. With this in mind, several measures are taken to ensure that there are not extended sequences of 2 T and 3 T marks and spaces:
Referring again to
In both paths, the read signal first derivative signal 154 (read_d1) or midpoint first derivative signal 160 (mid_d1) is used to qualify the amplitude of the transitions. The amplitude required to qualify transitions is programmable by providing appropriate values for a VFO Field threshold 164 (ph_vfo_d1_thresh_reg) and Data Field threshold 166 (ph_data_d1_thresh_reg). These threshold values are utilized to perform an amplitude qualification in order to skip transitions caused by 2 T or 3 T marks and spaces. If the amplitude of the first derivative is sufficiently large and the signal crosses zero a transition is detected and the following values are computed:
In the Read Path:
In the Midpoint Path:
Referring again to
It is noted that the calculation outlined above utilize the second derivatives to determine these intermediate values. In this case, the second derivatives are incorporated to minimize the effects of inter-symbol interference caused by adjacent short marks and spaces. Utilizing these second derivative values, the resulting calculations above provide ISI compensated read samples and midpoints. (read_a, read_b, read_c, read_d and mid_a, mid_b, mid_c, mid_d, respectively). Utilizing these ISI compensated values, the calculated phase errors become much more accurate and avoid the detrimental effects of the proceeding or following short marks and spaces.
Utilizing these ISI compensated samples, phase detection is then completed utilizing the system outlined in
Referring now more specifically to the read samples shown in
Whenever the read samples meet the qualifications for a valid transition (samples A, B, C, or D), the corresponding ISI compensated samples are computed. The ISI compensated samples are determined using the read sample and its second derivative. For example:
When short marks and spaces proceed or follow transitions from long marks and spaces, the transition changes slope near 0, which causes the magnitude of the second derivative to increase. This property of the read signal is used to adjust the values of read_a, b, c, d and thereby minimize the effect of ISI on the phase error calculation. The rough phase error without normalization is equal to the differences of the adjusted values (read—a−read_b) and (read_d−read_c).
As further illustrated in
Using the above outlined ISI compensated read samples and midpoint values, the specialized phase detector 80 is then able to determine related phase errors. As mentioned above, the rough phase errors are easily calculated. However, it is important that the phase error be normalized, and yield a value between −0.5 T and +0.5 T. The normalized phase error value is computed for both the read and midpoints signals using the following equations:
The above outlined calculations are carried out by various calculation systems within phase detector 80. A read signal numerator and denominator calculation block 190 outputs the possible values for both the numerator or denominator of the normalized read signal phase error calculation. These are then provided to a read signal numerator multiplexer (MUX) 194, a read signal denominator multiplexer (MUX) 196 which, under appropriate controls, provides their outputs to read signal phase divider 198. The output from read signal phase divider 198 provides a normalized read signal phase error 199 (read_ph_err) which is thus normalized to yield a value between −0.5 T and +0.5 T. Similarly, midpoint numerator and denominator calculation device 192 provides appropriate calculations to midpoint numerator multiplexer (MUX) 200 and midpoint denominator multiplexer (MUX) 202, which then provide signals to midpoint phase divider 204. The output from midpoint phase divider 204 then provides a normalized midpoint phase error 205 (mid_ph_err), which is again appropriately normalized.
Based on the calculations and analysis outlined above, the read signal phase error 199 determined from the read signal, and the midpoint phase error 205 determined from the calculated midpoints, should be approximately +/−0.5 T apart from one another. In order to provide a double check on the system, both the read signal phase error 199 and the midpoint error 205 are provided to a phase error analysis device 206 for further calculations and analysis. Initially, the relationship between the read signal phase error 199 and the midpoint phase error 205 is analyzed to verify that these two signals are approximately +/−0.5 T apart. This provides a “sanity check” to reduce or avoid the possibility of bad phase error updates due to noise or media defects. Following this check, it is desirable to determine which of the two phase errors are closest to zero. Stated alternatively, the system is looking for the phase error signal with the smallest absolute value. If the read signal of phase error 199 has the lowest absolute value, this value is then output as the selected phase error 210 (ph_err_sel) and passed to a low pass filter 208. Alternatively, if the absolute value of the midpoint phase error 205 is smaller, the system determines that this value should be utilized for further phase error analysis. However, when using the midpoint phase error 199, this phase error value must be corrected or adjusted by adding or subtracting 0.5 T to obtain the proper value. Looking to the actual value of the midpoint phase error 205 determines whether the adjustment should be in the positive or negative direction. More specifically, if the midpoint phase error is greater than zero, then 0.5 T should be subtracted from this value. However, if the midpoint phase error is less than zero, then 0.5 T should be added. Following this adjustment, the midpoint phase error 205 will then be utilized as the selected phase error signal 210 and passed on to the low pass filter 208. As shown in
Another feature of the present system is the ability to detect when “phase rollover” occurs. Phase rollover is defined as the point in time when the above-referenced phase calculations result in the phase error making a discontinuous step from −0.5 T to +0.5 T (positive phase rollover), or a discontinuous step from +0.5 T to −0.5 T (negative phase rollover). This rollover detection is analyzed in rollover detection device 218, which receives the selected phase error 210 and the phase error signal 214, along with an appropriate value from phase roll window register 220. All these signals are combined to detect positive or negative phase rollover, and output appropriate signals. More specifically, phase rollover detect device 218 will output a positive phase rollover signal 222 (ph_pos_roll) or a negative phase rollover signal 224 (ph_neg_roll) when those conditions are detected.
Now referring back to
As shown in
Now referring specifically to
Similarly, the offset control read signal 70 the first derivative 154 and the second derivative 156 are all provided to a plurality of identical delays 104 to provide staged outputs at appropriate points in time. Utilizing these various outputs, and the related signals as shown in
As suggested above, bit slip is an issue for the reconstructor of the present invention, due to the quasi-synchronous nature of the ADC samples. Again, bit slip is defined as the condition where the quasi-synchronous sampling differs by more than plus or minus 0.5 T from a synchronous sampling point. When this occurs, the waveform reconstruction process of the present invention must make appropriate adjustments to accommodate for this slip. Generally speaking, the waveform reconstruction process of the present invention adjusts to utilize a new sample that is within the +/−0.5 T range. This function is accomplished by the various registers or FIFO's shown in
Referring more specifically to the various registers, reconstruction sample FIFO 130 generally contains the reconstructed waveform sample. Insert sample FIFO 132 contains samples to be inserted in the event of a negative phase rollover condition. Decrement FIFO 134 contains a bit flag indicating that the FIFO pointer must be decremented by one, and increment FIFO 136 contains a bit flag indicating that FIFO pointer P 140 must be incremented by one.
Again, during the reading of samples, ADC 44 may be sampling at a faster rate than an ideal synchronous sample rate. This variation in sampling rate causes the above-referenced phase rollover (i.e., phase error magnitude increasing beyond +/−0.5 T, thus causing a discontinuous jump in the measured phase error signal 214). When the sampling rate is slightly faster than ideal, a positive phase rollover occurs, meaning the reconstructed waveform sample 120 must be skipped. Alternatively, when the ADC sampling rate is slightly slower than an ideal rate, a negative phase rollover occurs. During a negative phase rollover condition, an additional reconstructed waveform sample must be inserted (insert sample 122). As discussed above, insert samples 122 are calculated continuously, thus making this insertion fairly straight forward. In order to accomplish this in waveform reconstructor 40, skipping of a sample is accomplished by simply decrementing FIFO pointer 140. On the other hand, when it is necessary to insert a sample, the insert sample 122 is taken from insert FIFO 132, and the FIFO pointer 140 is incremented.
As mentioned, the various FIFOs discussed above are all controlled by FIFO pointer/control device 124. Further details regarding FIFO pointer/control 124 are shown in
Referring again to
Looking now to the generation of FIFO pointer 140 as illustrated in
In addition, FIFO counter and control logic 260 also provides status information to a FIFO status register 270. This status information is generated by FIFO counter and control logic 260. The value of the FIFO pointer is saved at the end of each sector that is read and provided as a final pointer value 280 (fifo_pntr_final_st). FIFO underflow/overflow conditions are also detected. If the FIFO pointer is at 0 and receives a decr bit flag, FIFO Underflow status signal 282 (fifo_underflow st) is posted. Likewise, if the FIFO pointer is at its maximum value and receives an incr bit flag, FIFO Overflow status signal 284 (fifo_overflow_st) is posted. Both of status conditions indicate that uncompensated bit slip has occurred. Two additional status bits are generated that can be used for verifying recorded data. Both of these status bits are utilized to monitor operation as compared to programmable values. When the FIFO pointer is less than a programmable low value 291 (fifo_verify_lo_reg), the verified low status bit 286 is set (fifo_verify_under_st). When the FIFO pointer is greater than a programmable high value 292 (fifo_verify_hi_reg), the verified high status bit 288 is set (fifo_verify_over_st). Information from these two bits can be used to determine if sectors should be relocated due to disk defects that affect the Wobble PLL clock 48 and cause excessive bit slip within a sector.
At the start of reading each sector, FIFO pointer P 140 is initialized with a programmable value (fifo_pntr_init_reg) 294. The FIFO pointer/control logic 260 would typically be initialized to the center (half) of the FIFO length. For example, if a FIFO length of 32 is used, the FIFO pointer P 140 would be initialized to 16. This allows for bit slip in either direction (fast or slow). The FIFO length is determined by the maximum number of channel bits that are expected to slip during the read back of one sector. This will primarily be based on the timing jitter of the Wobble PLL clock 48.
As discussed in relation to
Channel bit decoder 280 is a well understood mechanism that determines the sequence of marks and space lengths, as recorded on the storage media. Typically a Viterbi decoder is used for Partial Response Maximum Likelihood (PMRL) channel design. The decoder produces a bit stream 282 (decode out) that is used by an RLL (1, 7) data decoder (not shown).
Also shown in
As mentioned above, waveform reconstructor 40 also includes a read offset control 68 which generates the read offset signal (read_off) 66 that is fed back to provide offset centering of the reconstructed waveform. Read offset control 68 is shown in more detail in
The first derivative 298 of the reconstructed waveform 142 is calculated in derivative calculator 300 and is defined as follows:
rec_d1n=rec_d0n−rec_d0n-1
Similar to the specialized phase detector 80, the first derivative signal 298 (rec_d1) is used to qualify the amplitude of transitions. The amplitude required to qualify transitions is programmable by an offset VFO threshold signal 302 (off_vfo_d1_thresh_reg) and an offset data threshold signal 304 (off_data_d1_thresh_reg) for the VFO Field and Data Field, respectively. The read offset error 306 (off_err) is computed by finding the center of the long mark and space transitions in the reconstructed waveform. The following equation is used:
if |rec_d1n|>off_data_d1_thresh_reg
off_errn=(rec_d0n+rec_d0n-1)/2
The offset error can be limited in magnitude to minimize undesirable response caused by dust or media defects. The limit is programmable by a VFO error limit value 308 (off_vfo_err_lim_reg) and a data error limit value 310 (off_data_err_lim_reg) providing appropriate values for the VFO Field and Data Field, respectively.
The offset error 306 then feeds into a digital integrator 312. The gain of the integrator is programmable and controlled by a VFO gain value 314 (off_vfo_shift_reg) and a data gain value 316 (off_data_shift_reg) for the VFO Field and Data Field, respectively. The read offset integrator output 320 (read_off) is used as a feedback and subtracted from the equalized read signal 54 (read_eq) to actively control read signal offset variations, as mentioned previously.
Utilizing the system and components outlined above, the waveform reconstructor of the present invention accomplishes the output of read channel signals without the use of a PLL timing loop. Due to the lack of this timing loop, significant advantages are achieved, including higher bandwidth and very fast phase correction. Additionally, the use of a digital equalizer is possible since the output is not dependent upon a PLL.
The advantages and features of the present invention, along with other advantages, will be understood by those skilled in the art. While various embodiments of the present invention have been described above in order to illustrate their features and operation, it is not intended that the present application be limited to these embodiments. It is clearly understood that certain modifications and alterations can be made without departing from the scope and spirit of the following claims.
