Patent Application
20230187904
There is a need to accurately align a laser chip and a Si chip which are used in SiP technology as building blocks for design and fabrication of Photonic integrated Circuits, PICs. In the related designs, the laser chips, consist a laser waveguide which enables to output the laser radiation into a waveguide on the Si chip. To achieve an effective coupling for the laser radiation, the corresponding waveguides on laser and Si chips must be properly aligned. In general, the Si chip comprises the other photonic integrated circuit (PIC), which are driven by the laser's optical signal to achieve a specific functionality of a certain required application.
The activation of the laser chip during an alignment process to a Si chip is costly, complicated, and problematic, especially for devices which are manufactured in mass production. Hence there is a growing demand for methods which doesn't required the laser activation which are defined as passive alignment methods.
Generally, in these alignment methods it is required to fabricate additional elements such as waveguides, marks and other elements on both the laser and Si die parts. The manufacturing cost of these additional elements on the laser dies are significantly higher than on the Si die part. Hence a simplification of either the processing and or die sizes can have a much higher impact on the manufacturing cost of an assembly of PIC circuits composed out of a Laser chip and Si chip.
Hence there is a high motivation to develop such alignment methods which can simplify the alignment process and reduce manufacturing cost of the laser die/chip. Furthermore, there is a high motivation to develop such alignment methods which will have almost no impact on the related PIC circuit performance, composed of an assembly laser and Si chips.
In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, and components have not been described in detail so as not to obscure the present invention.
The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.
Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
Any reference in the specification to a method should be applied mutatis mutandis to a device or system capable of executing the method.
Any reference in the specification to a system or device should be applied mutatis mutandis to a method that may be executed by the system.
Any combination of any module or unit listed in any of the figures, any part of the specification and/or any claims may be provided.
Any combination of any steps of any method illustrated in the specification and/or drawings may be provided.
Any combination of any subject matter of any of claims may be provided.
Any combinations of systems, units, components, processors, sensors, illustrated in the specification and/or drawings may be provided.
There is provided a method and a system for passive alignment between a laser chip and an electrooptic chip, the electrooptic chip may include one or more optical elements configured to receive radiation from the laser chip, without a requirement for the laser activation and without requiring to use costly alignment equipment such as optical backscatter reflectometers that are very expensive and have very slow mode of operation.
The alignment electrooptic chip may include a Wavelength Selective Coupler (WSC) that is configured to define a first WSC optical path between the laser chip and a first part of the electrooptic chip and to define a second WSC optical path between the laser chip and a second part of the electrooptic chip.
The first part of the electrooptic chip may be or may include alignment circuitry.
The second part of the electrooptic chip may be or may include an electrooptic unit such as a photonic integrated circuit (PIC).
The second part may also be referred to as an operational part, a main part, a functional part, or a post-alignment part of the electrooptic chip.
The first WSC path and at least some of the components of the first part of the electrooptic chip form a first optical path that is utilized during the alignment process.
The first optical path may be configured to convey radiation (also referred to as probe radiation) within a first wavelength range—and may be centered about a first wavelength.
The first optical path may be used to convey radiation from a radiation source (also referred to as alignment radiation source) located within the electrooptic chip. The alignment radiation source may be external to the electrooptic chip—and the electrooptic chip may be optically coupled to the alignment radiation source and configured to convey the radiation of the alignment radiation source through the first optical path to the laser chip.
The first optical path may include the laser waveguide or may use a different waveguide (for example an auxiliary waveguide) of the laser chip.
The second WSC path and at least some of the components of the second part of the electrooptic chip form a second optical path that may be utilized after the completion of the alignment process.
The second optical path may be configured to convey radiation of a second wavelength range—and may be centered about a second wavelength.
The first wavelength may differ from the second wavelength.
The first wavelength range may differ from the second wavelength range. The first and second wavelength ranges may be non-overlapping.
The first and second wavelength ranges may be distance from each other to enable the WSC to easily differentiate between them.
Due to the wavelength selective behavior of the WSC (which differentiates between the first and second wavelength ranges), there may be no need to move the electrooptic chip in relation to the laser chip once alignment is obtained.
The second optical path may be used to convey radiation from the laser chip to the electrooptic chip.
Using the WSC during alignment allows wafer level pick and place process using coupling to grating couplers. This allows an alignment method that does not depend (as in an Optical Backscatter Reflectometry (OBR) based method) on the electrooptical unit design and application. It may also be used in a high loss electrooptical unit—which may be problematic with the OBR based method. The OBR based involves using a very expensive OBR measurement device and complicated and slow scan mode. See, for example Flip-chip Integration of InP to SiN Photonic Integrated Circuits, M. Therurer Et el, Journal of Lightwave Technology, Vol. 38, No.9, May 2020.
The first path may include a coupler such as a grating coupler. Such a coupler may or may not be provided in the second path.
The second path may be regarded as the operational path or main path or functional path or post-alignment path of the system—and it may exhibit lower losses than the first path.
The second path may be independent from the first path—so that any energy penalty occurring during the alignment process may not affect the passage of radiation through the second path.
The method may include performing a Back Reflection setup measurement, for example—obtaining a single readout (or a few readouts), using special PIC design with external source and power meter. This allows a very fast scan of placement and alignment. This is in contrary of using OBR based method—that requires sweeping wavelengths on every location—that is a very time consuming process at each location and requires analysis of OBR data.
During the alignment, the laser chip is illuminated with radiation over the first path—and reflect back reflected radiation over the first path. The reflection can be mainly (almost only) from a laser waveguide of the laser chip (minor reflection can be from the WSC). Allowing one readout method. This is in contrary to the OBR based method. This method may be applied for an electrooptic chip having any electrooptical unit any electrooptic chip, even with high losses. This is in contrary of using the OBR based method that suffers from having reflections from various components such as free space, electrooptical components, laser, that require using OBR.
The method may avoid the activation of the laser which is costly and complicated for high volume manufacturing of these device. Furthermore, in the disclosed method the first waveguide is aligned directly to a laser waveguide with almost no requirements for additional passive alignment elements on the laser die part. This results in a highly accurate passive method which have accuracy similarly to active alignment method.
A first detector 12 and a first radiation source 13 may also be included in system 100. The first detector 12 and the first radiation source 13 may be located outside the electrooptic chip 10 (as shown in
The first detector 12 and the first radiation source 13 may be optically coupled to the electrooptic chip in various manner—for example by a fiber array 29 that includes spaced apart fibers (illustrates as lines that pass through the rectangle denoted 29).
It should be noted that the system 100 may not include IML 30.
The laser chip 40 includes a laser waveguide 44 located at a top of the laser diode body/chip 43, and is illustrated as having a distal reflective element such as high reflective coating layer 42, and a proximal reflective element such as low reflective coating layer 41.
The low reflective coating layer 41 may be an Anti-Reflective Coating (ARC) layer designed reduce the internal reflections from the laser chip output facet back into the laser chip.
The distal reflective element may be a wavelength selective element (for example—be a Low Bandwidth Reflective Layer) that is configured to have a high reflectivity in the first wavelength range and have low reflectivity in the second wavelength range.
The electrooptic chip 10 may include WSC 20, first part 31, and second part 32.
First part 31 may include first coupling unit 18.
The first radiation source 13 is optically coupled via a fiber and via a port of the electrooptic chip 10 to a first port 18a of the first coupling unit 18.
The first detector 12 is optically coupled via another fiber and via another port of the electrooptic chip 10 to a second port 18b of the first coupling unit 18.
A third port 18c of the first coupling unit 18 is optically coupled to a first WSC port 20a of WSC 20.
A fourth port 18d of the first coupling unit is grounded or otherwise ignored of.
Second part 32 includes an electrooptical unit such as photonic integrated circuit (PIC) 22. PIC 22 may include a receiver, may include transmission path optics, may be a sensor, a modulator, a bio sensor, or any other PIC.
A first port 22a of PIC 22 is optically coupled to a second WSC port 20b of WSC 20 via PIC waveguide 14.
A second port 22b of PIC 22 may be optically coupled to any other unit—such as post-PIC unit 15.
A third port 20c of WSC 22 is optically coupled to first waveguide 11.
A fourth port 20d of WSC 22 is grounded or otherwise ignored of.
The following examples illustrates the progress of signals through the system. The passage may amend any signal—for example reduce the intensity of the signal, add noise or perform any other operation. For simplicity of explanation the same term is used to describe the signal throughout the progress.
During the alignment process a probe signal 61 is
When the first waveguide 11 is aligned with the laser waveguide 44, then the probe signal 61 also passes through the laser waveguide and is reflected from the distal reflective element to provide a reflected probe signal 62.
The reflected probe signal 62:
When the first waveguide 11 is not aligned with the laser waveguide 44, then the probe signal 61 may be barely (and even insignificantly) reflected from proximal reflective element to provide the reflected probe signal.
In any case—it is expected that the reflected probe signal 62 from an aligned laser chip significantly differs from the reflected probe signal 62 from an unaligned laser chip—thereby allowing to determine whether the lase chip is aligned (with the electrooptic chip).
The detection signals of first detector 12 may be processed by a controller 70 to assist in the alignment process.
The controller 70 may control the spatial relationship between the laser chip 40 and the electrooptic chip 100—for example by controlling or requesting the movement of one (or both) of the chips until an alignment stop condition is fulfilled—for example—an alignment is obtained, the alignment failed, a predefined number of alignment iterations were executed, and the like.
For example—one or more chip of the electrooptic chip and the laser chip can be mechanically manipulated—for example along x,y-directions, with a sufficiently large spatial resolution. The mechanical manipulation can be done along a plane that is perpendicular to the optical axis of the laser waveguide. It should be noted that at the start of the alignment process the electrooptic chip and the laser chip may be roughly aligned.
During the alignment process, the strength of the reflected probe signal may provide an indication of the degree of alignment—for example—stronger reflected probe signal can indicate of a better alignment.
The probe signal 61 and the reflected probe signal 62 pass through the first optical path.
During an operational mode, the laser chip 40 outputs a laser signal 63 that is:
The optically processed laser signal may be outputted from second port 22b of PIC 22 to post-PIC unit 15.
Once aligned—the position of the laser chip and the electrooptic chip may be fixed. For example—the laser chip can be bonded to the electrooptic chip, the electrooptic chip may be bonded to the laser chip—or one or both chips can be bonded to a third component.
The IML 30 is configured to fill air gaps between the laser chip and the electrooptic chip. The IML 30 may also be configured to mechanically bond the laser chip to the electrooptic chip.
The IML 30 may be configured to reduce reflection (related to radiation within the first wavelength range and the second wavelength range) which may evolve by an index mismatch due to air gaps between the laser chip and the electrooptic chip.
The IML 30 may be an Ultraviolet glue which is fabricated in a gel phase. In this case, the refractive index of the first waveguide may be fabricated from a core and of cladding layers that can be made of Oxide, Nitride, Si or any other dielectric material.
The low reflective coating layer may be designed to have a refractive index which matches the refractive index of the first waveguide 11, thereby reducing internal reflections magnitude between the laser chip 40 and the electrooptic chip 10.
The first waveguide 11 may include a plurality of waveguide segments of Nit and Ox, Oxynitride layers.
The first waveguide 11 may include tapers along the alignment waveguide of the Si layer edge.
The first waveguide 11 may include a combination of Nit and Ox, Oxynitride layers.
A first detector 12, a second detector 12′, and a first radiation source 13 may also be included in system 101. The first detector 12, the first radiation source 13 and the second detector 12′ may be located outside the electrooptic chip 10 (as shown in
The first detector 12, the second detector 12′ and the first radiation source 13 may be optically coupled to the electrooptic chip in various manner—for example by a fiber array 29 that includes spaced apart fibers (illustrates as lines that pass through the rectangle denoted 29).
System 101 differ from system 100 by having a probe signal measurement circuit that includes a fifth port 18e of the first coupling unit and a second detector 12′. The additional port 16e provides a sample of the probe signal, and the second detector 12′ measures the sample.
The detection signals of the second detector may be sent to controller 70. Controller 70 may determine the different between the probe signal and the reflected probe signal.
First coupling unit 18 include first coupler 12a for providing reflected probe radiation to the first detector 12 (via second port 18b), second coupler 13a for receiving the probe radiation from the first radiation source 13 (via port 18a), third coupler 14a for providing a sample of the probe radiation (via port 18e) to second detector 12′, and fourth coupler 17.
There may be any type of couplers.
The first and second couplers may be grating couplers.
The fourth coupler 17 may be a 2×1 directional coupler that may be implemented by 2×2 directional coupler with a termination connected to fourth port 17d. The termination eliminates almost completely back reflections of the probe signal and the reflected probe signal.
First port 17a of fourth coupler 17 is optically coupled to an output of second coupler 12a.
Second port 17b of fourth coupler 17 is optically coupled to an output of first coupler 13a.
Third port 17c of fourth coupler 17 is optically coupled to a first port 20a of WSC 20.
The WSC 20 may be implemented in various manners—for example
The WSC can be replaced by SM optical 2×1 multiplexer or by an add-drop filter, configured to support a first internal optical path for radiation of the first wavelength range and a second internal path for radiation of the second wavelength range.
The WSC can include two parallel waveguides which are coupled by a ring resonator device so that at the first wavelength range, these waveguide are selectively coupled routing the signals of the first wavelength range to the coupler unit, and at the second wavelength range the signals are directed to the PIC .
The WSC device may include a ring resonator coupler which couples incoming light from the coupler unit at a resonant wavelength centered around the first wavelength, alignment waveguide at the Si part.
The WSC may include a ring resonator coupler which is composed out of two implanted n-type and p-type segments and an intrinsic segments, wherein n-type and p-type segments are externally contacted to Voltage source which is used to apply a voltage on the implanted n type and p-type side hence modify the refractive index of the ring resonator enabling a tuning of its resonant coupling wavelength.
The WSC may include a split ring resonators made of split ring resonator made of dielectric maleic or dielectric material which can be processed on the Si chip side and which can couple the incoming light from the coupler unit at a resonant wavelength centered around the first wavelength, waveguide alignment wave guide at the Si part.
The WSC may include WSC made of metallic split ring resonator.
The WSC may include made of a 1D, 2D or 3D photonic crystal structure made of rods holes in circular cylindrical or any arbitrary shape made of dielectric or metallic material which can processed on the Si chip and which can couple the incoming light from the coupler unit at a resonant wavelength centered around the first wavelength (λ1), waveguide alignment wave guide at the Si part.
It is noted that the WSC may provide selective routing of signals over more than two different wavelength ranges—and it has more than two WSC optical paths. This can be achieved by cascade of WSC devices, and/or by using multiple directional couplers.
Instead of tapping the radiation from the first radiation source (as in
Method 400 may be for aligning a laser chip with an electrooptic chip.
Method 400 may include one or more alignment iterations.
Each alignment iteration may start by step 410 of directing a probe signal from the electrooptic chip towards the laser chip.
Step 410 may be followed by step 420 of detecting a reflected probe signal by a first detector of the electrooptic chip, the reflected probe signal being reflected from the laser chip.
The probe signal and the reflected probe signal are within a first wavelength range.
The reflected probe signal passes through a first optical path of the electrooptic chip, the first optical path being configured to convey signals within the first wavelength range.
The first optical path differs from a second optical path of the electrooptic chip, the second optical path is configured to convey signals within a second wavelength range that differs from the first wavelength range.
The laser chip is configured to output a laser signal within the second wavelength range.
Steps 410 and 420 occur while maintaining a current spatial relationship between the laser chip and the electrooptic chip. This is illustrated by step 440 of maintaining a current spatial relationship between the laser chip and the electrooptic chip.
Step 420 may be followed by step 430 of determining, based on the reflected probe signal, whether the laser chip is aligned with the electrooptic chip.
If aligned—the step 430 may be followed by post-alignment step 450.
The post alignment step 450 may include, for example fixing the spatial relationship between the laser chip and the electrooptic chip.
If misaligned—step 430 may include changing (step 460) the current spatial relationship and jumping to step 410.
Step 460 may be executed in any manner—for example following a predefined set of spatial relationships, searching for a local or global alignment extremum point, and the like.
It should be noted that reaching a stop condition—for example—no alignment was obtained for at least a first plurality of alignment iterations—then an alignment failure may be declared.
Yet another stop condition is reaching a certain (while not perfect) alignment—after a second plurality of alignment iterations—then an alignment success may be declared.
Step 410 may include receiving the probe signal by a first wavelength selective coupler (WSC) port of a WSC of the electrooptic chip, directing the probe signal from the first WSC port to a second WSC port, through a first WSC optical path that is configured to convey signals within the first wavelength range, and outputting the probe signal from the second WSC port to a first waveguide.
Step 420 may include receiving the reflected probe signal by the second WSC port and from the first waveguide; and directing the reflected probe signal from the second WSC port to the first WSC port, through the first WSC optical path.
A third WSC port of the WSC is optically coupled to the second WSC port via a second WSC optical path that is configured to convey signals within the second wavelength range.
Method 400 may include step 460 of measuring a sample of the probe signal to provide a probe signal measurement. Step 430 may be responsive to the measurement—especially responsive to the difference of the probe signal (as indicated by the sample) and the reflected probe signal.
Method 400 may be executed while a laser of the laser chip is deactivated.
Steps 410 and 420 may be executed by an alignment unit of the electrooptic.
Method 500 may be for operating a laser chip.
Method 500 may include step 510 of outputting a laser signal from the laser chip towards an electrooptic chip that is aligned with the laser chip.
Step 510 may be followed by step 520 of passing the laser signal through a second optical path of the electrooptic chip, the second optical path is configured to convey signals within a second wavelength range, wherein the laser signal is within the second wavelength range.
The alignment between the electrooptic chip and the laser chip may be obtained by executing any step of method 400.
The successful completion of method 400 may be a prerequisite to the execution of steps 510 and 520.
The Si chip/Electrooptic chip may be fabricated from Si on Insulator Wafers (SOI wafers). The SOI wafer may include the following layer stuck:
PIC elements of the electro optical chip/Si chip, such as all waveguiding structures, couplers, grating couplers, WSC devices other couplers and all other devices may be fabricated on the SOI wafer Si top layer.
Ports of optical components and/or optical components may be optically coupled to each other using waveguides. For simplicity of explanation only some of the waveguides are associated with reference numbers.
In
Port 718a is optically coupled (via waveguide 761) to an output of the external laser source 713. Port 718d is optically coupled (via waveguide 762) to port 720a. Port 720c is optically coupled to waveguide 711. Ports 720b is optically coupled to waveguide 714 and to one port of PIC-1722. Another port of PIC-1722 is optically coupled to waveguide 715.
In
In
Port 718b′ is optically coupled (via waveguide 763′) to an input of first detector 712′. Port 718d′ is optically coupled (via waveguide 762′) to port 720a′. Port 720c′ is optically coupled to waveguide 711′. Ports 720b′ is optically coupled to waveguide 714′ and to one port of PIC-2722′. Another port of PIC-2722′ is optically coupled to waveguide 715′.
In
In
In
When the multiple chip regions are aligned—one end of the auxiliary waveguide 745 is aligned with waveguide 719 that is optically coupled to port 718c, another end of the auxiliary waveguide 745 is aligned with waveguide 719′ that is optically coupled to port 718c′.
In
If the multiple chip regions are aligned, the first optical probe signal passes through waveguides 743 and 743′ and active electrooptical component 744, through IML layer 742′, through LR layer 730′, through waveguide 711′, to port 720c′, through WSC-2720′, from port 720a′, through coupler unit-2718′, from port 718b′ to first detector PD 712′.
If the multiple chip regions are not aligned the first detector PD 712′ may not receive any significant signal.
After the multiple chip regions are aligned and bonded and after the active electrooptical component 744 can be activated (may be required to form conductive paths for activating the active electrooptical component)—then PIC-1722 may provide, during a transmission iteration, a transmitted optical signal of the second wavelength band (PIC-1722 may generate the transmitted optical signal or may receive the transmitted optical signal via waveguide 715). The transmitted optical signal may propagate over waveguide 714, to port 720b, through WCS-1720, from port 720c, through waveguide 711 and towards LR layer 730. IML layer 742 and to intermediate chip region 740, through the intermediate chip region (through waveguides 743, especially be received by active electrooptical component 744 and be optically processed—for example amplified), through IML layer 742′, through LR layer 730′, through waveguide 711′, to port 720c′, through WSC-2720′, from port 720b′, to PIC-2722′, through waveguide 715′ and outside the second chip region.
The reverse direction path may be provided from PIC-2722′ to PIC-1722.
The first chip region 710″ of
Port 718a is optically coupled to an output of the external laser source 713. Port 718d is optically coupled to port 720a. Port 720c is optically coupled to waveguide 711 that terminates in second port 792. Port 720d is optically coupled (via a waveguide) to first port 791. Port 720b is optically coupled to waveguide 714 and to one port of PIC-1722. Another port of PIC-1722 is optically coupled to waveguide 715.
During an alignment iteration the external laser source 713 transmits a first optical probe signal of first wavelength band (that includes first wavelength λ1) to port 718a, through coupler unit-1718, from port 718d to port 720a, through WSC1720, from port 720d, through waveguide 711 and towards IML layer 742, LR layer 730 and to other chip region 750.
If the multiple chip regions are aligned, the first optical probe signal passes through waveguide 743′, through active electrooptical component 744, through LR layer 730, through IML layer 742, through LR layer 730, through a waveguide to port 720d, through WSC-1720, from port 720a, to port 718d, through coupler unit-1718, from port 718b to second detector PD 712.
If the multiple chip regions are not aligned the first detector PD 712 may not receive any significant signal.
After the multiple chip regions are aligned and bonded and after the active electrooptical component 744 can be activated (may require to form conductive paths for activating the active electrooptical component)—then PIC-1722 may provide, during a transmission iteration, a transmitted optical signal of the second wavelength band (PIC-1722 may generate the transmitted optical signal or may receive the transmitted optical signal via waveguide 715). The transmitted optical signal may propagate over waveguide 714, to port 720b, through WCS-1720, from port 720c, through waveguide 711 and towards LR layer 730, IML layer 742 and to other chip region 750, through the other chip region (through waveguide 743′, especially be received by active electrooptical component 744 and be optically processed—for example amplified, and through waveguide 743), through LR layer 730, through IML layer 742, through a waveguide to port 720d, through WSC-1720, from port 720b back to PIC-1722, through waveguide 715′ and outside the second chip region. Another PCI may receive the transmitted optical signal after being optically processed by the active electrooptical component 744.
Method 1000 may include multiple alignment iteration. The method may include one or more alignment iterations. The alignment iterations may stop when alignment is reached, or when the alignment is deemed to fail.
Method 1000 may start by step 1010 of directing, during an alignment iteration, a first optical probe signal of a first wavelength band, from a first chip region towards an intermediate chip region. The multiple chip regions may include the first chip region, the intermediate chip region, and a second chip region.
The intermediate chip region may include an intermediate optical path, that is at least partially transparent to the first wavelength band and to a second wavelength band. The second wavelength band does not overlap the first wavelength band. The active electrooptical component is maintained idle during the alignment iteration.
When the multiple chip regions are aligned the intermediate optical path optically couples the multiple chip regions.
Step 1010 may include at least one of the following:
Step 1010 may be followed by step 1020 of evaluating one or more signals generated by a detector of the second chip region during the alignment iteration to determine whether the multiple chip regions are aligned.
If it is determined that the multiple chips regions are not aligned—step 1020 may be followed by step 1022 of determining whether to perform another alignment iteration.
Step 1022 may be followed by ending the method (“END”) when determining not to perform another alignment iteration.
Step 1022 may be followed by step 1024 of changing the spatial relationship between the multiple chips and jumping to step 1010—when determining to perform the other alignment iteration.
If it is determined that the multiple chips regions are aligned—step 1020 may be followed by step 1030 of maintaining a spatial relationship between the multiple chip regions.
Step 1030 may include attaching—for example—bonding the multiple chip regions.
Step 1030 may be followed by step 1040 of operating the multiple chip regions.
Step 1040 may be preceded by enabling the active electrooptical component to be activated—for example forming conductive paths to activate the active electrooptical component.
Step 1040 may include at least one of:
The intermediate optical path may pass through the active electrooptical component.
The intermediate optical path may not pass through the active electrooptical component—for example may pass through an auxiliary path.
The active electrooptical component may be a semiconductor optical amplifier (SOA)—or may differ from the SOA.
The first chip region and the second chip region may belong to a single integrated circuit.
The intermediate optical path may include one or more waveguides and anti-reflective elements.
Method 1100 may start by step 1110 of directing, during an alignment iteration, a first optical probe signal of a first wavelength band, from a first port of a first chip region towards another chip region. The multiple chip regions may include the first chip region and the other chip region.
The second chip region may include an intermediate optical path that is at least partially transparent to the first wavelength band and to a second wavelength band, the second wavelength band does not overlap the first wavelength band.
The intermediate optical path may pass or may not pass through an active electrooptical component of the intermediate chip region. The active electrooptical component is idle during the alignment iteration.
When the multiple chip regions are aligned the intermediate optical path optically couples the first port (for example first port 791 of
Step 1110 may be followed by step 1120 of evaluating one or more signals generated by a detector of the first chip region during the alignment iteration to determine whether the multiple chip regions are aligned.
Step 1120 may be followed by step 1130 of maintaining a spatial relationship between the multiple chip regions when it is determined that the multiple chip regions are aligned.
While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.
Any reference to comprising or including should be applied mutatis mutandis to consisting and/or to “consisting essentially of”.
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.
Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures may be implemented which achieve the same functionality.
Any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality may be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “operably coupled,” to each other to achieve the desired functionality.
Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.
However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.
It is appreciated that various features of the embodiments of the disclosure which are, for clarity, described in the contexts of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of the embodiments of the disclosure which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.
It will be appreciated by persons skilled in the art that the embodiments of the disclosure are not limited by what has been particularly shown and described hereinabove. Rather the scope of the embodiments of the disclosure is defined by the appended claims and equivalents thereof.
| Number | Date | Country | |
|---|---|---|---|
| 63202039 | May 2021 | US | |
| 63120713 | Dec 2020 | US | |
| 63061014 | Aug 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/IB21/57145 | Aug 2021 | US |
| Child | 18165293 | US |
