The present disclosure relates generally to semiconductor memory and methods, and more particularly, to wear leveling memory using error rate.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.
Memory devices can be combined together to form a storage volume of a memory system such as a solid state drive (SSD). A solid state drive can include non-volatile memory (e.g., NAND flash memory and NOR flash memory), and/or can include volatile memory (e.g., DRAM and SRAM), among various other types of non-volatile and volatile memory.
An SSD can be used to replace hard disk drives as the main storage volume for a computer, as the solid state drive can have advantages over hard drives in terms of performance, size, weight, ruggedness, operating temperature range; and power consumption. For example, SSDs can have superior performance when compared to magnetic disk drives due to their lack of moving parts, which may avoid seek time, latency, and other electro-mechanical delays associated with magnetic disk drives.
Flash memory cells experience wear due to, for example, damage to a tunnel oxide layer as electrons move therethrough (e.g., via quantum mechanical tunneling) in association with program and erase operations. As such, the memory cells of an SSD can experience data retention issues over the lifetime of the device. As an example, some flash memory cells (e.g., multilevel cells (MLCs)) can be expected to sustain 10,000 program/erase (P/E) cycles per cell before an SSD reaches an endurance limitation, which can refer to the number of P/E cycles beyond which the SSD is no longer reliable.
The lifetime of an SSD can be determined, for instance, based on its weakest memory device (e.g., die). As an example, once individual groups of cells (e.g., blocks and/or physical pages) within a memory device of an SSD start to develop increased bit errors (e.g., an amount of bit errors which are not correctable via an error detection/correction component), the entire SSD may be considered to have reached its end of life.
In order to spread wear among groups of memory cells of an SSD, a process known as wear leveling can be used. Such wear leveling can prevent particular cells from experiencing excessive wear as compared to other cells, which can extend the life of an SSD. SSD controllers may implement wear leveling algorithms of varying complexity and/or sophistication in order to maintain even wear among cells of the SSD. As an example, some wear leveling algorithms may result in differences in wear among blocks of cells less than 0.5% or less.
The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.
A number of embodiments of the present disclosure can improve wear leveling as compared to previous techniques, which can extend the useful lifetime of a memory apparatus (e.g., an SSD), for instance. As described further herein, a number of embodiments can provide benefits such as reducing over provisioning, reducing power consumption, and improving data reliability and/or integrity as compared to previous wear leveling approaches, among other benefits.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how a number of embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure.
As used herein, “a number of something can refer to one or more such things. For example, a number of memory devices can refer to one or more memory devices. Additionally, the designators “N”, “B”, “R”, and “S” as used herein, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with a number of embodiments of the present disclosure.
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 110 may reference element “10” in
As illustrated in
Host 102 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host 102 can include a system motherboard and/or backplane and can include a number of memory access devices (e.g., a number of processors).
The memory devices 110-1, . . . , 110-N can include a number of arrays of memory cells (e.g., non-volatile memory cells). The arrays can be flash arrays with a NAND architecture, for example. However, embodiments are not limited to a particular type of memory array or array architecture. As described further below in connection with
In operation, data can be written to and/or read from a memory device of a memory system (e.g., memory devices 110-1, . . . , 110-N of system 104) as a page of data, for example. As such, a page of data can be referred to as a data transfer size of the memory system. Data can be transferred to/from a host (e.g., host 102) in data segments referred to as sectors (e.g., host sectors). As such, a sector of data can be referred to as a data transfer size of the host.
The controller 108 can communicate with the memory devices 110-1, . . . , 110-N to control data read, write, and erase operations, among other operations. The controller 108 can include, for example, a number of components in the form of hardware and/or firmware (e.g., one or more integrated circuits) and/or software for controlling access to the number of memory devices 110-1, . . . , 110-N and/or for facilitating data transfer between the host 102 and memory devices 110-1, . . . , 110-N. For instance, in the example illustrated in
The memory management component 114 can implement wear leveling to control the wear rate on the memory devices 110-1, . . . , 110-N. Wear leveling can reduce the number of process cycles (e.g., program and/or erase cycles) performed on a particular group of cells by spreading the cycles more evenly over an entire array and/or device. Wear leveling can include dynamic wear leveling to minimize the amount of valid blocks moved to reclaim a block. Dynamic wear leveling can include a technique called garbage collection. Garbage collection can include reclaiming (e.g., erasing and making available for programming) blocks that have the most invalid pages (e.g., according to a “greedy algorithm”). Alternatively, garbage collection can include reclaiming blocks with more than a threshold amount (e.g., quantity) of invalid pages. If sufficient free blocks exist for a programming operation, then a garbage collection operation may not occur. An invalid page, for example, can be a page of data that has been updated to a different page. Static wear leveling can include writing static data to blocks that have high program/erase counts to prolong the life of the block.
The controller 108 can be configured to control (e.g., via memory management component 114) wear leveling using error rate in accordance with a number of embodiments described herein. For instance, the error detection/correction component 118 can be used to detect and/or correct erroneous bits in association with reading data from memory devices 110-1 to 110-N. As an example, the error detection/correction component 118 can employ error correcting codes (ECC) such as low density parity check (LDPC) codes and Hamming codes, among others). In a number of embodiments, and as described further below in connection with
As shown in
In the example shown in
As shown in
As one of ordinary skill in the art will appreciate, each row 220-1, 220-2, . . . , 220-R can comprise one or more physical pages of cells. A physical page of cells can refer to a number of memory cells that are programmed and/or read together or as a functional group. In the embodiment shown in
In the example shown in
Memory devices such as memory device 210 can have a finite lifetime associated therewith. For instance, the cells of memory device 210 may become unreliable after a particular quantity of process cycles (e.g., program and/or erase (P/E) cycles) have been performed thereon. The particular process cycle count at which a memory device becomes unreliable can vary and can depend on various factors such as manufacturing differences between devices, operating temperatures and/or storage temperatures associated with the memory devices, and the error detection/correction capability associated with a memory device, among other factors. In various instances, a product specification may indicate a process cycle count below which the memory cells are “guaranteed” to maintain reliability. Such guaranteed process cycle counts can depend on factors such as whether the cells are single level cells or multi-level cells, for example, and can be values such as 1,000 cycles, 5,000, cycles, 10,000 cycles, or 100,000 cycles.
Some memory systems employ over-provisioning (OP) to prolong the lifetime of an SSD, for instance. OP can limit the accessible amount of memory allowed by the controller (e.g., controller 108 shown in
In some instances, an SSD may be considered to have reached its end of life once the total bytes written (TBW) to the SSD (e.g., to the memory devices of the SSD) has reached a threshold level, which may be indicated as part of a product specification provided by the device manufacturer, for instance.
In some previous approaches, blocks of an SSD are retired when they reach or exceed a threshold program and/or erase (P/E) cycle count. To spread wear among the blocks of the SSD, wear leveling can be performed based on the program and/or erase (P/E) cycle counts. For instance, a block may be selected to receive data in association with a programming operation based on a determination that the block has a lowermost P/E cycle count corresponding thereto. However, some groups of memory cells (e.g., blocks and/or pages) are still reliable even after reaching or exceeding the threshold P/E cycle count. For example, an error rate corresponding to a block of cells may be well below a reliable threshold error rate despite the block having a reached or exceeded the threshold P/E cycle count used by the wear leveling algorithm to determine when blocks will be retired. Therefore, retiring such groups of memory cells can needlessly reduce the useful life of an SSD.
In a number of embodiments, the group to be programmed is selected based, at least partially, on a process cycle count corresponding to the selected group. For instance, the group having a lowermost cycle count corresponding thereto may be selected. The process cycle counts corresponding to the respective groups can be maintained in memory on the controller and/or in the groups of memory cells themselves. A number of embodiments include determining which of the respective groups of memory cells is to receive data in association with a program operation based on the maintained process cycle counts until a threshold process cycle count is reached or exceeded, and thereafter (e.g., subsequent to the threshold process cycle count being reached) determining which of the respective groups of memory cells is to receive data in association with a program operation based on determined error rates corresponding to the respective groups of memory cells.
At 332, the method includes determining whether a threshold process cycle count (Tpcc) has been reached or exceeded. The Tpcc can be a threshold amount (e.g., quantity) of program and/or erase cycles performed on the group, for instance. The Tpcc can be determined, for example, based on a product specification provided by a device manufacturer. For instance, the Tpcc may be a particular fraction of the amount of process cycles guaranteed by the product specification. As an example, if an SSD product specification indicates that the cells of the SSD are guaranteed up to 10,000 P/E cycles, then the Tpcc may be ¼ of the guaranteed amount (e.g., 2,500 cycles), ½ of the guaranteed amount (e.g., 5,000 cycles), or ¾ of the guaranteed amount (e.g., 7,500 cycles). In a number of embodiments, the method shown in
In the example shown in
At 338, the method of
In a number of embodiments, and as illustrated at 452, the maintained process cycle counts corresponding to the respective groups of memory cells can be adjusted based on determined error rates corresponding to the respective groups. The error rates corresponding to the groups of memory cells can be determined, for instance, responsive to the process cycle count reaching or exceeding one or more threshold counts. However, embodiments are not so limited. For example, in a number of embodiments, error rates corresponding to the respective groups of memory cells can be determined via a background sampling process. For instance, the controller can be used to determine error rates of the respective groups at various times (e.g., while data is being programmed to the memory, read from the memory, erased, and/or while an SSD is not actively processing memory commands).
In a number of embodiments, and as described further below in connection with
In a number of embodiments, the TBW (e.g., the total amount of data programmed to an SSD) can be tracked (e.g., via a controller). As an example, wear leveling can be performed on the memory based on process cycle counts until a threshold amount of data is written to the memory, and thereafter wear leveling can be performed on the memory based on error rates. As such, groups of memory cells having high process cycle counts, which may be retired (e.g., removed from usage) due to a likelihood of unreliability and/or failure, may remain in usage for an extended period (e.g., beyond a process cycle count threshold) due to the group of cells having an acceptably low error rate.
As shown at 454, the method of
In a number of embodiments, a controller (e.g., controller 108 shown in
In a number of embodiments, and as illustrated at 563, error rates corresponding to the respective groups 562 can be determined. As illustrated in table 570, the process cycle counts 564 corresponding to the respective groups 562 can be adjusted based on determined error rates corresponding to the groups. The error rates corresponding to the groups 562 can be determined responsive to the process cycle reaching or exceeding one of a number of threshold process cycle counts. For example, the error rates corresponding to the groups 562 may be determined only after the groups have experienced each of a number of particular threshold process cycle counts (e.g., after 1,000 P/E cycles, after 2,000 P/E cycles, after 5,000, and after 7,500 P/E cycles). However, embodiments are not so limited. For instance, in a number of embodiments, the error rates corresponding to the number of groups 562 may be determined via a background sampling process.
Table 570 illustrates an adjustment to the process cycle count 569 of the selected group 565 (e.g., group 3) responsive to the determined error rate corresponding thereto. In this example, the process cycle count 569 corresponding to the selected group 565 is adjusted from “X” to “X+Y”. The quantity “Y” can be a positive or negative value. That is, the maintained process cycle count 569 can be increased or decreased responsive to the determined error rate at 563. As such, in a number of embodiments, the maintained process cycle counts 564 corresponding to the groups of memory cells 562 can be adjusted (e.g., changed) from an actual value (e.g., “X”) to a different value (e.g., a value other than the actual value such as “X+Y”). Adjusting the actual values of the process cycle counts 564 can affect a wear leveling algorithm that selects groups to be programmed based on the process cycle counts corresponding to the groups. associated with the groups (e.g., by causing groups to be programmed more or less frequently due to adjustments to the process cycle counts).
In a number of embodiments, wear leveling performed on groups of memory cells (e.g., 562) can include selecting groups to be programmed based on process cycle counts (e.g., 564) until a threshold process cycle count is reached or exceeded, and thereafter selecting groups to be programmed based on determined error rates corresponding to the groups. That is, wear leveling can be based on process cycle counts until a threshold process cycle count is reached or exceeded, and then the wear leveling can be based on error rates thereafter (e.g., subsequent to a threshold process cycle count being reached or exceeded).
Using error rates in association with wear leveling as described herein can increase the useful life of a memory (e.g., an SSD), among other benefits, by better accounting for device to device (e.g., die to die) variability as compared to previous wear leveling approaches. For example, a number of embodiments of the present disclosure can reduce over provisioning and improve the reliability, data integrity, and/or performance of SSDs as compared to previous wear leveling approaches.
The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.
Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of a number of embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. Combination of the above embodiments, and other embodiments not specifically described herein will be apparent to those of skill in the art upon reviewing the above description. The scope of a number of embodiments of the present disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of a number of embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.
In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the present disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.