Wide range multi-phase delay-locked loop

Abstract

A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

Description

FIELD OF THE INVENTION

[0003] The present invention relates to the field of data communications. In particular the present invention discloses methods and circuits for robust data recovery on a high-speed serial data link.

BACKGROUND OF THE INVENTION

[0004] As serial links are required to operate at higher frequencies and over longer distances, more sophisticated mechanisms have been adopted to recover data from more severely degraded signals. However, conventional serial transceiver systems have shortcomings. For example, a conventional transmitter uses a conventional current mode-driver whose speed is limited to 0.43/RC due to a passive pull-up resistor. Furthermore, if a Delay-Locked Loop (DLL) is used in a transmitter, special consideration must be made in designing a wide-range multi-phase DLL due to a so-called stuck problem.

[0005] In a conventional receiver system that uses using oversampling, the receiver Phase-Locked Loop (PLL) is locked to a reference clock rather than to the transmitted signal. In a tracked two-times (2×) oversampling receiver, two samples are made per bit, one for the data sampling and the other for edge tracking. Prior art Two-times (2×) sampling pulses are illustrated in FIG. 1B. The sampled bits are examined to determine whether to move the sampling clock phase earlier (UP) or later (DOWN). In a prior art receiver that uses two-times (2×) sampling, the decision is binary: either UP or DOWN. FIG. 1C illustrates the prior art number of UP and DOWN pulses issues 90 by a phase adjustment circuitry from the jitter of FIGS. 1A and 1B.

[0006] When a two-times (2×) sampling system has reached a locked state, the number of UP pulses is equal to the number of DOWN pulses. Thus, the phase adjustment circuitry tends to oscillate when it is in a locked steady state. Furthermore, in such a 2× sampling system, the clock edge for data sampling could be quite off from the optimum center point as illustrated in FIG. 1A. This misplacement of the sampling clock is due to the asymmetric nature of severe jitter as illustrated by the histogram in FIG. 1B, and is not desirable.

[0007] Also, a conventional tracked three-times (3×) oversampling phase detector raises several design problems due to long pumping pulses persisting for one Voltage Controlled Oscillator (VCO) cycle time. (See Inyeol Lee, et al. “A 622 Mb/s CMOS Clock Recovery PLL with Time-Interleaved Phase Detector Array,” ISSCC Digest of Technical papers, pp. 198-199, February 1996.)

[0008] For better jitter performance, the Phase-Locked Loop should have a structure that is more immune to power-supply noise. The Phase-Locked Loop should also contain a smaller number of possible noise sources.

[0009] Conventional Voltage Controlled Oscillators (VCOs) that use replica bias circuits are known to produce most of their jitter due to the noise in the bias voltage from the replica circuit. (See Ian A. Young, et al., “A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEE JSSC, vol. 27, pp. 1599-1607, Nov. 1992.) Due to these and other shortcomings of prior art transceiver systems, there is a need for an improved transceiver that provides robust clock and data recovery.

SUMMARY OF THE INVENTION

[0010] The present invention introduces a transceiver that performs three-times (3×) oversampling and dead zone detection in order to stabilize the voltage controlled oscillator (VCO) when the proper sampling frequency has been reached.

[0011] A delay locked loop apparatus, in accordance with the present invention, includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

[0012] The transceiver of the present invention incorporates a voltage-mode driver, on-chip mid-supply terminator, an analog multi-phase delay-locked loop (DLL), a tracked 3× oversampling technique with dead-zone phase detection, and a phase-locked loop (PLL) with folded starved-inverter delay cells. The implemented transceiver was proven to transmit and recover data at 2.5 GBaud over a 10 meter 150Ω Single-Twisted-Pair (STP) cable and at 1.25 GBaud over a 25 meter Single-Twisted-Pair (STP) cable with a Bit Error Rate (BER) of less than 10−13.

[0013] These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following detailed descriptions and a study of the various FIGS.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1A illustrates a prior art eye diagram for a received signal.

[0015] FIG. 1B illustrates a prior art asymmetric jitter distribution histogram for the signal of FIG. 1A and sampling clocks in a two-times (2×) oversampling receiver system.

[0016] FIG. 1C illustrates the prior art UP and DOWN pulses for a Voltage Controlled Oscillator from the signal of FIG. 1A.

[0017] FIG. 2 illustrates a simplified block diagram of a serial link transceiver, in accordance with the present invention.

[0018] FIG. 3 illustrates a more detailed block diagram of the transceiver device, in accordance with the present invention.

[0019] FIG. 4 illustrates a more detailed block diagram of the frequency comparator.

[0020] FIGS. 5A an 5B illustrates a schematic diagram of a DLL used in the present invention.

[0021] FIG. 5C illustrates a schematic diagram of a delay cell element used in the DLL of FIG. 3A.

[0022] FIG. 5D illustrates a schematic diagram of a current steering phase detectors used in the DLL of FIG. 5B.

[0023] FIG. 5E illustrates a timing diagram of the clock waveforms when the DLL of FIG. 4A is in a locked state.

[0024] FIG. 6A illustrates an eye diagram for a received signal.

[0025] FIG. 6B illustrates an asymmetric jitter distribution histogram for the signal of FIG. 5A and sampling clocks in a three-times (3×) oversampling receiver system.

[0026] FIG. 6C illustrates the UP and DOWN pulses for a Voltage Controlled Oscillator from the signal of FIG. 6A.

[0027] FIGS. 7A to 7E illustrate timing diagrams that cause various phase adjustments as set forth in Table 1.

[0028] FIG. 8 is a schematic diagram of a folded starved inverter with a supply regulator used in the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0029] A method and apparatus for implementing an oversampling transceiver with dead-zone phase detection is disclosed. In the following description, for purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. For example, certain teachings of the present invention have been described with reference to a phase-locked loop circuit in a data communication transceiver device. However, the signal phase comparison and locking techniques of the present invention can easily be applied to other types of phase-locked loop applications or in other applications that require a phase comparison.

Transceiver Architecture Overview

[0030] FIG. 2 illustrates a simplified block diagram of a serial link transceiver 100, in accordance with the present invention. Included is a 75 ohm cable-in 10, a receiver 100, a multi-phase DLL 130, a transmitter 180 and a 75 ohm cable-out 20. Also included is a comma detector 100.

[0031] FIG. 3 illustrates a more detailed block diagram of the transceiver device 100, in accordance with the present invention. The main components of the transceiver device 100 are the receiver 110 and the transmitter 180.

Transmitter Overview

[0032] The transmitter 180 of the transceiver device 100 illustrated in FIG. 3 is composed of a wide operating range multi-phase Delay-Locked Loop (DLL) 181, a serializer 185, and a voltage-mode driver 187. The voltage-mode driver 187 exhibits both active pull-up and active pull-down, and maintains its speed regardless of the cable impedance. Furthermore, the voltage-mode driver 187 can be AC coupled to a cable without any additional resistors.

[0033] A Delay-Locked Loop (DLL) 181 rather than a Phase-Locked Loop (PLL) is used in the transmitter 180 of the present invention to avoid jitter peaking which causes the jitter components near the bandwidth to be amplified rather than being suppressed when the receiver PLL has the similar bandwidth as the transmitter's. Since the Delay-Locked Loop (DLL) 181 has different frequency characteristics, such jitter peaking does not occur. The only concern is to build a Delay-Locked Loop (DLL) 181 with a wide frequency range, which will be explained below.

Receiver Overview

[0034] The receiver 110 of the transceiver device 100 illustrated in FIG. 3 is composed of on-chip termination resistor 111, oversamplers 120, a multi-phase Phase-Locked Loop (PLL) 130, a dead-zone phase detector 150, and a frequency comparator 160. The receiver Phase-Locked Loop (PLL) 130 tracks the transmitter clock frequency. Thus, clock recovery is accomplished in the Phase-Locked Loop 130.

[0035] The Voltage Controlled Oscillator 131 of the Phase-Locked Loop 130 produces a clock signal to have the oversamplers 120 sample the incoming signal at three-times (3×) the bit frequency.

[0036] While the digital Phase-Locked Loop 130 based 3× oversampling architecture has an inherent static sampling phase error up to ⅙ bit time and shows abrupt phase jump in the recovered clock due to phase quantization, the architecture of the present invention reduces such sampling error and avoids the phase jump in the presence of excessive amount of jitter in the data stream. Delay cells with a folded starved inverter configuration are used in the Voltage Controlled Oscillator (VCO) to exhibit less jitter and more tolerance against supply noise.

[0037] The dead-zone phase detector 150, of which detailed operation will be explained later, examines the sampled data and determines the direction of change for the Voltage Controlled Oscillator (VCO) 131 frequency. The dead-zone phase detector 150 is activated only after frequency lock is obtained when the external reference clock frequency and the Voltage Controlled Oscillator 131 frequency are within 200 ppm of each other.

[0038] The frequency comparator 160 is designed to have a hysteresis between its lock and unlock states in order to interact with the Phase-Locked Loop 130 in a compatible manner and to lock more robustly to the reference clock. Specifically, the frequency comparator 160 is deactivated when the external reference clock frequency and the Voltage Controlled Oscillator 131 frequency are within 200 ppm of each other, but the frequency comparator 160 is only reactivated when the external reference clock frequency and the Voltage Controlled Oscillator 131 are greater than 1000 ppm of each other.

[0039] FIG. 4 illustrates a more detailed block diagram of the frequency comparator 160. As previously stated, the frequency comparator has hysteresis between the lock and unlock conditions. A 16-bit binary counter 162 is updated at VCO-CLK cycle. A 14 bit divider 164 divides the Ref-CLK. Latch U2 samples the binary counter value at the divided Ref-CLK ridges. However, the Ref-CLK and VCO-CLK domains are asynchronous with each other. As a result, there is a possibility that the latch U2 will fall ino meta-stability when transmitted value changes on the sampling edge of the Ref-CLK. Since some bits have been changed while others have not at the sampling time, the sampled value can possibly be very different from the original value. To prevent this meta-stability problem, a binary-to-gray code converter 166 is inserted before the latching stage to allow only one bit to be inverted whenever the counter value is updated.

Other Transceiver Circuits

[0040] Referring back to FIG. 3, a comma detector 192 in the transceiver device 100 monitors the incoming data stream 30 to search for a K28.5 pattern in IBM 8B/10B coding for byte alignment. For ease of testing at the full speed, the transceiver device 100 includes an integrated Built-In Self Test (BIST) circuit 199. The Build-In Self Test (BIST) circuit includes Pseudo Random Bit Stream (PRBS) generation 40, verification (not shown), and Bit Error Rate (BER) counting logic (not shown).

DLL Design

[0041] FIGS. 5A-D illustrate the structure and operation of one embodiment of a Delay-Locked Loop (DLL) 181 circuit for the transceiver of FIG. 2. A new DLL architecture is shown to widen its range further in an architecture level.

[0042] FIG. 4A illustrates a Voltage-Controlled Delay Line (VCDL) circuit 201 that consists of 10 delay cell elements (210, 211, . . . 219) and generates the same number of clock outputs. FIG. 4B illustrates one possible embodiment of the internal structure of each delay cell element (210, 211, . . . 219).

[0043] For the main phase detector (PD) in FIG. 5B to work around the stuck and harmonic-lock problems, the initiai TVCDL value should satisfy the following inequality, as shown in equation I:

0.5×TCLK<TVCDL<1.5×TCLK   (EQUATION I)

[0044] where TCLK is the period of the reference clock.

[0045] However, the range of TVCDL is generally wider than the above restraint and the initial value of TVCDL is not known at the start-up time. To put the initial TVCDL within the range in the preceeding inequality (equation I), two Current Steering Phase Detectors (CSPDs) 50 and 60 are used. Specifically, FIG. 5B illustrates CSPD, 50 and CSPD2 60. Since the upper to lower current ratio is tuned to 3:1 as illustrated in FIG. 5C, Ref-CLK, CLK0, and CLK1 maintain the delay relationship illustrated in the timing diagram of FIG. 5E. It can be summarized in the following inequalities, as shown in equation II:

T DC <⅛×TCLK and 2×TDC>⅛×TCLK   (Equation II)

[0046] Or equivalently in terms of TVCDL, as shown in equation III:

⅝×TCLK<TVCDL<{fraction (5/4)}×TCLK (therefore TDC={fraction (1/10)}×TVCDL)   (Equation III)

[0047] where TDC is Ref-CLK to CLK0 delay and 2×TDC is Ref-CLK to CLK1 delay.

[0048] In such a locked state, the Q1 output from CSPD1 is ‘0’ and the Q2 output from CSPD2 is ‘1’ as illustrated in the timing diagram FIG. 5E. Thus, referring back to FIG. 5B, “gup” and “gdown” become ‘0’ and “glock” become ‘1’. Then, CP0 is disabled and PD1 is activated. Since inequality (equation III) satisfies inequality (equation I) in the control hand-over, the transition is smooth and PD1 removes the residual phase error between Ref-CLK and CLK9 without losing the lock:

[0049] PD2 (fine phase detector) is also activated and performs cell-level duty-cycle correction. In this manner, multi-phase clocks are made equally spaced with a 50% duty-cycle. The condition for correct Current Steering Phase Detector (CSPD) operation is as follows:

T DC.max (={fraction (1/10)}×TVCDL.max)<⅞×TCLK   (Equation IV)

[0050] This inequality determines the lower bound of the Delay-Locked Loop operating range as follows:

{fraction (4/35)}×TVCDL.max<TCLK≦TVCDL.max   (Equation V)

[0051] Thus, the theoretical operating frequency range of the circuit is 8.75:1, which is wide enough for many applications.

Dead Zone Phase Detection

[0052] In high bandwidth communication systems over a long distance, the receiver should be able to operate in the worst case when the total jitter of the incoming data signals is less than or equal to about 40% of a bit time. The total jitter is the sum of deterministic and random jitter. The deterministic jitter includes the effect of systematic variation of bit times and Inter-Symbol Interference (ISI). The deterministic jitter generally provides the major portion of the total jitter in a long copper cable.

[0053] When a receiver finally receives a signal that was transmitted over a long cable, the received signal is severely degraded. One specific type of degradation is jitter, a time-based distortion of the received signal. Jitter causes the signal transition time to vary. For example, FIGS. 1A and 6A illustrate an eye diagram of a signal 60 and 62 that has been degraded by jitter. Note that there is no clean signal transition edge 70 or 74 in FIGS. 1A and 6A.

[0054] FIGS. 1B and 6B illustrate a histogram of the jitter distribution 80 and 82 of the signals 60 and 62 in FIGS. 1A and 6A, respectively. Due to systematic variation of bit times and various other reasons, the jitter histograms are often found to be asymmetric and have a longer tail 80a and 82b in one direction.

[0055] The purpose of the phase detection in a receiver circuit is to have the sampling clock located at the middle of the “data eye” in the eye diagram 60 and 62 of FIGS. 1A and 6A. This will minimize the bit error rate when recovering data from a severely degraded signal.

3× Oversampling with Dead Zone Detection

[0056] The system of the present invention prevents such an oscillation at the locked state and optimizes the placement of the data-sampling clock. Specifically, the present invention introduces a tracked three-times (3×) oversampling with “dead-zone” detection. In the system of the present invention, only the extreme tail portions of the jitter histogram activate the phase adjustment circuitry. The edges located in the “dead-zone” (the middle portion of one-third of the bit time) are ignored for phase comparison. Thus, the phase adjustment circuit is active less often as illustrated in the UP and DOWN pulse diagram of FIG. 6C.

[0057] The dead-zone detection circuit may operate by comparing the bit values of two consecutive data samples and the two edge detection samples that occur between the two consecutive data samples. The following Table I provides a truth table of how the data edge bits. Table I can be viewed with reference to FIGS. 7A to 7E.

TABLE I
Data			Data		FIG-
N	Edge 1	Edge 2	N + 1	Phase Adjustment	URE
0	0	0	0	No Change (No Transition)
0	0	0	1	DOWN
0	0	1	0	No Change (No Transition)
0	0	1	1	No Change (Dead Zone)
0	1	0	0	No Change (No Transition)
0	1	0	1	Should not occur.
0	1	1	0	No Change (No Transition)
0	1	1	1	UP
1	0	0	0	UP
1	0	0	1	No Change (No Transition)
1	0	1	0	Should not occur.
1	0	1	1	No Change (No Transition)
1	1	0	0	No Change (Dead Zone)
1	1	0	1	No Change (No Transition)
1	1	1	0	DOWN
1	1	1	1	No Change (No Transition)

[0058] Since the data sampling points are driven toward the center of the data eye only with the worst-case edges, the operation of the 3× oversampling system with dead-zone detection is more robust in the presence of excessive jitter, where bit errors are more likely. Furthermore, the system of the present invention does better job of keeping the data sampling clock at the center of the data eye as illustrated by FIG. 6A.

[0059] Although the width of the dead-zone can be varied, simulation has proved that the dead-zone of one-third of a bit time offers quite adequate performance. Furthermore, a one-third of a bit time dead zone can be easily implemented with a 3× oversampling clock. Interestingly, the clock recovered from the data stream is expected to contain more jitter when the incoming serial data signal is clean. In such a case, the clock edges drift by up to one third of a bit time. However, the bit error rate is very low in such circumstances.

[0060] The design of the present invention reduces the pulse width to one bit time, thereby avoiding using an extremely small pumping current. Furthermore, due to the wide tolerance of the phase detection mechanism, the design of the present invention exhibits a wide frequency range operation without the pumping current control under PVT variations of PLL components.

PLL Design

[0061] FIG. 8 illustrates a schematic diagram of a folded starved inverter for use in the Voltage Controlled Oscillator (VCO) of one embodiment of the present invention. A cross-coupled PMOS pair is included to sharpen the transition edges of the output waveform regardless of the delay time. The inverters, G1 and G2, give more linearity to the VCO gain and its positive supply-sensitivity compensates the negative supply-sensitivity of the starved cell.

[0062] To reduce the effect of a power supply fluctuation further, a supply regulator 620 is added. Resistors and capacitors filter out the high frequency components of the 3.3V supply and provide a clean voltage to the gate of a NMOS source follower. Simulation results show that a VCO implemented according to FIG. 8 has about 10 times smaller supply sensitivity (0.23 ps/mV) and substrate sensitivity (0.26 ps/mV) and 15 dB less phase noise than a typical VCO.

Experimental Results

[0063] A prototype chip has been fabricated with a 0.25 μm CMOS process. The DLL operating range is 30 MHz to 250 MHz with less than 2% timing error among clock phases. Board level testing shows that the transceiver operates at 2.5 GBaud over a 10-meter 150Ω Single-Twisted-Pair (STP) cable and at 1.25 GBaud over a 25 meter Single-Twisted-Pair (STP) cable with 25% eye opening with no error detected for more than 3 hours (A Bit Error Rate (BER) of less than 10−13).

[0064] Due to the operation of the dead-zone phase detection circuit 150 of the present invention, the recovered clock jitter is actually reduced as the jitter increases in the serial data signals. In an extreme case at 1.25 GBaud, recovered clock jitter is reduced down to 28 ps, RMS when the signal jitter is 111 ps, RMS. On the other hand, when there is little jitter in the serial data signal, relatively large jitter of 40 ps, RMS is observed at the receiver but without any bit error.

[0065] When the Phase-Locked Loop 130 of the receiver 110 is locked to the reference clock at 187 MHz, the measured jitter is 5.5 ps, RMS and 35 ps, peak-to-peak. The following Table II summarizes the measured performance of the transceiver circuit as implemented in 0.25 μm CMOS semiconductor process technology.

TABLE II
Semiconductor Process		0.25 μm N-well 4-metal CMOS process
Supply voltage		2.5 V (core), 3.3 V (I/O)
DLL frequency range		30-250 MHz
Data rate range		0.6-2.6 GBaud
Area	Total	4.9 mm2
	DLL	0.1 mm2
	PLL	0.36 mm2
Power dissipation	Total	57.5 (mW/GBaud) × Data rate +
		125.5 (mW)
		(197 mW @ 1.25 GBaud,
		269 mW @ 2.5 GBaud
	DLL	16.8 mW @ 125 GBaud
	PLL	29.4 mW @ 1.25 GBaud
		(6.6 mW for VCO only)
Accumulated Jitter	Tx data	7.3 ps RMS/46 ps peak-to-peak
(with link activated)	DLL	6.0 ps RMS/40 ps peak-to-peak
(@ 1.87 GBaud)	PL	5.5 ps RMS/35 ps peak-to-peak
Bit Error Rate (BER)		<10−13 with a 10 m 150 Ω
		Single-Twisted-Pair
		(STP) cable @ 2.5 GBaud
		<10−13 with a 25 m 150 Ω
		Single-Twisted-Pair
		(STP) cable @ 12.5 GBaud

[0066] The foregoing has described a method and apparatus for implementing an oversampling transceiver with dead-zone phase detection. It is contemplated that changes and modifications may be made by one of ordinary skill in the art, to the materials and arrangements of elements of the present invention without departing from the scope of the invention.

Claims

1. A delay locked loop apparatus comprising: a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal; a second delay element to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal; and a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

2. The apparatus of claim 1 wherein the harmonic lock prevention circuit further comprises: a first current steering phase detector to receive the reference signal and the first delayed signal and to output a signal based on a state of the first delayed signal; a second current steering phase detector to receive the reference signal and the second delayed signal and to output a signal based on a state of the second delayed signal; and a delay time adjustment circuit to increase the delay time if the state of the first delayed signal is high, to decrease the delay time if the state of the second delayed signal is low, and to output a harmonic lock prevent signal if the state of the first signal is low and the state of the second signal is high.

3. The apparatus of claim 1 wherein the delay locked loop further comprises a residual phase error correction circuit to receive the harmonic lock prevented signal and to correct a residual phase error in the delayed signals.

4. The apparatus of claim 1 wherein a boundary of the predetermined range is less than an integer multiple of a period of the reference signal.

5. The apparatus of claim 1 wherein the predetermined range of the period of each delayed signal has a first boundary that is greater than one-half the period of the reference signal and a second boundary that is less than three-halves the period of the reference signal.

6. The apparatus of claim 1 wherein the first delay element further comprises six transistors.

7. The apparatus of claim 2 wherein the a first current steering phase detector comprises an NMOS tree of XNOR gates.